arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399

The pd_tcpc0 and pd_tcpc1 nodes are currently a sub node of pd_vio.
In the rk3399 TRM figure of the 'Power Domain Partition' and in the
table of 'Power Domain and Voltage Domain Summary' these power domains
are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
Link: https://lore.kernel.org/r/20200428203003.3318-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 492a35221d3d23d951bfe22f3c0297ec3f35fa4a..528dfe8eff36fc22e8414195ef662cee9d8ee83e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1056,6 +1056,16 @@
                                clocks = <&cru HCLK_SDIO>;
                                pm_qos = <&qos_sdioaudio>;
                        };
+                       pd_tcpc0@RK3399_PD_TCPD0 {
+                               reg = <RK3399_PD_TCPD0>;
+                               clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+                                        <&cru SCLK_UPHY0_TCPDPHY_REF>;
+                       };
+                       pd_tcpc1@RK3399_PD_TCPD1 {
+                               reg = <RK3399_PD_TCPD1>;
+                               clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+                                        <&cru SCLK_UPHY1_TCPDPHY_REF>;
+                       };
                        pd_usb3@RK3399_PD_USB3 {
                                reg = <RK3399_PD_USB3>;
                                clocks = <&cru ACLK_USB3>;
@@ -1088,16 +1098,6 @@
                                        pm_qos = <&qos_isp1_m0>,
                                                 <&qos_isp1_m1>;
                                };
-                               pd_tcpc0@RK3399_PD_TCPD0 {
-                                       reg = <RK3399_PD_TCPD0>;
-                                       clocks = <&cru SCLK_UPHY0_TCPDCORE>,
-                                                <&cru SCLK_UPHY0_TCPDPHY_REF>;
-                               };
-                               pd_tcpc1@RK3399_PD_TCPD1 {
-                                       reg = <RK3399_PD_TCPD1>;
-                                       clocks = <&cru SCLK_UPHY1_TCPDCORE>,
-                                                <&cru SCLK_UPHY1_TCPDPHY_REF>;
-                               };
                                pd_vo@RK3399_PD_VO {
                                        reg = <RK3399_PD_VO>;
                                        #address-cells = <1>;