arm: dts: r8a774b1: Import DTS queued for Linux 5.12-rc1

Update the RZ/G2N dtsi from Renesas repo destined to become 5.12-rc1.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi
index 23119c0..5b05474 100644 (file)
--- a/arch/arm/dts/r8a774b1.dtsi
+++ b/arch/arm/dts/r8a774b1.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for the r8a774b1 SoC
  *
- * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright (C) 2019 Renesas Electronics Corp.
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -282,7 +282,7 @@
                        resets = <&cpg 905>;
                };
 
-               pfc: pin-controller@e6060000 {
+               pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a774b1";
                        reg = <0 0xe6060000 0 0x50c>;
                };
@@ -709,6 +709,21 @@
                        status = "disabled";
                };
 
+               usb2_clksel: clock-controller@e6590630 {
+                       compatible = "renesas,r8a774b1-rcar-usb2-clock-sel",
+                                    "renesas,rcar-gen3-usb2-clock-sel";
+                       reg = <0 0xe6590630 0 0x02>;
+                       clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+                                <&usb_extal_clk>, <&usb3s0_clk>;
+                       clock-names = "ehci_ohci", "hs-usb-if",
+                                     "usb_extal", "usb_xtal";
+                       #clock-cells = <0>;
+                       power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+                       resets = <&cpg 703>, <&cpg 704>;
+                       reset-names = "ehci_ohci", "hs-usb-if";
+                       status = "disabled";
+               };
+
                usb_dmac0: dma-controller@e65a0000 {
                        compatible = "renesas,r8a774b1-usb-dmac",
                                     "renesas,usb-dmac";
@@ -989,6 +1004,8 @@
                        power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        phy-mode = "rgmii";
+                       rx-internal-delay-ps = <0>;
+                       tx-internal-delay-ps = <0>;
                        iommus = <&ipmmu_ds0 16>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -2158,6 +2175,23 @@
                        status = "disabled";
                };
 
+               rpc: spi@ee200000 {
+                       compatible = "renesas,r8a774b1-rpc-if",
+                                    "renesas,rcar-gen3-rpc-if";
+                       reg = <0 0xee200000 0 0x200>,
+                             <0 0x08000000 0 0x4000000>,
+                             <0 0xee208000 0 0x100>;
+                       reg-names = "regs", "dirmap", "wbuf";
+                       interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 917>;
+                       clock-names = "rpc";
+                       power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+                       resets = <&cpg 917>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                sata: sata@ee300000 {
                        compatible = "renesas,sata-r8a774b1",
                                     "renesas,rcar-gen3-sata";
@@ -2240,6 +2274,44 @@
                        status = "disabled";
                };
 
+               pciec0_ep: pcie-ep@fe000000 {
+                       compatible = "renesas,r8a774b1-pcie-ep",
+                                    "renesas,rcar-gen3-pcie-ep";
+                       reg = <0x0 0xfe000000 0 0x80000>,
+                             <0x0 0xfe100000 0 0x100000>,
+                             <0x0 0xfe200000 0 0x200000>,
+                             <0x0 0x30000000 0 0x8000000>,
+                             <0x0 0x38000000 0 0x8000000>;
+                       reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 319>;
+                       clock-names = "pcie";
+                       resets = <&cpg 319>;
+                       power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+                       status = "disabled";
+               };
+
+               pciec1_ep: pcie-ep@ee800000 {
+                       compatible = "renesas,r8a774b1-pcie-ep",
+                                    "renesas,rcar-gen3-pcie-ep";
+                       reg = <0x0 0xee800000 0 0x80000>,
+                             <0x0 0xee900000 0 0x100000>,
+                             <0x0 0xeea00000 0 0x200000>,
+                             <0x0 0xc0000000 0 0x8000000>,
+                             <0x0 0xc8000000 0 0x8000000>;
+                       reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+                       interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 318>;
+                       clock-names = "pcie";
+                       resets = <&cpg 318>;
+                       power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+                       status = "disabled";
+               };
+
                fdp1@fe940000 {
                        compatible = "renesas,fdp1";
                        reg = <0 0xfe940000 0 0x2400>;