armv8: lsch3: Enable WUO config for RNI-20 node

Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 41e1704..9c69ed1 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -18,6 +18,14 @@ ENTRY(lowlevel_init)
        mov     x29, lr                 /* Save LR */
 
 #ifdef CONFIG_FSL_LSCH3
+
+       /* Set Wuo bit for RN-I 20 */
+#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A)
+       ldr     x0, =CCI_AUX_CONTROL_BASE(20)
+       ldr     x1, =0x00000010
+       bl      ccn504_set_aux
+#endif
+
        /* Add fully-coherent masters to DVM domain */
        ldr     x0, =CCI_MN_BASE
        ldr     x1, =CCI_MN_RNF_NODEID_LIST

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 0ef7c9d..22f9c8f 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -91,6 +91,8 @@
 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
 
+#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
+
 /* TZ Protection Controller Definitions */
 #define TZPC_BASE                              0x02200000
 #define TZPCR0SIZE_BASE                                (TZPC_BASE)

diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S
index 7570c7b..1e07876 100644 (file)
--- a/arch/arm/lib/ccn504.S
+++ b/arch/arm/lib/ccn504.S
@@ -59,3 +59,24 @@ ENTRY(ccn504_set_qos)
        ret
 ENDPROC(ccn504_set_qos)
 
+/*************************************************************************
+ *
+ * void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value);
+ *
+ * Initialize AUX control settings
+ *
+ *************************************************************************/
+ENTRY(ccn504_set_aux)
+       /*
+        * x0: CCI_AUX_CONTROL_BASE
+        * x1: Value
+        */
+
+       ldr     x9, [x0]
+       mov     x10, x1
+       orr     x9, x9, x10
+       str     x9, [x0]
+
+       ret
+ENDPROC(ccn504_set_aux)
+