void GenContext::emitRead64Instruction(const SelectionInstruction &insn) {
const uint32_t elemNum = insn.extra.elem;
const uint32_t tmpRegSize = (p->curr.execWidth == 8) ? elemNum * 2 : elemNum;
- const GenRegister tempAddr = ra->genReg(insn.dst(0));
- const GenRegister dst = ra->genReg(insn.dst(tmpRegSize + 1));
- const GenRegister tmp = ra->genReg(insn.dst(1));
+ const GenRegister tempAddr = ra->genReg(insn.dst(tmpRegSize + 1));
+ const GenRegister dst = ra->genReg(insn.dst(tmpRegSize));
+ const GenRegister tmp = ra->genReg(insn.dst(0));
const GenRegister src = ra->genReg(insn.src(0));
const uint32_t bti = insn.extra.function;
p->READ64(dst, tmp, tempAddr, src, bti, elemNum);
SelectionVector *srcVector = this->appendVector();
SelectionVector *dstVector = this->appendVector();
- /* temporary addr register is to be modified, set it to dst registers.*/
- insn->dst(0) = tempAddr;
// Regular instruction to encode
for (uint32_t elemID = 0; elemID < elemNum; ++elemID)
- insn->dst(elemID + 1) = dst[elemID];
+ insn->dst(elemID) = dst[elemID];
+ /* temporary addr register is to be modified, set it to dst registers.*/
+ insn->dst(elemNum) = tempAddr;
insn->src(0) = addr;
insn->extra.function = bti;
insn->extra.elem = valueNum;
// Only the temporary registers need contiguous allocation
dstVector->regNum = elemNum - valueNum;
dstVector->isSrc = 0;
- dstVector->reg = &insn->dst(1);
+ dstVector->reg = &insn->dst(0);
// Source cannot be scalar (yet)
srcVector->regNum = 1;