};
};
-&dsi0 {
- vdda-supply = <&vreg_l3c_1p2>;
- status = "okay";
-};
-
-&dsi0_out {
- remote-endpoint = <&sn65dsi86_in>;
- data-lanes = <0 1 2 3>;
-};
-
-&dsi_phy {
- vdds-supply = <&vreg_l4a_0p8>;
- status = "okay";
-};
-
&i2c2 {
clock-frequency = <400000>;
status = "okay";
reg = <0>;
sn65dsi86_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
status = "okay";
};
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3c_1p2>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&sn65dsi86_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l4a_0p8>;
+ status = "okay";
+};
+
&pm6150_adc {
thermistor@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
};
};
-&dsi0 {
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
status = "okay";
vdda-supply = <&vreg_l3c_1p2>;
port {
panel0_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
};
-&dsi_phy {
+&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vreg_l4a_0p8>;
};
-&mdss {
- status = "okay";
-};
-
&qfprom {
vcc-supply = <&vreg_l11a_1p8>;
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
-&dsi0_out {
- remote-endpoint = <&ps8640_in>;
-};
-
edp_brij_i2c: &i2c2 {
status = "okay";
clock-frequency = <400000>;
port@0 {
reg = <0>;
ps8640_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
+&mdss_dsi0_out {
+ remote-endpoint = <&ps8640_in>;
+};
+
&tlmm {
edp_brij_ps8640_rst: edp-brij-ps8640-rst-state {
pins = "gpio11";
compatible = "google,quackingstick-sku1537", "qcom,sc7180";
};
-&dsi_phy {
+&mdss_dsi0_phy {
qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>;
qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>;
qcom,phy-drive-ldo-level = <375>;
};
};
-&dsi0 {
+&gpio_keys {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ap_ts: touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+ post-power-on-delay-ms = <20>;
+ hid-descr-addr = <0x0001>;
+
+ vdd-supply = <&pp3300_ts>;
+ };
+};
+
+&mdss_dsi0 {
panel: panel@0 {
/* Compatible will be filled in per-board */
reg = <0>;
port {
panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
};
-&gpio_keys {
- status = "okay";
-};
-
-&i2c4 {
- status = "okay";
- clock-frequency = <400000>;
-
- ap_ts: touchscreen@10 {
- compatible = "hid-over-i2c";
- reg = <0x10>;
- pinctrl-names = "default";
- pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
-
- interrupt-parent = <&tlmm>;
- interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
-
- post-power-on-delay-ms = <20>;
- hid-descr-addr = <0x0001>;
-
- vdd-supply = <&pp3300_ts>;
- };
-};
-
&sdhc_2 {
status = "okay";
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
-&dsi0_out {
- remote-endpoint = <&sn65dsi86_in>;
-};
-
edp_brij_i2c: &i2c2 {
status = "okay";
clock-frequency = <400000>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
+&mdss_dsi0_out {
+ remote-endpoint = <&sn65dsi86_in>;
+};
+
&tlmm {
edp_brij_irq: edp-brij-irq-state {
pins = "gpio11";
compatible = "google,wormdingler-sku1024", "qcom,sc7180";
};
-&dsi_phy {
+&mdss_dsi0_phy {
qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>;
qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>;
qcom,phy-drive-ldo-level = <450>;
};
};
-&dsi0 {
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ap_ts: touchscreen@1 {
+ compatible = "hid-over-i2c";
+ reg = <0x01>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_l>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+
+ post-power-on-delay-ms = <70>;
+ hid-descr-addr = <0x0001>;
+
+ vdd-supply = <&pp3300_ts>;
+ vddl-supply = <&pp1800_ts>;
+ };
+};
+
+&mdss_dsi0 {
panel: panel@0 {
reg = <0>;
port {
panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
};
-&i2c4 {
- status = "okay";
- clock-frequency = <400000>;
-
- ap_ts: touchscreen@1 {
- compatible = "hid-over-i2c";
- reg = <0x01>;
- pinctrl-names = "default";
- pinctrl-0 = <&ts_int_l>;
-
- interrupt-parent = <&tlmm>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
-
- post-power-on-delay-ms = <70>;
- hid-descr-addr = <0x0001>;
-
- vdd-supply = <&pp3300_ts>;
- vddl-supply = <&pp1800_ts>;
- };
-};
-
&pm6150_adc {
skin-temp-thermistor@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
status = "disabled";
};
-&dsi0 {
- status = "okay";
- vdda-supply = <&vdda_mipi_dsi0_1p2>;
-};
-
-&dsi0_out {
- data-lanes = <0 1 2 3>;
-};
-
-&dsi_phy {
- status = "okay";
- vdds-supply = <&vdda_mipi_dsi0_pll>;
-};
-
ap_sar_sensor_i2c: &i2c5 {
clock-frequency = <400000>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>;
};
+&mdss_dsi0 {
+ status = "okay";
+ vdda-supply = <&vdda_mipi_dsi0_1p2>;
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+};
+
&pm6150_adc {
charger-thermistor@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
};
};
- dsi0: dsi@ae94000 {
+ mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sc7180-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
- phys = <&dsi_phy>;
+ phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
- dsi0_in: endpoint {
+ mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
};
};
- dsi_phy: phy@ae94400 {
+ mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
<0 0x0ae94a00 0 0x1e0>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
+ reg-names = "dsi0_phy",
+ "dsi0_phy_lane",
"dsi_pll";
#clock-cells = <1>;
reg = <0 0x0af00000 0 0x200000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
- <&dsi_phy 0>,
- <&dsi_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>;
clock-names = "bi_tcxo",