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drm/radeon: set correct CE ram size for CIK
author
Jammy Zhou
<Jammy.Zhou@amd.com>
Mon, 3 Nov 2014 13:58:20 +0000
(08:58 -0500)
committer
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>
Fri, 21 Nov 2014 17:23:02 +0000
(09:23 -0800)
commit
dc4edad6530a9b7b66c3d905e2bc06021a05dcad
upstream.
CE ram size is 32k/0k/0k for GFX/CS0/CS1 with CIK
Ported from amdgpu driver.
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/radeon/cik.c
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diff --git
a/drivers/gpu/drm/radeon/cik.c
b/drivers/gpu/drm/radeon/cik.c
index
ab5c265
..
e94eb72
100644
(file)
--- a/
drivers/gpu/drm/radeon/cik.c
+++ b/
drivers/gpu/drm/radeon/cik.c
@@
-3936,8
+3936,8
@@
static int cik_cp_gfx_start(struct radeon_device *rdev)
/* init the CE partitions. CE only used for gfx on CIK */
radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
- radeon_ring_write(ring, 0x
c
000);
- radeon_ring_write(ring, 0x
c
000);
+ radeon_ring_write(ring, 0x
8
000);
+ radeon_ring_write(ring, 0x
8
000);
/* setup clear context state */
radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));