Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig
authorTom Rini <trini@konsulko.com>
Fri, 2 Dec 2022 21:42:40 +0000 (16:42 -0500)
committerTom Rini <trini@konsulko.com>
Thu, 22 Dec 2022 15:31:48 +0000 (10:31 -0500)
This converts the following to Kconfig:
   CONFIG_PEN_ADDR_BIG_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
arch/arm/Kconfig
arch/arm/cpu/armv7/ls102xa/Kconfig
include/configs/ls1021aiot.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h

index 8381e09..6e191e4 100644 (file)
@@ -1599,6 +1599,7 @@ config TARGET_LS1021AQDS
        select CPU_V7_HAS_NONSEC
        select CPU_V7_HAS_VIRT
        select LS1_DEEP_SLEEP
+       select PEN_ADDR_BIG_ENDIAN
        select SUPPORT_SPL
        select SYS_FSL_DDR
        select FSL_DDR_INTERACTIVE
@@ -1617,6 +1618,7 @@ config TARGET_LS1021ATWR
        select CPU_V7_HAS_NONSEC
        select CPU_V7_HAS_VIRT
        select LS1_DEEP_SLEEP
+       select PEN_ADDR_BIG_ENDIAN
        select SUPPORT_SPL
        select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
        select GPIO_EXTRA_HEADER
@@ -1681,6 +1683,7 @@ config TARGET_LS1021AIOT
        select CPU_V7A
        select CPU_V7_HAS_NONSEC
        select CPU_V7_HAS_VIRT
+       select PEN_ADDR_BIG_ENDIAN
        select SUPPORT_SPL
        select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
        select GPIO_EXTRA_HEADER
index 7e138e0..a83eb7e 100644 (file)
@@ -51,6 +51,9 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
+config PEN_ADDR_BIG_ENDIAN
+       bool
+
 config SYS_CCI400_OFFSET
        hex "Offset for CCI400 base"
        depends on SYS_FSL_HAS_CCI400
index 179c512..0e3ff3c 100644 (file)
@@ -68,7 +68,6 @@
 
 #define FSL_PCIE_COMPAT                "fsl,ls1021a-pcie"
 
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_SMP_PEN_ADDR            0x01ee0200
 
 #define HWCONFIG_BUFFER_SIZE           256
index fead9ed..76e7533 100644 (file)
  * MMC
  */
 
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_SMP_PEN_ADDR            0x01ee0200
 
 #define HWCONFIG_BUFFER_SIZE           256
index b07978a..281b26f 100644 (file)
 
 /* GPIO */
 
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_SMP_PEN_ADDR            0x01ee0200
 
 #define HWCONFIG_BUFFER_SIZE           256