vpp: optimize rgb screen convert coef [1/1]
authorMingLiang Dong <mingliang.dong@amlogic.com>
Fri, 28 Jun 2019 13:03:34 +0000 (21:03 +0800)
committerTao Zeng <tao.zeng@amlogic.com>
Mon, 8 Jul 2019 08:04:11 +0000 (01:04 -0700)
PD#TV-7280

Problem:
rgb screen pattern white balance data is a little high

Solution:
optimize convert coef

Verify:
verify on TL1

Change-Id: Iae1e8134d1a48fe0bbf206dd9b148c264951da2a
Signed-off-by: MingLiang Dong <mingliang.dong@amlogic.com>
arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
drivers/amlogic/media/video_sink/video.c

index 95fdefd..e771a9f 100644 (file)
                gamma_en = <1>;/*1:enabel ;0:disable*/
                wb_en = <1>;/*1:enabel ;0:disable*/
                cm_en = <1>;/*1:enabel ;0:disable*/
-               wb_sel = <1>;/*1:mtx ;0:gainoff*/
+               wb_sel = <0>;/*1:mtx ;0:gainoff*/
                vlock_en = <1>;/*1:enable;0:disable*/
                vlock_mode = <0x4>;
                /* vlock work mode:
index 41ca6e6..e5aece5 100644 (file)
                gamma_en = <1>;/*1:enabel ;0:disable*/
                wb_en = <1>;/*1:enabel ;0:disable*/
                cm_en = <1>;/*1:enabel ;0:disable*/
-               wb_sel = <1>;/*1:mtx ;0:gainoff*/
+               wb_sel = <0>;/*1:mtx ;0:gainoff*/
                vlock_en = <1>;/*1:enable;0:disable*/
                vlock_mode = <0x4>;
                /* vlock work mode:
index 57830db..6b0dc20 100644 (file)
                gamma_en = <1>;/*1:enabel ;0:disable*/
                wb_en = <1>;/*1:enabel ;0:disable*/
                cm_en = <1>;/*1:enabel ;0:disable*/
-               wb_sel = <1>;/*1:mtx ;0:gainoff*/
+               wb_sel = <0>;/*1:mtx ;0:gainoff*/
                vlock_en = <1>;/*1:enable;0:disable*/
                vlock_mode = <0x4>;
                /* vlock work mode:
index 8714b80..a26d0ae 100644 (file)
@@ -10955,7 +10955,7 @@ static u32 rgb2yuv(u32 rgb)
        int y, u, v;
 
        y = ((47*r + 157*g + 16*b + 128) >> 8) + 16;
-       u = ((-26*r - 87*g + 112*b + 128) >> 8) + 128;
+       u = ((-26*r - 87*g + 113*b + 128) >> 8) + 128;
        v = ((112*r - 102*g - 10*b + 128) >> 8) + 128;
 
        return  (y << 16) | (u << 8) | v;