#define SCRAMBLE_SEL 1
#define HYST_HDMI_TO_DVI 5
/* must = 0, other agilent source fail */
-#define HYST_DVI_TO_HDMI 0
+#define HYST_DVI_TO_HDMI 1
#define GCP_GLOBAVMUTE_EN 1 /* ag506 must clear this bit */
#define EDID_CLK_DIV 9 /* sys clk/(9+1) = 20M */
#define HDCP_KEY_WR_TRIES (5)
unsigned int i = 0;
unsigned int k = 0;
- hdmirx_wr_bits_dwc(DWC_HDCP_SETTINGS, HDCP_FAST_MODE, 0);
+ unsigned int data32 = 0;
+ /* I2C_SPIKE_SUPPR */
+ data32 |= 1 << 16;
+ /* FAST_I2C */
+ data32 |= 0 << 12;
+ /* ONE_DOT_ONE */
+ data32 |= 0 << 9;
+ /* FAST_REAUTH */
+ data32 |= 0 << 8;
+ /* DDC_ADDR */
+ data32 |= 0x3a << 1;
+ hdmirx_wr_dwc(DWC_HDCP_SETTINGS, data32);
+ /* hdmirx_wr_bits_dwc(DWC_HDCP_SETTINGS, HDCP_FAST_MODE, 0); */
/* Enable hdcp bcaps bit(bit7). In hdcp1.4 spec: Use of
* this bit is reserved, hdcp Receivers not capable of
* supporting HDMI must clear this bit to 0. For YAMAHA
void hdmirx_close_port(void)
{
- if (sm_pause)
- return;
+ /* if (sm_pause) */
+ /* return; */
/* External_Mute(1); */
}
case FSM_HPD_HIGH:
hpd_wait_cnt++;
if (rx_get_cur_hpd_sts() == 0) {
- if ((edid_update_flag) || (rx.boot_flag)) {
+ if (edid_update_flag) {
if (hpd_wait_cnt <= hpd_wait_max*10)
break;
} else {
if (hpd_wait_cnt <= hpd_wait_max)
break;
}
- rx.boot_flag = false;
}
hpd_wait_cnt = 0;
clk_unstable_cnt = 0;
break;
case FSM_WAIT_CLK_STABLE:
if (is_clk_stable()) {
- clk_unstable_cnt = 0;
+ if (clk_unstable_cnt != 0) {
+ rx_pr("wait clk cnt %d\n", clk_unstable_cnt);
+ clk_unstable_cnt = 0;
+ }
if (++clk_stable_cnt > clk_stable_max) {
rx.state = FSM_EQ_START;
clk_stable_cnt = 0;
* hpd reset once to recovery, to avoid
* recognition to DVI of low probability
*/
- if (rx.pre.sw_dvi && dvi_check_en) {
+ if (rx.pre.sw_dvi && dvi_check_en &&
+ (rx.hdcp.hdcp_version ==
+ HDCP_VER_NONE)) {
rx.state = FSM_HPD_LOW;
dvi_check_en = false;
break;
}
hpd_wait_cnt++;
if (rx_get_cur_hpd_sts() == 0) {
- if ((edid_update_flag) || (rx.boot_flag)) {
+ if (edid_update_flag) {
if (hpd_wait_cnt <= hpd_wait_max*10)
break;
} else {
if (hpd_wait_cnt <= hpd_wait_max)
break;
}
- rx.boot_flag = false;
}
hpd_wait_cnt = 0;
pre_port = rx.port;
}
sig_stable_cnt = 0;
sig_unstable_cnt = 0;
- if (rx.pre.sw_dvi && dvi_check_en) {
+ if (rx.pre.sw_dvi && dvi_check_en &&
+ (rx.hdcp.hdcp_version ==
+ HDCP_VER_NONE)) {
rx.state = FSM_HPD_LOW;
dvi_check_en = false;
break;
rx_pr("------------------\n");
rx_pr("Hdmirx version0: %s\n", RX_VER0);
rx_pr("Hdmirx version1: %s\n", RX_VER1);
+ rx_pr("Hdmirx version2: %s\n", RX_VER2);
rx_pr("------------------\n");
}
return 0;