2012-01-27 Richard Henderson <rth@redhat.com>
+ * config/m68k/m68k.c (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New.
+ * config/m68k/sync.md (atomic_test_and_set): Rename from
+ sync_test_and_setqi and adjust the operands.
+ (atomic_test_and_set_1): Rename from sync_test_and_setqi_1
+ and unconditionally enable.
+
+2012-01-27 Richard Henderson <rth@redhat.com>
+
* config/sparc/sparc.c (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New.
* config/sparc/sync.md (atomic_test_and_set): Only handle QImode.
(ldstub): Rename from ldstubqi.
#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
+/* The value stored by TAS. */
+#undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
+#define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
+
static const struct attribute_spec m68k_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
;; Elide the seq if operands[0] is dead.
"cas<sz> %1,%4,%2\;seq %0")
-(define_expand "sync_test_and_setqi"
- [(match_operand:QI 0 "register_operand" "")
- (match_operand:QI 1 "memory_operand" "")
- (match_operand:QI 2 "general_operand" "")]
- "!TARGET_CAS"
+(define_expand "atomic_test_and_set"
+ [(match_operand:QI 0 "register_operand" "") ;; bool success output
+ (match_operand:QI 1 "memory_operand" "") ;; memory
+ (match_operand:SI 2 "const_int_operand" "")] ;; model
+ ""
{
- if (operands[2] != const1_rtx)
- FAIL;
- emit_insn (gen_sync_test_and_setqi_1 (operands[0], operands[1]));
+ emit_insn (gen_atomic_test_and_set_1 (operands[0], operands[1]));
emit_insn (gen_negqi2 (operands[0], operands[0]));
DONE;
})
-(define_insn "sync_test_and_setqi_1"
+(define_insn "atomic_test_and_set_1"
[(set (match_operand:QI 0 "register_operand" "=d")
(unspec_volatile:QI
[(match_operand:QI 1 "memory_operand" "+m")]
UNSPECV_TAS_1))
(set (match_dup 1)
(unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))]
- "!TARGET_CAS"
+ ""
"tas %1\;sne %0")