drm/i915: introduce page_sizes field to dev_info
authorMatthew Auld <matthew.auld@intel.com>
Fri, 6 Oct 2017 22:18:16 +0000 (23:18 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Sat, 7 Oct 2017 09:11:44 +0000 (10:11 +0100)
In preparation for huge gtt pages expose page_sizes as part of the
device info, to indicate the page sizes supported by the HW.  Currently
only 4K is supported.

v2: s/page_size_mask/page_sizes/

v3: introduce I915_GTT_MAX_PAGE_SIZE

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006145041.21673-5-matthew.auld@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171006221833.32439-4-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem_gtt.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/selftests/mock_gem_device.c

index ec6f320..3d4dee8 100644 (file)
@@ -869,6 +869,8 @@ struct intel_device_info {
        u8 num_sprites[I915_MAX_PIPES];
        u8 num_scalers[I915_MAX_PIPES];
 
+       unsigned int page_sizes; /* page sizes supported by the HW */
+
 #define DEFINE_FLAG(name) u8 name:1
        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
index f62fb90..50218c1 100644 (file)
 #include "i915_gem_request.h"
 #include "i915_selftest.h"
 
-#define I915_GTT_PAGE_SIZE 4096UL
+#define I915_GTT_PAGE_SIZE_4K BIT(12)
+#define I915_GTT_PAGE_SIZE_64K BIT(16)
+#define I915_GTT_PAGE_SIZE_2M BIT(21)
+
+#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
+#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
+
 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
 
 #define I915_FENCE_REG_NONE -1
index 745b6a6..7938006 100644 (file)
        .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 
 /* Keep in gen based order, and chronological order within a gen */
+
+#define GEN_DEFAULT_PAGE_SIZES \
+       .page_sizes = I915_GTT_PAGE_SIZE_4K
+
 #define GEN2_FEATURES \
        .gen = 2, .num_pipes = 1, \
        .has_overlay = 1, .overlay_needs_physical = 1, \
@@ -67,6 +71,7 @@
        .ring_mask = RENDER_RING, \
        .has_snoop = true, \
        GEN_DEFAULT_PIPEOFFSETS, \
+       GEN_DEFAULT_PAGE_SIZES, \
        CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i830_info __initconst = {
@@ -100,6 +105,7 @@ static const struct intel_device_info intel_i865g_info __initconst = {
        .ring_mask = RENDER_RING, \
        .has_snoop = true, \
        GEN_DEFAULT_PIPEOFFSETS, \
+       GEN_DEFAULT_PAGE_SIZES, \
        CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i915g_info __initconst = {
@@ -163,6 +169,7 @@ static const struct intel_device_info intel_pineview_info __initconst = {
        .ring_mask = RENDER_RING, \
        .has_snoop = true, \
        GEN_DEFAULT_PIPEOFFSETS, \
+       GEN_DEFAULT_PAGE_SIZES, \
        CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i965g_info __initconst = {
@@ -205,6 +212,7 @@ static const struct intel_device_info intel_gm45_info __initconst = {
        .ring_mask = RENDER_RING | BSD_RING, \
        .has_snoop = true, \
        GEN_DEFAULT_PIPEOFFSETS, \
+       GEN_DEFAULT_PAGE_SIZES, \
        CURSOR_OFFSETS
 
 static const struct intel_device_info intel_ironlake_d_info __initconst = {
@@ -228,6 +236,7 @@ static const struct intel_device_info intel_ironlake_m_info __initconst = {
        .has_rc6p = 1, \
        .has_aliasing_ppgtt = 1, \
        GEN_DEFAULT_PIPEOFFSETS, \
+       GEN_DEFAULT_PAGE_SIZES, \
        CURSOR_OFFSETS
 
 #define SNB_D_PLATFORM \
@@ -271,6 +280,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst =
        .has_aliasing_ppgtt = 1, \
        .has_full_ppgtt = 1, \
        GEN_DEFAULT_PIPEOFFSETS, \
+       GEN_DEFAULT_PAGE_SIZES, \
        IVB_CURSOR_OFFSETS
 
 #define IVB_D_PLATFORM \
@@ -327,6 +337,7 @@ static const struct intel_device_info intel_valleyview_info __initconst = {
        .has_snoop = true,
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
        .display_mmio_offset = VLV_DISPLAY_BASE,
+       GEN_DEFAULT_PAGE_SIZES,
        GEN_DEFAULT_PIPEOFFSETS,
        CURSOR_OFFSETS
 };
@@ -365,6 +376,7 @@ static const struct intel_device_info intel_haswell_gt3_info __initconst = {
 #define GEN8_FEATURES \
        G75_FEATURES, \
        BDW_COLORS, \
+       GEN_DEFAULT_PAGE_SIZES, \
        .has_logical_ring_contexts = 1, \
        .has_full_48bit_ppgtt = 1, \
        .has_64bit_reloc = 1, \
@@ -417,13 +429,18 @@ static const struct intel_device_info intel_cherryview_info __initconst = {
        .has_reset_engine = 1,
        .has_snoop = true,
        .display_mmio_offset = VLV_DISPLAY_BASE,
+       GEN_DEFAULT_PAGE_SIZES,
        GEN_CHV_PIPEOFFSETS,
        CURSOR_OFFSETS,
        CHV_COLORS,
 };
 
+#define GEN9_DEFAULT_PAGE_SIZES \
+       .page_sizes = I915_GTT_PAGE_SIZE_4K
+
 #define GEN9_FEATURES \
        GEN8_FEATURES, \
+       GEN9_DEFAULT_PAGE_SIZES, \
        .has_logical_ring_preemption = 1, \
        .has_csr = 1, \
        .has_guc = 1, \
@@ -486,6 +503,7 @@ static const struct intel_device_info intel_skylake_gt4_info __initconst = {
        .has_reset_engine = 1, \
        .has_snoop = true, \
        .has_ipc = 1, \
+       GEN9_DEFAULT_PAGE_SIZES, \
        GEN_DEFAULT_PIPEOFFSETS, \
        IVB_CURSOR_OFFSETS, \
        BDW_COLORS
index e189d2b..f46c3a3 100644 (file)
@@ -174,6 +174,9 @@ struct drm_i915_private *mock_gem_device(void)
 
        mkwrite_device_info(i915)->gen = -1;
 
+       mkwrite_device_info(i915)->page_sizes =
+               I915_GTT_PAGE_SIZE_4K;
+
        spin_lock_init(&i915->mm.object_stat_lock);
        mock_uncore_init(i915);