#define DM_DIG_HIGH_PWR_THRESH_HIGH 75
#define DM_DIG_HIGH_PWR_THRESH_LOW 70
-#define DM_DIG_MIN_Netcore 0x12
+#define DM_DIG_MIN_NETCORE 0x12
void rtl92s_dm_watchdog(struct ieee80211_hw *hw);
void rtl92s_dm_init(struct ieee80211_hw *hw);
return true;
}
-void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 Mode)
+void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
{
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
struct h2c_set_pwrmode_parm pwrmode;
u16 max_wakeup_period = 0;
- pwrmode.mode = Mode;
+ pwrmode.mode = mode;
pwrmode.flag_low_traffic_en = 0;
pwrmode.flag_lpnav_en = 0;
pwrmode.flag_rf_low_snr_en = 0;
H2C_JOINBSS_CMD,
H2C_DISCONNECT_CMD, /*15*/
H2C_CREATEBSS_CMD,
- H2C_SETOPMode_CMD,
+ H2C_SETOPMODE_CMD,
H2C_SITESURVEY_CMD,
H2C_SETAUTH_CMD,
H2C_SETKEY_CMD, /*20*/
/* The following macros are used for FW
* CMD map and parameter updated. */
-#define FW_CMD_IO_CLR(rtlpriv, _Bit) \
+#define FW_CMD_IO_CLR(rtlpriv, _bit) \
do { \
udelay(1000); \
- rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \
+ rtlpriv->rtlhal.fwcmd_iomap &= (~_bit); \
} while (0)
#define FW_CMD_IO_UPDATE(rtlpriv, _val) \
union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
mac->ac[0].aifs));
u8 acm = p_aci_aifsn->f.acm;
- u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
+ u8 acm_ctrl = rtl_read_byte(rtlpriv, ACMHWCTRL);
acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
0x0 : 0x1);
if (acm) {
switch (e_aci) {
case AC0_BE:
- acm_ctrl |= AcmHw_BeqEn;
+ acm_ctrl |= ACMHW_BEQEN;
break;
case AC2_VI:
- acm_ctrl |= AcmHw_ViqEn;
+ acm_ctrl |= ACMHW_VIQEN;
break;
case AC3_VO:
- acm_ctrl |= AcmHw_VoqEn;
+ acm_ctrl |= ACMHW_VOQEN;
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
} else {
switch (e_aci) {
case AC0_BE:
- acm_ctrl &= (~AcmHw_BeqEn);
+ acm_ctrl &= (~ACMHW_BEQEN);
break;
case AC2_VI:
- acm_ctrl &= (~AcmHw_ViqEn);
+ acm_ctrl &= (~ACMHW_VIQEN);
break;
case AC3_VO:
- acm_ctrl &= (~AcmHw_VoqEn);
+ acm_ctrl &= (~ACMHW_VOQEN);
break;
default:
pr_err("switch case %#x not processed\n",
RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
"HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
- rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
+ rtl_write_byte(rtlpriv, ACMHWCTRL, acm_ctrl);
break;
}
case HW_VAR_RCR:{
/* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
/* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
/* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
- /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
+ /* 13. Test mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
/* 14. Set driver info, we only accept PHY status now. */
rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
rtl92se_enable_interrupt(hw);
}
-static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
+static void _rtl8192se_get_ic_inferiority(struct ieee80211_hw *hw)
{
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
if (rtlefuse->autoload_failflag)
return;
- _rtl8192se_get_IC_Inferiority(hw);
+ _rtl8192se_get_ic_inferiority(hw);
/* Read IC Version && Channel Plan */
/* VID, DID SE 0xA-D */
RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
bool rtstatus;
- u32 InitializeCount = 0;
+ u32 initializecount = 0;
do {
- InitializeCount++;
+ initializecount++;
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
"IPS Set eRf nic enable\n");
rtstatus = rtl_ps_enable_nic(hw);
- } while (!rtstatus && (InitializeCount < 10));
+ } while (!rtstatus && (initializecount < 10));
RT_CLEAR_PS_LEVEL(ppsc,
RT_RF_OFF_LEVL_HALT_NIC);
if (!rtstatus) {
pr_err("Write BB Reg Fail!!\n");
- goto phy_BB8190_Config_ParaFile_Fail;
+ goto phy_bb8190_config_parafile_fail;
}
/* 2. If EEPROM or EFUSE autoload OK, We must config by
}
if (!rtstatus) {
pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
- goto phy_BB8190_Config_ParaFile_Fail;
+ goto phy_bb8190_config_parafile_fail;
}
/* 3. BB AGC table Initialization */
if (!rtstatus) {
pr_err("%s(): AGC Table Fail\n", __func__);
- goto phy_BB8190_Config_ParaFile_Fail;
+ goto phy_bb8190_config_parafile_fail;
}
/* Check if the CCK HighPower is turned ON. */
rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
RFPGA0_XA_HSSIPARAMETER2, 0x200));
-phy_BB8190_Config_ParaFile_Fail:
+phy_bb8190_config_parafile_fail:
return rtstatus;
}
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 i;
u32 arraylength;
- u32 *ptraArray;
+ u32 *ptrarray;
arraylength = MAC_2T_ARRAYLENGTH;
- ptraArray = rtl8192semac_2t_array;
+ ptrarray = rtl8192semac_2t_array;
for (i = 0; i < arraylength; i = i + 2)
- rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
+ rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
return true;
}
}
static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
- u8 *cckpowerlevel, u8 *ofdmpowerLevel)
+ u8 *cckpowerlevel, u8 *ofdmpowerlevel)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
/* 2. OFDM for 1T or 2T */
if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
/* Read HT 40 OFDM TX power */
- ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
- ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
+ ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
+ ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
} else if (rtlphy->rf_type == RF_2T2R) {
/* Read HT 40 OFDM TX power */
- ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
- ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
+ ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
+ ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
} else {
- ofdmpowerLevel[0] = 0;
- ofdmpowerLevel[1] = 0;
+ ofdmpowerlevel[0] = 0;
+ ofdmpowerlevel[1] = 0;
}
}
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
/* [0]:RF-A, [1]:RF-B */
- u8 cckpowerlevel[2], ofdmpowerLevel[2];
+ u8 cckpowerlevel[2], ofdmpowerlevel[2];
if (!rtlefuse->txpwr_fromeprom)
return;
* 1. For CCK.
* 2. For OFDM 1T or 2T */
_rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
- &ofdmpowerLevel[0]);
+ &ofdmpowerlevel[0]);
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
channel, cckpowerlevel[0], cckpowerlevel[1],
- ofdmpowerLevel[0], ofdmpowerLevel[1]);
+ ofdmpowerlevel[0], ofdmpowerlevel[1]);
_rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
- &ofdmpowerLevel[0]);
+ &ofdmpowerlevel[0]);
rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
- rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
+ rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel);
}
#define BCNTCFG 0x01E0
#define CWRR 0x01E2
#define ACMAVG 0x01E4
-#define AcmHwCtrl 0x01E7
+#define ACMHWCTRL 0x01E7
#define VO_ADMTM 0x01E8
#define VI_ADMTM 0x01EC
#define BE_ADMTM 0x01F0
#define INTA_MASK 0x0300
#define ISR 0x0308
-/* 13. Test Mode and Debug Control Registers */
+/* 13. Test mode and Debug Control Registers */
#define DBG_PORT_SWITCH 0x003A
#define BIST 0x0310
#define DBS 0x0314
#define SYS_SWHW_SEL BIT(14)
#define SYS_FWHW_SEL BIT(15)
-#define CmdEEPROM_En BIT(5)
-#define CmdEERPOMSEL BIT(4)
-#define Cmd9346CR_9356SEL BIT(4)
+#define CMDEEPROM_EN BIT(5)
+#define CMDEERPOMSEL BIT(4)
+#define CMD9346CR_9356SEL BIT(4)
#define AFE_MBEN BIT(1)
#define AFE_BGEN BIT(0)
#define APLL_EN BIT(0)
-#define AFR_CardBEn BIT(0)
+#define AFR_CARDBEN BIT(0)
#define AFR_CLKRUN_SEL BIT(1)
-#define AFR_FuncRegEn BIT(2)
+#define AFR_FUNCREGEN BIT(2)
#define APSDOFF_STATUS BIT(15)
#define APSDOFF BIT(14)
#define HCI_RXDMA_EN BIT(3)
#define HCI_TXDMA_EN BIT(2)
-#define StopHCCA BIT(6)
-#define StopHigh BIT(5)
-#define StopMgt BIT(4)
-#define StopVO BIT(3)
-#define StopVI BIT(2)
-#define StopBE BIT(1)
-#define StopBK BIT(0)
+#define STOPHCCA BIT(6)
+#define STOPHIGH BIT(5)
+#define STOPMGT BIT(4)
+#define STOPVO BIT(3)
+#define STOPVI BIT(2)
+#define STOPBE BIT(1)
+#define STOPBK BIT(0)
#define LBK_NORMAL 0x00
#define LBK_MAC_LB (BIT(0) | BIT(1) | BIT(3))
#define TXDMAPRE2FULL BIT(23)
#define DISCW BIT(20)
#define TCRICV BIT(19)
-#define CfendForm BIT(17)
+#define cfendform BIT(17)
#define TCRCRC BIT(16)
#define FAKE_IMEM_EN BIT(15)
#define TSFRST BIT(9)
#define RRSR_MCS5 BIT(17)
#define RRSR_MCS6 BIT(18)
#define RRSR_MCS7 BIT(19)
-#define BRSR_AckShortPmb BIT(23)
+#define BRSR_ACKSHORTPMB BIT(23)
#define RATR_1M 0x00000001
#define RATR_2M 0x00000002
#define AC_PARAM_ECW_MIN_OFFSET 8
#define AC_PARAM_AIFS_OFFSET 0
-#define AcmHw_HwEn BIT(0)
-#define AcmHw_BeqEn BIT(1)
-#define AcmHw_ViqEn BIT(2)
-#define AcmHw_VoqEn BIT(3)
-#define AcmHw_BeqStatus BIT(4)
-#define AcmHw_ViqStatus BIT(5)
-#define AcmHw_VoqStatus BIT(6)
+#define ACMHW_HWEN BIT(0)
+#define ACMHW_BEQEN BIT(1)
+#define ACMHW_VIQEN BIT(2)
+#define ACMHW_VOQEN BIT(3)
+#define ACMHW_BEQSTATUS BIT(4)
+#define ACMHW_VIQSTATUS BIT(5)
+#define ACMHW_VOQSTATUS BIT(6)
#define RETRY_LIMIT_SHORT_SHIFT 8
#define RETRY_LIMIT_LONG_SHIFT 0
#define TCR_SAT BIT(24)
#define RCR_MXDMA_OFFSET 8
#define RCR_FIFO_OFFSET 13
-#define RCR_OnlyErlPkt BIT(31)
+#define RCR_ONLYERLPKT BIT(31)
#define CWR 0xDC
#define RETRYCTR 0xDE
projects / platform / kernel / linux-rpi.git / commitdiff