FSL DDR: Add 85xx specific register setting

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index d51a6dd..3a3c6a7 100644 (file)
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -34,6 +34,25 @@ SOBJS        = $(SOBJS-y)
 COBJS-$(CONFIG_MP) += mp.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
+# supports ddr1
+ifeq ($(CONFIG_FSL_DDR1),y)
+COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
+endif
+
+# supports ddr1/2
+ifeq ($(CONFIG_FSL_DDR2),y)
+COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
+COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
+COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
+
+# supports ddr1/2/3
+COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
+COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
+endif
+
 ifneq ($(CONFIG_FSL_DDR3),y)
 ifneq ($(CONFIG_FSL_DDR2),y)
 ifneq ($(CONFIG_FSL_DDR1),y)

diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
new file mode 100644 (file)
index 0000000..2c11ee4
--- /dev/null
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+                            unsigned int ctrl_num)
+{
+       unsigned int i;
+       volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+
+       if (ctrl_num != 0) {
+               printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+               return;
+       }
+
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               if (i == 0) {
+                       out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs0_config, regs->cs[i].config);
+
+               } else if (i == 1) {
+                       out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs1_config, regs->cs[i].config);
+
+               } else if (i == 2) {
+                       out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs2_config, regs->cs[i].config);
+
+               } else if (i == 3) {
+                       out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs3_config, regs->cs[i].config);
+               }
+       }
+
+       out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+       out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+       out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+       out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
+       out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+#endif
+
+       /*
+        * 200 painful micro-seconds must elapse between
+        * the DDR clock setup and the DDR config enable.
+        */
+       udelay(200);
+       asm volatile("sync;isync");
+
+       out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+       asm("sync;isync;msync");
+       udelay(500);
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void dma_init(void);
+extern uint dma_check(void);
+extern int dma_xfer(void *dest, uint count, void *src);
+
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+       uint *p = 0;
+       uint i = 0;
+       volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+
+       dma_init();
+
+       for (*p = 0; p < (uint *)(8 * 1024); p++) {
+               if (((unsigned int)p & 0x1f) == 0) {
+                       ppcDcbz((unsigned long) p);
+               }
+               *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
+               if (((unsigned int)p & 0x1c) == 0x1c) {
+                       ppcDcbf((unsigned long) p);
+               }
+       }
+
+       dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
+       dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
+       dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
+       dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
+       dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
+       dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
+       dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
+       dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+       dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+       dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
+
+       for (i = 1; i < dram_size / 0x800000; i++) {
+               dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
+       }
+
+       /*
+        * Enable errors for ECC.
+        */
+       debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
+       ddr->err_disable = 0x00000000;
+       asm("sync;isync;msync");
+       debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
+}
+
+#endif /* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */

diff --git a/cpu/mpc85xx/ddr-gen2.c b/cpu/mpc85xx/ddr-gen2.c
new file mode 100644 (file)
index 0000000..130090c
--- /dev/null
+++ b/cpu/mpc85xx/ddr-gen2.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+                            unsigned int ctrl_num)
+{
+       unsigned int i;
+       volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+
+       if (ctrl_num) {
+               printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+               return;
+       }
+
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               if (i == 0) {
+                       out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs0_config, regs->cs[i].config);
+
+               } else if (i == 1) {
+                       out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs1_config, regs->cs[i].config);
+
+               } else if (i == 2) {
+                       out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs2_config, regs->cs[i].config);
+
+               } else if (i == 3) {
+                       out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs3_config, regs->cs[i].config);
+               }
+       }
+
+       out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+       out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+       out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+       out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+       out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+       out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+       out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+       out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+       out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+       out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+       out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+       out_be32(&ddr->init_addr, regs->ddr_init_addr);
+       out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+       /*
+        * 200 painful micro-seconds must elapse between
+        * the DDR clock setup and the DDR config enable.
+        */
+       udelay(200);
+       asm volatile("sync;isync");
+
+       out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+       /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
+       while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+               udelay(10000);          /* throttle polling rate */
+       }
+}

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
new file mode 100644 (file)
index 0000000..d7cc9db
--- /dev/null
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+                            unsigned int ctrl_num)
+{
+       unsigned int i;
+       volatile ccsr_ddr_t *ddr;
+
+       switch (ctrl_num) {
+       case 0:
+               ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+               break;
+       case 1:
+               ddr = (void *)CFG_MPC85xx_DDR2_ADDR;
+               break;
+       default:
+               printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+               return;
+       }
+
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               if (i == 0) {
+                       out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs0_config, regs->cs[i].config);
+                       out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+               } else if (i == 1) {
+                       out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs1_config, regs->cs[i].config);
+                       out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+               } else if (i == 2) {
+                       out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs2_config, regs->cs[i].config);
+                       out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+               } else if (i == 3) {
+                       out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs3_config, regs->cs[i].config);
+                       out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
+               }
+       }
+
+       out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+       out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+       out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+       out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+       out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+       out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+       out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+       out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+       out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+       out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+       out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+       out_be32(&ddr->init_addr, regs->ddr_init_addr);
+       out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+       out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+       out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+       out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+       out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+       out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
+       out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+       out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+       out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+
+       /*
+        * 32-bit workaround for DDR2
+        * 32_BE
+        */
+       if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
+           && in_be32(&ddr->sdram_cfg_2) & 0x80000) {
+               /* set DEBUG_1[31] */
+               u32 temp = in_be32(&ddr->debug_1);
+               out_be32(&ddr->debug_1, temp | 1);
+       }
+
+       /*
+        * 200 painful micro-seconds must elapse between
+        * the DDR clock setup and the DDR config enable.
+        */
+       udelay(200);
+       asm volatile("sync;isync");
+
+       out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+       /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
+       while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+               udelay(10000);          /* throttle polling rate */
+       }
+}