vout: update viu config when change display mode

PD#156734: vout: update viu config when change display mode
also clearup related reg settings in hdmitx/cvbsout/lcd.

Change-Id: I196363d6caaf7158c8e167fb8ca1353c74913263
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_out.c b/drivers/amlogic/media/vout/cvbs/cvbs_out.c
index 5961223..3d0cf2d 100644 (file)
--- a/drivers/amlogic/media/vout/cvbs/cvbs_out.c
+++ b/drivers/amlogic/media/vout/cvbs/cvbs_out.c
@@ -548,7 +548,6 @@ static int cvbs_set_current_vmode(enum vmode_e mode)
                      tvmode, info->vinfo->sync_duration_den,
                      info->vinfo->sync_duration_num);
 
-       cvbs_out_reg_write(VPP_POSTBLEND_H_SIZE, info->vinfo->width);
        if (mode & VMODE_INIT_BIT_MASK) {
                cvbs_out_vpu_power_ctrl(1);
                cvbs_out_clk_gate_ctrl(1);

diff --git a/drivers/amlogic/media/vout/cvbs/cvbsregs.h b/drivers/amlogic/media/vout/cvbs/cvbsregs.h
index 10d2a84..abd4a34 100644 (file)
--- a/drivers/amlogic/media/vout/cvbs/cvbsregs.h
+++ b/drivers/amlogic/media/vout/cvbs/cvbsregs.h
@@ -227,7 +227,6 @@ static const struct reg_s cvbsregs_480cvbs_enc[] = {
        {VENC_VDAC_DACSEL3,            0x0000,},
        {VENC_VDAC_DACSEL4,            0x0000,},
        {VENC_VDAC_DACSEL5,            0x0000,},
-       {VPU_VIU_VENC_MUX_CTRL,        0x0005,},
        {VENC_VDAC_FIFO_CTRL,          0x2000,},
        {ENCI_DACSEL_0,                0x0011 },
        {ENCI_DACSEL_1,                0x11   },
@@ -278,7 +277,6 @@ static const struct reg_s cvbsregs_576cvbs_enc[] = {
        {VENC_VDAC_DACSEL3,               0x0000,    },
        {VENC_VDAC_DACSEL4,               0x0000,    },
        {VENC_VDAC_DACSEL5,               0x0000,    },
-       {VPU_VIU_VENC_MUX_CTRL,           0x0005,    },
        {VENC_VDAC_FIFO_CTRL,             0x2000,    },
        {ENCI_DACSEL_0,                   0x0011     },
        {ENCI_DACSEL_1,                   0x11       },

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
index 5cc26db..d81b7ed 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
@@ -70,7 +70,6 @@ static const struct reg_s tvregs_720p[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_VSO_ELINE, 5},
        {P_ENCP_VIDEO_MAX_LNCNT, 749},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -106,7 +105,6 @@ static const struct reg_s tvregs_720p_50hz[] = {
        {P_ENCP_VIDEO_MODE_ADV, 0x0019},
        {P_ENCP_VIDEO_SYNC_MODE, 0x407},
        {P_ENCP_VIDEO_YC_DLY, 0},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -132,7 +130,6 @@ static const struct reg_s tvregs_480i[] = {
        {P_ENCI_SYNC_MODE, 0x07},
        {P_ENCI_DBG_PX_RST, 0},
        {P_ENCI_VFIFO2VD_CTL, 0x4e01},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0x5},
        {P_ENCI_VFIFO2VD_PIXEL_START, 0xf3,},
        {P_ENCI_VFIFO2VD_PIXEL_END, 0x0693,},
        {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x12,},
@@ -175,7 +172,6 @@ static const struct reg_s tvregs_480p[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_SY_VAL, 8},
        {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_DACSEL_0, 0x3102},
        {P_ENCP_DACSEL_1, 0x0054},
        {P_ENCI_VIDEO_EN, 0},
@@ -208,7 +204,6 @@ static const struct reg_s tvregs_576i[] = {
        {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
        {P_ENCI_DBG_PX_RST, 0},
        {P_ENCI_VFIFO2VD_CTL, 0x4e01},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0x5},
        {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b},
        {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab},
        {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016},
@@ -251,7 +246,6 @@ static const struct reg_s tvregs_576p[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_SY_VAL, 8},
        {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
@@ -291,7 +285,6 @@ static const struct reg_s tvregs_1080i[] = {
        {P_ENCP_VIDEO_MODE, 0x5ffc},
        {P_ENCP_VIDEO_MODE_ADV, 0x0019},
        {P_ENCP_VIDEO_SYNC_MODE, 0x207},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
@@ -327,7 +320,6 @@ static const struct reg_s tvregs_1080i_50hz[] = {
        {P_ENCP_VIDEO_MODE, 0x5ffc},
        {P_ENCP_VIDEO_MODE_ADV, 0x0019},
        {P_ENCP_VIDEO_SYNC_MODE, 0x7},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
@@ -361,7 +353,6 @@ static const struct reg_s tvregs_1080p[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_VSO_ELINE, 5},
        {P_ENCP_VIDEO_MAX_LNCNT, 1124},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_VENC_VIDEO_PROG_MODE, 0x100},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
@@ -396,7 +387,6 @@ static const struct reg_s tvregs_1080p_30hz[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_VSO_ELINE, 5},
        {P_ENCP_VIDEO_MAX_LNCNT, 1124},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_VENC_VIDEO_PROG_MODE, 0x100},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
@@ -436,7 +426,6 @@ static const struct reg_s tvregs_1080p_50hz[] = {
        {P_ENCP_VIDEO_SYNC_MODE, 0x7},
        {P_ENCP_VIDEO_YC_DLY, 0},
        {P_ENCP_VIDEO_RGB_CTRL, 2},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
@@ -476,7 +465,6 @@ static const struct reg_s tvregs_1080p_24hz[] = {
        {P_ENCP_VIDEO_SYNC_MODE, 0x7},
        {P_ENCP_VIDEO_YC_DLY, 0},
        {P_ENCP_VIDEO_RGB_CTRL, 2},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
        {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
@@ -509,7 +497,6 @@ static const struct reg_s tvregs_4k2k_30hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -542,7 +529,6 @@ static const struct reg_s tvregs_4k2k_25hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -575,7 +561,6 @@ static const struct reg_s tvregs_4k2k_24hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -608,7 +593,6 @@ static const struct reg_s tvregs_4k2k_smpte[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -631,7 +615,6 @@ static const struct reg_s tvregs_4k2k_smpte_25hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -654,7 +637,6 @@ static const struct reg_s tvregs_4k2k_smpte_30hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -677,7 +659,6 @@ static const struct reg_s tvregs_4k2k_smpte_50hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
@@ -700,7 +681,6 @@ static const struct reg_s tvregs_4k2k_smpte_60hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index d3719ed..ed5c91a 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -1871,18 +1871,8 @@ static void hdmitx_set_scdc(struct hdmitx_dev *hdev)
 
 void hdmitx_set_enc_hw(struct hdmitx_dev *hdev)
 {
-       struct hdmi_format_para *para = NULL;
        set_vmode_enc_hw(hdev);
 
-       para = hdmi_get_fmt_paras(hdev->cur_video_param->VIC);
-
-       if (para == NULL) {
-               pr_info("error at %s[%d] vic = %d\n", __func__, __LINE__,
-               hdev->cur_video_param->VIC);
-       } else {
-               hd_write_reg(P_VPP_POSTBLEND_H_SIZE, para->hdmitx_vinfo.width);
-       }
-
        if (hdev->flag_3dfp) {
                hd_write_reg(P_VPU_HDMI_SETTING, 0x8e);
        } else {

diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
index 57b837a..d68ab81 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
@@ -449,7 +449,6 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
 
        lcd_vcbus_write(ENCL_VIDEO_EN, 0);
 
-       lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, ((0 << 0) | (0 << 2)));
        lcd_vcbus_write(ENCL_VIDEO_MODE, 0x8000);/*bit[15] shadown en*/
        lcd_vcbus_write(ENCL_VIDEO_MODE_ADV, 0x0418); /* Sampling rate: 1 */
 

diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
index 5c30fa0..f516cfc 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
@@ -95,8 +95,6 @@ static int lcd_set_current_vmode(enum vmode_e mode)
        } else
                lcd_clk_gate_switch(1);
 
-       lcd_vcbus_write(VPP_POSTBLEND_H_SIZE, lcd_drv->lcd_info->width);
-
        mutex_unlock(&lcd_vout_mutex);
        return ret;
 }

diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
index 1aa138b..5eea707 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
@@ -1064,7 +1064,6 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
 
        lcd_vcbus_write(ENCL_VIDEO_EN, 0);
 
-       lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, (0 << 0) | (3 << 2));
        /* Enable Hsync and equalization pulse switch in center;
         * bit[14] cfg_de_v = 1
         */

diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
index ba8ffea..e01bf71 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
@@ -300,8 +300,6 @@ static int lcd_set_current_vmode(enum vmode_e mode)
        } else
                lcd_clk_gate_switch(1);
 
-       lcd_vcbus_write(VPP_POSTBLEND_H_SIZE, lcd_drv->lcd_info->width);
-
        mutex_unlock(&lcd_vout_mutex);
        return ret;
 }

diff --git a/drivers/amlogic/media/vout/vout_serve/vout_func.c b/drivers/amlogic/media/vout/vout_serve/vout_func.c
index 3bea5c0..35766b0 100644 (file)
--- a/drivers/amlogic/media/vout/vout_serve/vout_func.c
+++ b/drivers/amlogic/media/vout/vout_serve/vout_func.c
@@ -121,10 +121,9 @@ static inline int vout_func_check_state(int index, unsigned int state,
 static void vout_func_update_viu(int index, struct vout_server_s *p_server)
 {
        struct vinfo_s *vinfo = NULL;
-       unsigned int post_reg = VPP_POSTBLEND_H_SIZE;
-       unsigned int bit = 0, mux = 3;
+       unsigned int mux_bit = 0, mux_sel = 3;
+       unsigned int clk_bit = 0, clk_sel = 0;
 
-       return;
        if (p_server->op.get_vinfo)
                vinfo = p_server->op.get_vinfo();
        else
@@ -132,21 +131,39 @@ static void vout_func_update_viu(int index, struct vout_server_s *p_server)
 
        switch (index) {
        case 1:
-               post_reg = VPP_POSTBLEND_H_SIZE;
-               bit = 0;
+               mux_bit = 0;
+               clk_sel = 0;
                break;
        case 2:
-               post_reg = VPP2_POSTBLEND_H_SIZE;
-               bit = 2;
+               mux_bit = 2;
+               clk_sel = 1;
                break;
        default:
                break;
        }
 
-       mux = vinfo->viu_mux;
+       mux_sel = vinfo->viu_mux;
+       switch (mux_sel) {
+       case VIU_MUX_ENCL:
+               clk_bit = 1;
+               break;
+       case VIU_MUX_ENCI:
+               clk_bit = 2;
+               break;
+       case VIU_MUX_ENCP:
+               clk_bit = 0;
+               break;
+       default:
+               break;
+       }
+
+       vout_func_vcbus_setb(VPU_VIU_VENC_MUX_CTRL, mux_sel, mux_bit, 2);
+       vout_func_vcbus_setb(VPU_VENCX_CLK_CTRL, clk_sel, clk_bit, 1);
 
-       vout_func_vcbus_write(post_reg, vinfo->width);
-       vout_func_vcbus_setb(VPU_VIU_VENC_MUX_CTRL, mux, bit, 2);
+#if 0
+       VOUTPR("%s: %d, mux_sel=%d, clk_sel=%d\n",
+               __func__, index, mux_sel, clk_sel);
+#endif
 }
 
 /*
@@ -176,10 +193,10 @@ int vout_func_set_current_vmode(int index, enum vmode_e mode)
 
                if (p_server->op.vmode_is_supported(mode) == true) {
                        p_module->curr_vout_server = p_server;
+                       vout_func_update_viu(index, p_server);
                        ret = p_server->op.set_vmode(mode);
                        if (p_server->op.set_state)
                                p_server->op.set_state(index);
-                       vout_func_update_viu(index, p_server);
                } else {
                        if (p_server->op.get_state) {
                                state = p_server->op.get_state();

diff --git a/drivers/amlogic/media/vout/vout_serve/vout_func.h b/drivers/amlogic/media/vout/vout_serve/vout_func.h
index fc97b08..4f5c5db 100644 (file)
--- a/drivers/amlogic/media/vout/vout_serve/vout_func.h
+++ b/drivers/amlogic/media/vout/vout_serve/vout_func.h
@@ -23,12 +23,17 @@
 #define VOUTPR(fmt, args...)     pr_info("vout: "fmt"", ## args)
 #define VOUTERR(fmt, args...)    pr_err("vout: error: "fmt"", ## args)
 
-/* [ 3: 2] cntl_viu2_sel_venc:
- *         0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
- * [ 1: 0] cntl_viu1_sel_venc:
- *         0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
+/* [3: 2] cntl_viu2_sel_venc:
+ *         0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
+ * [1: 0] cntl_viu1_sel_venc:
+ *         0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
  */
 #define VPU_VIU_VENC_MUX_CTRL                      0x271a
+/* [2] Enci_afifo_clk: 0: cts_vpu_clk_tm 1: cts_vpu_clkc_tm
+ * [1] Encl_afifo_clk: 0: cts_vpu_clk_tm 1: cts_vpu_clkc_tm
+ * [0] Encp_afifo_clk: 0: cts_vpu_clk_tm 1: cts_vpu_clkc_tm
+ */
+#define VPU_VENCX_CLK_CTRL                         0x2785
 #define VPP_POSTBLEND_H_SIZE                       0x1d21
 #define VPP2_POSTBLEND_H_SIZE                      0x1921