(define_insn "*bseti<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(ior:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"bseti\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
(define_insn "*bclri<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(and:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "not_single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "not_single_bit_mask_operand" "DnS")))]
"TARGET_ZBS"
"bclri\t%0,%1,%T2"
[(set_attr "type" "bitmanip")])
(define_insn "*binvi<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(xor:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "single_bit_mask_operand" "i")))]
+ (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
"TARGET_ZBS"
"binvi\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
(and (match_code "const_int")
(match_test "ival == 63")))
+(define_constraint "DbS"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "SINGLE_BIT_MASK_OPERAND (ival)")))
+
+(define_constraint "DnS"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"