[RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand
authorAndrew Pinski <apinski@marvell.com>
Mon, 15 Aug 2022 22:48:25 +0000 (22:48 +0000)
committerAndrew Pinski <apinski@marvell.com>
Wed, 24 Aug 2022 19:15:33 +0000 (12:15 -0700)
Like a previous patch, just add constraints for predicates
not_single_bit_mask_operand and single_bit_mask_operand.

OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu.

Thanks,
Andrew Pinski

gcc/ChangeLog:

* config/riscv/constraints.md (DbS): New constraint.
(DnS): New constraint.
* config/riscv/bitmanip.md (*bset<mode>_1_mask): Use new constraint.
(*bclr<mode>): Likewise.
(*binvi<mode>): Likewise.

gcc/config/riscv/bitmanip.md
gcc/config/riscv/constraints.md

index 73b2c10..2c0c8bb 100644 (file)
 (define_insn "*bseti<mode>"
   [(set (match_operand:X 0 "register_operand" "=r")
        (ior:X (match_operand:X 1 "register_operand" "r")
-              (match_operand 2 "single_bit_mask_operand" "i")))]
+              (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
   "TARGET_ZBS"
   "bseti\t%0,%1,%S2"
   [(set_attr "type" "bitmanip")])
 (define_insn "*bclri<mode>"
   [(set (match_operand:X 0 "register_operand" "=r")
        (and:X (match_operand:X 1 "register_operand" "r")
-              (match_operand 2 "not_single_bit_mask_operand" "i")))]
+              (match_operand:X 2 "not_single_bit_mask_operand" "DnS")))]
   "TARGET_ZBS"
   "bclri\t%0,%1,%T2"
   [(set_attr "type" "bitmanip")])
 (define_insn "*binvi<mode>"
   [(set (match_operand:X 0 "register_operand" "=r")
        (xor:X (match_operand:X 1 "register_operand" "r")
-              (match_operand 2 "single_bit_mask_operand" "i")))]
+              (match_operand:X 2 "single_bit_mask_operand" "DbS")))]
   "TARGET_ZBS"
   "binvi\t%0,%1,%S2"
   [(set_attr "type" "bitmanip")])
index 444870a..2873d53 100644 (file)
   (and (match_code "const_int")
        (match_test "ival == 63")))
 
+(define_constraint "DbS"
+  "@internal"
+  (and (match_code "const_int")
+       (match_test "SINGLE_BIT_MASK_OPERAND (ival)")))
+
+(define_constraint "DnS"
+  "@internal"
+  (and (match_code "const_int")
+       (match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"