soc: imx: gpcv2: add support for i.MX8MN power domains

This adds support for the power domains founds on i.MX8MN. The Nano
has fewer domains than the Mini, and the access to some of these domains
is different than that of the Mini, the Mini power domains cannot be
reused.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 35bbb1b..34a9ac1 100644 (file)
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -20,6 +20,7 @@
 #include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/power/imx8mq-power.h>
 #include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/power/imx8mn-power.h>
 
 #define GPC_LPCR_A_CORE_BSC                    0x000
 
@@ -58,6 +59,12 @@
 #define IMX8MM_PCIE_A53_DOMAIN                 BIT(3)
 #define IMX8MM_MIPI_A53_DOMAIN                 BIT(2)
 
+#define IMX8MN_DISPMIX_A53_DOMAIN              BIT(12)
+#define IMX8MN_GPUMIX_A53_DOMAIN               BIT(9)
+#define IMX8MN_DDR1_A53_DOMAIN         BIT(7)
+#define IMX8MN_OTG1_A53_DOMAIN         BIT(4)
+#define IMX8MN_MIPI_A53_DOMAIN         BIT(2)
+
 #define GPC_PU_PGC_SW_PUP_REQ          0x0f8
 #define GPC_PU_PGC_SW_PDN_REQ          0x104
 
@@ -94,6 +101,12 @@
 #define IMX8MM_PCIE_SW_Pxx_REQ                 BIT(1)
 #define IMX8MM_MIPI_SW_Pxx_REQ                 BIT(0)
 
+#define IMX8MN_DISPMIX_SW_Pxx_REQ              BIT(10)
+#define IMX8MN_GPUMIX_SW_Pxx_REQ               BIT(7)
+#define IMX8MN_DDR1_SW_Pxx_REQ         BIT(5)
+#define IMX8MN_OTG1_SW_Pxx_REQ         BIT(2)
+#define IMX8MN_MIPI_SW_Pxx_REQ         BIT(0)
+
 #define GPC_M4_PU_PDN_FLG              0x1bc
 
 #define GPC_PU_PWRHSK                  0x1fc
@@ -116,6 +129,14 @@
 #define IMX8MM_VPUMIX_HSK_PWRDNREQN            BIT(8)
 #define IMX8MM_DISPMIX_HSK_PWRDNREQN           BIT(7)
 #define IMX8MM_HSIO_HSK_PWRDNREQN              (BIT(5) | BIT(6))
+
+#define IMX8MN_GPUMIX_HSK_PWRDNACKN            (BIT(29) | BIT(27))
+#define IMX8MN_DISPMIX_HSK_PWRDNACKN           BIT(25)
+#define IMX8MN_HSIO_HSK_PWRDNACKN              BIT(23)
+#define IMX8MN_GPUMIX_HSK_PWRDNREQN            (BIT(11) | BIT(9))
+#define IMX8MN_DISPMIX_HSK_PWRDNREQN           BIT(7)
+#define IMX8MN_HSIO_HSK_PWRDNREQN              BIT(5)
+
 /*
  * The PGC offset values in Reference Manual
  * (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -152,6 +173,12 @@
 #define IMX8MM_PGC_VPUG2               28
 #define IMX8MM_PGC_VPUH1               29
 
+#define IMX8MN_PGC_MIPI                16
+#define IMX8MN_PGC_OTG1                18
+#define IMX8MN_PGC_DDR1                21
+#define IMX8MN_PGC_GPUMIX              23
+#define IMX8MN_PGC_DISPMIX             26
+
 #define GPC_PGC_CTRL(n)                        (0x800 + (n) * 0x40)
 #define GPC_PGC_SR(n)                  (GPC_PGC_CTRL(n) + 0xc)
 
@@ -764,6 +791,70 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
        .reg_access_table = &imx8mm_access_table,
 };
 
+static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
+       [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
+               .genpd = {
+                       .name = "hsiomix",
+               },
+               .bits  = {
+                       .pxx = 0, /* no power sequence control */
+                       .map = 0, /* no power sequence control */
+                       .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
+                       .hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
+               },
+       },
+
+       [IMX8MN_POWER_DOMAIN_OTG1] = {
+               .genpd = {
+                       .name = "usb-otg1",
+               },
+               .bits  = {
+                       .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
+                       .map = IMX8MN_OTG1_A53_DOMAIN,
+               },
+               .pgc   = IMX8MN_PGC_OTG1,
+       },
+
+       [IMX8MN_POWER_DOMAIN_GPUMIX] = {
+               .genpd = {
+                       .name = "gpumix",
+               },
+               .bits  = {
+                       .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
+                       .map = IMX8MN_GPUMIX_A53_DOMAIN,
+                       .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
+                       .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
+               },
+               .pgc   = IMX8MN_PGC_GPUMIX,
+       },
+};
+
+static const struct regmap_range imx8mn_yes_ranges[] = {
+       regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+                        GPC_PU_PWRHSK),
+       regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
+                        GPC_PGC_SR(IMX8MN_PGC_MIPI)),
+       regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
+                        GPC_PGC_SR(IMX8MN_PGC_OTG1)),
+       regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
+                        GPC_PGC_SR(IMX8MN_PGC_DDR1)),
+       regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
+                        GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
+       regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
+                        GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
+};
+
+static const struct regmap_access_table imx8mn_access_table = {
+       .yes_ranges     = imx8mn_yes_ranges,
+       .n_yes_ranges   = ARRAY_SIZE(imx8mn_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
+       .domains = imx8mn_pgc_domains,
+       .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
+       .reg_access_table = &imx8mn_access_table,
+};
+
 static int imx_pgc_domain_probe(struct platform_device *pdev)
 {
        struct imx_pgc_domain *domain = pdev->dev.platform_data;
@@ -948,6 +1039,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
 static const struct of_device_id imx_gpcv2_dt_ids[] = {
        { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
        { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
+       { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
        { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
        { }
 };