return true;
}
+template <>
+bool AVRExpandPseudo::expand<AVR::LSLB7Rd>(Block &MBB, BlockIt MBBI) {
+ MachineInstr &MI = *MBBI;
+ Register DstReg = MI.getOperand(0).getReg();
+ bool DstIsDead = MI.getOperand(0).isDead();
+ bool DstIsKill = MI.getOperand(1).isKill();
+ bool ImpIsDead = MI.getOperand(2).isDead();
+
+ // ror r24
+ // clr r24
+ // ror r24
+
+ buildMI(MBB, MBBI, AVR::RORRd)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ buildMI(MBB, MBBI, AVR::EORRdRr)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ auto MIRRC =
+ buildMI(MBB, MBBI, AVR::RORRd)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ if (ImpIsDead)
+ MIRRC->getOperand(2).setIsDead();
+
+ // SREG is always implicitly killed
+ MIRRC->getOperand(3).setIsKill();
+
+ MI.eraseFromParent();
+ return true;
+}
+
+template <>
+bool AVRExpandPseudo::expand<AVR::LSRB7Rd>(Block &MBB, BlockIt MBBI) {
+ MachineInstr &MI = *MBBI;
+ Register DstReg = MI.getOperand(0).getReg();
+ bool DstIsDead = MI.getOperand(0).isDead();
+ bool DstIsKill = MI.getOperand(1).isKill();
+ bool ImpIsDead = MI.getOperand(2).isDead();
+
+ // rol r24
+ // clr r24
+ // rol r24
+
+ buildMI(MBB, MBBI, AVR::ADCRdRr)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ buildMI(MBB, MBBI, AVR::EORRdRr)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ auto MIRRC =
+ buildMI(MBB, MBBI, AVR::ADCRdRr)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ if (ImpIsDead)
+ MIRRC->getOperand(3).setIsDead();
+
+ // SREG is always implicitly killed
+ MIRRC->getOperand(4).setIsKill();
+
+ MI.eraseFromParent();
+ return true;
+}
+
+template <>
+bool AVRExpandPseudo::expand<AVR::ASRB7Rd>(Block &MBB, BlockIt MBBI) {
+ MachineInstr &MI = *MBBI;
+ Register DstReg = MI.getOperand(0).getReg();
+ bool DstIsDead = MI.getOperand(0).isDead();
+ bool DstIsKill = MI.getOperand(1).isKill();
+ bool ImpIsDead = MI.getOperand(2).isDead();
+
+ // lsl r24
+ // sbc r24, r24
+
+ buildMI(MBB, MBBI, AVR::ADDRdRr)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ auto MIRRC = buildMI(MBB, MBBI, AVR::SBCRdRr)
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ .addReg(DstReg, getKillRegState(DstIsKill));
+
+ if (ImpIsDead)
+ MIRRC->getOperand(3).setIsDead();
+
+ // SREG is always implicitly killed
+ MIRRC->getOperand(4).setIsKill();
+
+ MI.eraseFromParent();
+ return true;
+}
+
template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register DstLoReg, DstHiReg;
EXPAND(AVR::RORWRd);
EXPAND(AVR::ROLWRd);
EXPAND(AVR::ASRWRd);
+ EXPAND(AVR::LSLB7Rd);
+ EXPAND(AVR::LSRB7Rd);
+ EXPAND(AVR::ASRB7Rd);
EXPAND(AVR::SEXT);
EXPAND(AVR::ZEXT);
EXPAND(AVR::SPREAD);
Victim =
DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
ShiftAmount -= 4;
+ } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
+ // Optimize LSL when ShiftAmount == 7.
+ Victim = DAG.getNode(AVRISD::LSL7, dl, VT, Victim);
+ ShiftAmount = 0;
+ } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
+ // Optimize LSR when ShiftAmount == 7.
+ Victim = DAG.getNode(AVRISD::LSR7, dl, VT, Victim);
+ ShiftAmount = 0;
+ } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
+ // Optimize ASR when ShiftAmount == 7.
+ Victim = DAG.getNode(AVRISD::ASR7, dl, VT, Victim);
+ ShiftAmount = 0;
}
}
def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
+def AVRlsl7 : SDNode<"AVRISD::LSL7", SDTIntUnaryOp>;
+def AVRlsr7 : SDNode<"AVRISD::LSR7", SDTIntUnaryOp>;
+def AVRasr7 : SDNode<"AVRISD::ASR7", SDTIntUnaryOp>;
// Pseudo shift nodes for non-constant shift amounts.
def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
"lslw\t$rd",
[(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>;
+ def LSLB7Rd : Pseudo<(outs GPR8:$rd),
+ (ins GPR8:$src),
+ "lslb7\t$rd",
+ [(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>;
+
def LSRRd : FRd<0b1001,
0b0100110,
(outs GPR8:$rd),
"lsr\t$rd",
[(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>;
+ def LSRB7Rd : Pseudo<(outs GPR8:$rd),
+ (ins GPR8:$src),
+ "lsrb7\t$rd",
+ [(set i8:$rd, (AVRlsr7 i8:$src)), (implicit SREG)]>;
+
def LSRWRd : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src),
"lsrw\t$rd",
"asr\t$rd",
[(set i8:$rd, (AVRasr i8:$src)), (implicit SREG)]>;
+ def ASRB7Rd : Pseudo<(outs GPR8:$rd),
+ (ins GPR8:$src),
+ "asrb7\t$rd",
+ [(set i8:$rd, (AVRasr7 i8:$src)), (implicit SREG)]>;
+
def ASRWRd : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src),
"asrw\t$rd",