rtw88: pci: 8822c should set clock delay to zero

Since RTL8822CE has enabled reference clock auto calibration,
there is no need to add any clock delay for covering the timing
gap of the reference clock.

Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

diff --git a/drivers/net/wireless/realtek/rtw88/pci.c b/drivers/net/wireless/realtek/rtw88/pci.c
index 1fbc14c..9ac77ae 100644 (file)
--- a/drivers/net/wireless/realtek/rtw88/pci.c
+++ b/drivers/net/wireless/realtek/rtw88/pci.c
@@ -1197,11 +1197,18 @@ static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter)
 
 static void rtw_pci_link_cfg(struct rtw_dev *rtwdev)
 {
+       struct rtw_chip_info *chip = rtwdev->chip;
        struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
        struct pci_dev *pdev = rtwpci->pdev;
        u16 link_ctrl;
        int ret;
 
+       /* RTL8822CE has enabled REFCLK auto calibration, it does not need
+        * to add clock delay to cover the REFCLK timing gap.
+        */
+       if (chip->id == RTW_CHIP_TYPE_8822C)
+               rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0);
+
        /* Though there is standard PCIE configuration space to set the
         * link control register, but by Realtek's design, driver should
         * check if host supports CLKREQ/ASPM to enable the HW module.

diff --git a/drivers/net/wireless/realtek/rtw88/pci.h b/drivers/net/wireless/realtek/rtw88/pci.h
index 1580cfc..cd4fcd0 100644 (file)
--- a/drivers/net/wireless/realtek/rtw88/pci.h
+++ b/drivers/net/wireless/realtek/rtw88/pci.h
@@ -39,6 +39,7 @@
 #define RTK_PCIE_LINK_CFG      0x0719
 #define BIT_CLKREQ_SW_EN       BIT(4)
 #define BIT_L1_SW_EN           BIT(3)
+#define RTK_PCIE_CLKDLY_CTRL   0x0725
 
 #define BIT_PCI_BCNQ_FLAG      BIT(4)
 #define RTK_PCI_TXBD_DESA_BCNQ 0x308