EDAC/amd64: Merge sysfs debugging attributes setup code

There's no need for them to be in a separate file so merge them into the
main driver compilation unit like the other EDAC drivers do.

Drop now-unneeded function export, make the function static and shorten
static function names.

No functional changes.

Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Link: https://lkml.kernel.org/r/20201215110517.5215-1-bp@alien8.de

diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 464d3d8..1c70cdc 100644 (file)
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_EDAC_I82860)             += i82860_edac.o
 obj-$(CONFIG_EDAC_R82600)              += r82600_edac.o
 
 amd64_edac_mod-y := amd64_edac.o
-amd64_edac_mod-$(CONFIG_EDAC_DEBUG) += amd64_edac_dbg.o
 amd64_edac_mod-$(CONFIG_EDAC_AMD64_ERROR_INJECTION) += amd64_edac_inj.o
 
 obj-$(CONFIG_EDAC_AMD64)               += amd64_edac_mod.o

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 543221e..b00dea7 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -500,8 +500,8 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
  * complete 32-bit values despite the fact that the bitfields in the DHAR
  * only represent bits 31-24 of the base and offset values.
  */
-int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
-                            u64 *hole_offset, u64 *hole_size)
+static int get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
+                             u64 *hole_offset, u64 *hole_size)
 {
        struct amd64_pvt *pvt = mci->pvt_info;
 
@@ -554,7 +554,61 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);
+
+#ifdef CONFIG_EDAC_DEBUG
+#define EDAC_DCT_ATTR_SHOW(reg)                                                \
+static ssize_t reg##_show(struct device *dev,                          \
+                        struct device_attribute *mattr, char *data)    \
+{                                                                      \
+       struct mem_ctl_info *mci = to_mci(dev);                         \
+       struct amd64_pvt *pvt = mci->pvt_info;                          \
+                                                                       \
+       return sprintf(data, "0x%016llx\n", (u64)pvt->reg);             \
+}
+
+EDAC_DCT_ATTR_SHOW(dhar);
+EDAC_DCT_ATTR_SHOW(dbam0);
+EDAC_DCT_ATTR_SHOW(top_mem);
+EDAC_DCT_ATTR_SHOW(top_mem2);
+
+static ssize_t hole_show(struct device *dev, struct device_attribute *mattr,
+                        char *data)
+{
+       struct mem_ctl_info *mci = to_mci(dev);
+
+       u64 hole_base = 0;
+       u64 hole_offset = 0;
+       u64 hole_size = 0;
+
+       get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
+
+       return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
+                                                hole_size);
+}
+
+/*
+ * update NUM_DBG_ATTRS in case you add new members
+ */
+static DEVICE_ATTR(dhar, S_IRUGO, dhar_show, NULL);
+static DEVICE_ATTR(dbam, S_IRUGO, dbam0_show, NULL);
+static DEVICE_ATTR(topmem, S_IRUGO, top_mem_show, NULL);
+static DEVICE_ATTR(topmem2, S_IRUGO, top_mem2_show, NULL);
+static DEVICE_ATTR(dram_hole, S_IRUGO, hole_show, NULL);
+
+static struct attribute *dbg_attrs[] = {
+       &dev_attr_dhar.attr,
+       &dev_attr_dbam.attr,
+       &dev_attr_topmem.attr,
+       &dev_attr_topmem2.attr,
+       &dev_attr_dram_hole.attr,
+       NULL
+};
+
+static const struct attribute_group dbg_group = {
+       .attrs = dbg_attrs,
+};
+#endif /* CONFIG_EDAC_DEBUG */
+
 
 /*
  * Return the DramAddr that the SysAddr given by @sys_addr maps to.  It is
@@ -593,8 +647,7 @@ static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
 
        dram_base = get_dram_base(pvt, pvt->mc_node_id);
 
-       ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
-                                     &hole_size);
+       ret = get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
        if (!ret) {
                if ((sys_addr >= (1ULL << 32)) &&
                    (sys_addr < ((1ULL << 32) + hole_size))) {
@@ -3415,7 +3468,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
 
 static const struct attribute_group *amd64_edac_attr_groups[] = {
 #ifdef CONFIG_EDAC_DEBUG
-       &amd64_edac_dbg_group,
+       &dbg_group,
 #endif
 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
        &amd64_edac_inj_group,

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 52b5d03..c072ccd 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -462,10 +462,6 @@ struct ecc_settings {
        } flags;
 };
 
-#ifdef CONFIG_EDAC_DEBUG
-extern const struct attribute_group amd64_edac_dbg_group;
-#endif
-
 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
 extern const struct attribute_group amd64_edac_inj_group;
 #endif
@@ -501,9 +497,6 @@ int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
 #define amd64_write_pci_cfg(pdev, offset, val) \
        __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
 
-int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
-                            u64 *hole_offset, u64 *hole_size);
-
 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
 
 /* Injection helpers */

diff --git a/drivers/edac/amd64_edac_dbg.c b/drivers/edac/amd64_edac_dbg.c
deleted file mode 100644 (file)
index 393be33..0000000
--- a/drivers/edac/amd64_edac_dbg.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "amd64_edac.h"
-
-#define EDAC_DCT_ATTR_SHOW(reg)                                                \
-static ssize_t amd64_##reg##_show(struct device *dev,                  \
-                              struct device_attribute *mattr,          \
-                              char *data)                              \
-{                                                                      \
-       struct mem_ctl_info *mci = to_mci(dev);                         \
-       struct amd64_pvt *pvt = mci->pvt_info;                          \
-               return sprintf(data, "0x%016llx\n", (u64)pvt->reg);     \
-}
-
-EDAC_DCT_ATTR_SHOW(dhar);
-EDAC_DCT_ATTR_SHOW(dbam0);
-EDAC_DCT_ATTR_SHOW(top_mem);
-EDAC_DCT_ATTR_SHOW(top_mem2);
-
-static ssize_t amd64_hole_show(struct device *dev,
-                              struct device_attribute *mattr,
-                              char *data)
-{
-       struct mem_ctl_info *mci = to_mci(dev);
-
-       u64 hole_base = 0;
-       u64 hole_offset = 0;
-       u64 hole_size = 0;
-
-       amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
-
-       return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
-                                                hole_size);
-}
-
-/*
- * update NUM_DBG_ATTRS in case you add new members
- */
-static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);
-static DEVICE_ATTR(dbam, S_IRUGO, amd64_dbam0_show, NULL);
-static DEVICE_ATTR(topmem, S_IRUGO, amd64_top_mem_show, NULL);
-static DEVICE_ATTR(topmem2, S_IRUGO, amd64_top_mem2_show, NULL);
-static DEVICE_ATTR(dram_hole, S_IRUGO, amd64_hole_show, NULL);
-
-static struct attribute *amd64_edac_dbg_attrs[] = {
-       &dev_attr_dhar.attr,
-       &dev_attr_dbam.attr,
-       &dev_attr_topmem.attr,
-       &dev_attr_topmem2.attr,
-       &dev_attr_dram_hole.attr,
-       NULL
-};
-
-const struct attribute_group amd64_edac_dbg_group = {
-       .attrs = amd64_edac_dbg_attrs,
-};