Parallel port reset

Attached patch adds a reset handler to parallel port, so it gets correct
register values after a reset.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5942 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/hw/parallel.c b/hw/parallel.c
index 025067a..c734bdb 100644 (file)
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -418,8 +418,10 @@ static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
     return ret;
 }
 
-static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
+static void parallel_reset(void *opaque)
 {
+    ParallelState *s = opaque;
+
     s->datar = ~0;
     s->dataw = ~0;
     s->status = PARA_STS_BUSY;
@@ -430,9 +432,7 @@ static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
     s->control = PARA_CTR_SELECT;
     s->control |= PARA_CTR_INIT;
     s->control |= 0xc0;
-    s->irq = irq;
     s->irq_pending = 0;
-    s->chr = chr;
     s->hw_driver = 0;
     s->epp_timeout = 0;
     s->last_read_offset = ~0U;
@@ -447,7 +447,10 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
     s = qemu_mallocz(sizeof(ParallelState));
     if (!s)
         return NULL;
-    parallel_reset(s, irq, chr);
+    s->irq = irq;
+    s->chr = chr;
+    parallel_reset(s);
+    qemu_register_reset(parallel_reset, s);
 
     if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
         s->hw_driver = 1;
@@ -538,8 +541,11 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
     s = qemu_mallocz(sizeof(ParallelState));
     if (!s)
         return NULL;
-    parallel_reset(s, irq, chr);
+    s->irq = irq;
+    s->chr = chr;
     s->it_shift = it_shift;
+    parallel_reset(s);
+    qemu_register_reset(parallel_reset, s);
 
     io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
     cpu_register_physical_memory(base, 8 << it_shift, io_sw);