drm/i915/bdw: Use The GT mailbox for IPS enable/disable

v2: Squash in fixup from Ben to synchronize the GT mailbox commands.

CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d9d6db2..5deeb19 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1805,7 +1805,7 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
-#define HAS_IPS(dev)           (IS_ULT(dev))
+#define HAS_IPS(dev)           (IS_ULT(dev) || IS_BROADWELL(dev))
 
 #define HAS_DDI(dev)           (INTEL_INFO(dev)->has_ddi)
 #define HAS_POWER_WELL(dev)    (IS_HASWELL(dev) || IS_BROADWELL(dev))

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2abdd7..f99c8c5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4953,6 +4953,7 @@
 #define   GEN6_PCODE_WRITE_D_COMP              0x11
 #define   GEN6_ENCODE_RC6_VID(mv)              (((mv) - 245) / 5)
 #define   GEN6_DECODE_RC6_VID(vids)            (((vids) * 5) + 245)
+#define   DISPLAY_IPS_CONTROL                  0x19
 #define GEN6_PCODE_DATA                                0x138128
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT       8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT     16

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1b1e75e..e690cfe 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3393,15 +3393,26 @@ void hsw_enable_ips(struct intel_crtc *crtc)
         * only after intel_enable_plane. And intel_enable_plane already waits
         * for a vblank, so all we need to do here is to enable the IPS bit. */
        assert_plane_enabled(dev_priv, crtc->plane);
-       I915_WRITE(IPS_CTL, IPS_ENABLE);
-
-       /* The bit only becomes 1 in the next vblank, so this wait here is
-        * essentially intel_wait_for_vblank. If we don't have this and don't
-        * wait for vblanks until the end of crtc_enable, then the HW state
-        * readout code will complain that the expected IPS_CTL value is not the
-        * one we read. */
-       if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
-               DRM_ERROR("Timed out waiting for IPS enable\n");
+       if (IS_BROADWELL(crtc->base.dev)) {
+               mutex_lock(&dev_priv->rps.hw_lock);
+               WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
+               mutex_unlock(&dev_priv->rps.hw_lock);
+               /* Quoting Art Runyan: "its not safe to expect any particular
+                * value in IPS_CTL bit 31 after enabling IPS through the
+                * mailbox." Therefore we need to defer waiting on the state
+                * change.
+                * TODO: need to fix this for state checker
+                */
+       } else {
+               I915_WRITE(IPS_CTL, IPS_ENABLE);
+               /* The bit only becomes 1 in the next vblank, so this wait here
+                * is essentially intel_wait_for_vblank. If we don't have this
+                * and don't wait for vblanks until the end of crtc_enable, then
+                * the HW state readout code will complain that the expected
+                * IPS_CTL value is not the one we read. */
+               if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
+                       DRM_ERROR("Timed out waiting for IPS enable\n");
+       }
 }
 
 void hsw_disable_ips(struct intel_crtc *crtc)
@@ -3413,7 +3424,12 @@ void hsw_disable_ips(struct intel_crtc *crtc)
                return;
 
        assert_plane_enabled(dev_priv, crtc->plane);
-       I915_WRITE(IPS_CTL, 0);
+       if (IS_BROADWELL(crtc->base.dev)) {
+               mutex_lock(&dev_priv->rps.hw_lock);
+               WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
+               mutex_unlock(&dev_priv->rps.hw_lock);
+       } else
+               I915_WRITE(IPS_CTL, 0);
        POSTING_READ(IPS_CTL);
 
        /* We need to wait for a vblank before we can disable the plane. */