assert(OutlinedFn && "Invalid outlined function!");
- auto &Ctx = CGF.getContext();
-
// Fill up the arrays with all the captured variables.
MappableExprsHandler::MapValuesArrayTy KernelArgs;
MappableExprsHandler::MapBaseValuesArrayTy BasePointers;
MapTypes.append(CurMapTypes.begin(), CurMapTypes.end());
}
- // Keep track on whether the host function has to be executed.
- auto OffloadErrorQType =
- Ctx.getIntTypeForBitwidth(/*DestWidth=*/32, /*Signed=*/true);
- auto OffloadError = CGF.MakeAddrLValue(
- CGF.CreateMemTemp(OffloadErrorQType, ".run_host_version"),
- OffloadErrorQType);
- CGF.EmitStoreOfScalar(llvm::Constant::getNullValue(CGM.Int32Ty),
- OffloadError);
-
// Fill up the pointer arrays and transfer execution to the device.
- auto &&ThenGen = [&BasePointers, &Pointers, &Sizes, &MapTypes, Device,
- OutlinedFnID, OffloadError,
- &D](CodeGenFunction &CGF, PrePostActionTy &) {
+ auto &&ThenGen = [this, &BasePointers, &Pointers, &Sizes, &MapTypes, Device,
+ OutlinedFn, OutlinedFnID, &D,
+ &KernelArgs](CodeGenFunction &CGF, PrePostActionTy &) {
auto &RT = CGF.CGM.getOpenMPRuntime();
// Emit the offloading arrays.
TargetDataInfo Info;
OffloadingArgs);
}
- CGF.EmitStoreOfScalar(Return, OffloadError);
+ // Check the error code and execute the host version if required.
+ llvm::BasicBlock *OffloadFailedBlock =
+ CGF.createBasicBlock("omp_offload.failed");
+ llvm::BasicBlock *OffloadContBlock =
+ CGF.createBasicBlock("omp_offload.cont");
+ llvm::Value *Failed = CGF.Builder.CreateIsNotNull(Return);
+ CGF.Builder.CreateCondBr(Failed, OffloadFailedBlock, OffloadContBlock);
+
+ CGF.EmitBlock(OffloadFailedBlock);
+ emitOutlinedFunctionCall(CGF, D.getLocStart(), OutlinedFn, KernelArgs);
+ CGF.EmitBranch(OffloadContBlock);
+
+ CGF.EmitBlock(OffloadContBlock, /*IsFinished=*/true);
};
// Notify that the host version must be executed.
- auto &&ElseGen = [OffloadError](CodeGenFunction &CGF, PrePostActionTy &) {
- CGF.EmitStoreOfScalar(llvm::ConstantInt::get(CGF.Int32Ty, /*V=*/-1u),
- OffloadError);
+ auto &&ElseGen = [this, &D, OutlinedFn, &KernelArgs](CodeGenFunction &CGF,
+ PrePostActionTy &) {
+ emitOutlinedFunctionCall(CGF, D.getLocStart(), OutlinedFn,
+ KernelArgs);
};
// If we have a target function ID it means that we need to support
RegionCodeGenTy ElseRCG(ElseGen);
ElseRCG(CGF);
}
-
- // Check the error code and execute the host version if required.
- auto OffloadFailedBlock = CGF.createBasicBlock("omp_offload.failed");
- auto OffloadContBlock = CGF.createBasicBlock("omp_offload.cont");
- auto OffloadErrorVal = CGF.EmitLoadOfScalar(OffloadError, SourceLocation());
- auto Failed = CGF.Builder.CreateIsNotNull(OffloadErrorVal);
- CGF.Builder.CreateCondBr(Failed, OffloadFailedBlock, OffloadContBlock);
-
- CGF.EmitBlock(OffloadFailedBlock);
- emitOutlinedFunctionCall(CGF, D.getLocStart(), OutlinedFn, KernelArgs);
- CGF.EmitBranch(OffloadContBlock);
-
- CGF.EmitBlock(OffloadContBlock, /*IsFinished=*/true);
}
void CGOpenMPRuntime::scanForTargetRegionsFunctions(const Stmt *S,
TT<long long, char> d;
// CHECK: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null)
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT0:@.+]]()
{
}
- // CHECK: store i32 0, i32* [[RHV:%.+]], align 4
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
// CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}})
#pragma omp target if(0) firstprivate(global)
{
// CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], i[[SZ]]* [[CBPADDR0]]
// CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], i[[SZ]]* [[CPADDR0]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}})
// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]*
// CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]]
// CHECK-DAG: store i[[SZ]] [[P1:%[^,]+]], i[[SZ]]* [[CPADDR1]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFELSE]]
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFEND]]
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+ // CHECK-NEXT: br label %[[IFEND:.+]]
+ // CHECK: [[IFELSE]]
+ // CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}})
+ // CHECK-NEXT: br label %[[IFEND]]
+
+ // CHECK: [[IFEND]]
#pragma omp target if(n>10)
{
a += 1;
// CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CPADDR8]]
// CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* [[SADDR8]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
- // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
-
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
+ // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+ // CHECK-NEXT: br label %[[IFEND:.+]]
+ // CHECK: [[IFELSE]]
+ // CHECK: call void [[HVT4]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+ // CHECK-NEXT: br label %[[IFEND]]
+
+ // CHECK: [[IFEND]]
#pragma omp target if(n>20)
{
a += 1;
// CHECK-DAG: store i16* %{{.+}}, i16** [[CPADDR4]]
// CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* [[SADDR4]]
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
-// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
-
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
+// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT7]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+
+// CHECK: [[IFEND]]
//
// CHECK: define {{.*}}[[FSTATIC]]
// CHECK-DAG: store [10 x i32]* [[VAL3:%[^,]+]], [10 x i32]** [[CBPADDR3]]
// CHECK-DAG: store [10 x i32]* [[VAL3]], [10 x i32]** [[CPADDR3]]
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+
+// CHECK: [[IFEND]]
//
// CHECK: define {{.*}}[[FTEMPLATE]]
// CHECK-DAG: store [10 x i32]* [[VAL2:%[^,]+]], [10 x i32]** [[CBPADDR2]]
// CHECK-DAG: store [10 x i32]* [[VAL2]], [10 x i32]** [[CPADDR2]]
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT5]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
// Check that the offloading functions are emitted and that the arguments are
// CHECK: [[C:%.+]] = alloca [5 x [10 x double]],
// CHECK: [[D:%.+]] = alloca [[TT]],
// CHECK: [[ACAST:%.+]] = alloca i{{[0-9]+}},
- // CHECK: {{.+}} = alloca i{{[0-9]+}},
// CHECK: [[BASE_PTR_ARR:%.+]] = alloca [1 x i8*],
// CHECK: [[PTR_ARR:%.+]] = alloca [1 x i8*],
// CHECK: [[A2CAST:%.+]] = alloca i{{[0-9]+}},
TT<long long, char> d;
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null, i32 1, i32 0)
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT0:@.+]]()
{
}
- // CHECK: store i32 0, i32* [[RHV:%.+]], align 4
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
// CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}})
#pragma omp target parallel if(target: 0)
{
// CHECK-DAG: store i[[SZ]] [[VAL0:%.+]], i[[SZ]]* [[CBPADDR0]],
// CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]],
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}})
// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]*
// CHECK-DAG: store i[[SZ]] [[VAL1:%.+]], i[[SZ]]* [[CBPADDR1]],
// CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]],
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFELSE]]
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFEND]]
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+ // CHECK-NEXT: br label %[[IFEND:.+]]
+ // CHECK: [[IFELSE]]
+ // CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}})
+ // CHECK-NEXT: br label %[[IFEND]]
+ // CHECK: [[IFEND]]
+
#pragma omp target parallel if(target: n>10)
{
a += 1;
// CHECK-DAG: [[CPADDR8]] = bitcast i8** {{%[^,]+}} to [[TT]]**
// CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* {{%[^,]+}}
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK-DAG: [[CPADDR4]] = bitcast i8** {{%[^,]+}} to i16**
// CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* {{%[^,]+}}
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK-DAG: store [10 x i32]* [[VAL3:%.+]], [10 x i32]** [[CBPADDR3]],
// CHECK-DAG: store [10 x i32]* [[VAL3]], [10 x i32]** [[CPADDR3]],
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
//
// CHECK: define {{.*}}[[FTEMPLATE]]
// CHECK-DAG: store [10 x i32]* [[VAL2:%.+]], [10 x i32]** [[CBPADDR2]],
// CHECK-DAG: store [10 x i32]* [[VAL2]], [10 x i32]** [[CPADDR2]],
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
-
-
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
// Check that the offloading functions are emitted and that the arguments are
// correct and loaded correctly for the target regions of the callees of bar().
return a;
}
-
-
//
// CHECK: define {{.*}}[[FS1]]([[S1]]* {{%.+}}, i32 {{[^%]*}}[[PARM:%.+]])
//
// CHECK: [[ARG:%.+]] = load i[[SZ]], i[[SZ]]* [[CAPEC_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 3, {{.*}}, i32 1, i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
//
// CHECK: [[IF_THEN]]
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 2, {{.*}}, i32 1, i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: br label {{%?}}[[END:.+]]
-//
-// CHECK: [[IF_ELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align
-// CHECK: br label {{%?}}[[END]]
-//
-// CHECK: [[END]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
-// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
-//
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
+// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT2:@.+]]([[S1]]* {{%.+}}, i[[SZ]] [[ARG]])
-// CHECK: br label {{%?}}[[END]]
+// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
-
-
-
-
-
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IF_ELSE]]
+// CHECK: call void [[HVT2]]([[S1]]* {{%.+}}, i[[SZ]] [[ARG]])
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
//
// CHECK: define {{.*}}[[FSTATIC]](i32 {{[^%]*}}[[PARM:%.+]])
//
// CHECK: [[IF_THEN]]
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.*}}, i32 1, i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: br label {{%?}}[[END:.+]]
-//
-// CHECK: [[IF_ELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align
-// CHECK: br label {{%?}}[[END]]
-//
-// CHECK: [[END]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
-// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
-//
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
+// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT3:@.+]](i[[SZ]] [[ARG]])
-// CHECK: br label {{%?}}[[END]]
+// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IF_ELSE]]
+// CHECK: call void [[HVT3]](i[[SZ]] [[ARG]])
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
//
//
//
//
// CHECK: [[IF_THEN]]
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 0, {{.*}}, i32 1, i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: br label {{%?}}[[END:.+]]
-//
-// CHECK: [[IF_ELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align
-// CHECK: br label {{%?}}[[END]]
-//
-// CHECK: [[END]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
-// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
-//
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
+// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT4:@.+]]()
-// CHECK: br label {{%?}}[[END]]
+// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IF_ELSE]]
+// CHECK: call void [[HVT4]]()
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
// CHECK: define {{.*}}[[FTEMPLATE]]
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.*}}, i32 1, i32 0)
-// CHECK-NEXT: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK-NEXT: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
//
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 2, {{.*}}, i32 1, i32 0)
-// CHECK-NEXT: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK-NEXT: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[THREADS:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 3, {{.*}}, i32 1, i32 [[THREADS]])
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
//
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.+}}, i32 1, i32 1024)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[THREADS:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.*}}, i32 1, i32 [[THREADS]])
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[THREADS:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.*}}, i32 1, i32 [[THREADS]])
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: define {{.*}}[[FTEMPLATE]]
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 0, {{.*}}, i32 1, i32 20)
-// CHECK-NEXT: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK-NEXT: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[THREADS:%.+]] = sext i16 [[T]] to i32
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 3, {{.*}}, i32 1, i32 [[THREADS]])
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
TT<long long, char> d;
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null, i32 0, i32 0)
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT0:@.+]]()
{
}
- // CHECK: store i32 0, i32* [[RHV:%.+]], align 4
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
// CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}})
#pragma omp target teams if(target: 0)
{
// CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[CBPADDR0]]
// CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[CPADDR0]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}})
// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]*
// CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[CBPADDR1]]
// CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[CPADDR1]]
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFELSE]]
- // CHECK: store i32 -1, i32* [[RHV]], align 4
- // CHECK-NEXT: br label %[[IFEND:.+]]
-
- // CHECK: [[IFEND]]
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+ // CHECK-NEXT: br label %[[IFEND:.+]]
+ // CHECK: [[IFELSE]]
+ // CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}})
+ // CHECK-NEXT: br label %[[IFEND]]
+ // CHECK: [[IFEND]]
#pragma omp target teams if(target: n>10)
{
a += 1;
// CHECK-DAG: [[CPADDR8]] = bitcast i8** {{%[^,]+}} to [[TT]]**
// CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* {{%[^,]+}}
- // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
- // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
- // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+ // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK-DAG: [[CPADDR4]] = bitcast i8** {{%[^,]+}} to i16**
// CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* {{%[^,]+}}
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK-DAG: [[CBPADDR3]] = bitcast i8** {{%[^,]+}} to [10 x i32]**
// CHECK-DAG: [[CPADDR3]] = bitcast i8** {{%[^,]+}} to [10 x i32]**
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
//
// CHECK: define {{.*}}[[FTEMPLATE]]
// CHECK-DAG: [[CBPADDR2]] = bitcast i8** {{%[^,]+}} to [10 x i32]**
// CHECK-DAG: [[CPADDR2]] = bitcast i8** {{%[^,]+}} to [10 x i32]**
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFELSE]]
-// CHECK: store i32 -1, i32* [[RHV]], align 4
-// CHECK-NEXT: br label %[[IFEND:.+]]
-
-// CHECK: [[IFEND]]
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
+// CHECK-NEXT: br label %[[IFEND:.+]]
+// CHECK: [[IFELSE]]
+// CHECK: call void [[HVT5]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
+// CHECK-NEXT: br label %[[IFEND]]
+// CHECK: [[IFEND]]
// CHECK: [[TEAMS:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 3, {{.*}}, i32 [[TEAMS]], i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
//
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.+}}, i32 1024, i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[TEAMS:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.*}}, i32 [[TEAMS]], i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[TEAMS:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.*}}, i32 [[TEAMS]], i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: define {{.*}}[[FTEMPLATE]]
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 0, {{.*}}, i32 20, i32 0)
-// CHECK-NEXT: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK-NEXT: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[TEAMS:%.+]] = sext i16 [[T]] to i32
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 3, {{.*}}, i32 [[TEAMS]], i32 0)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[TL:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 3, {{.*}}, i32 0, i32 [[TL]])
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
//
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.+}}, i32 0, i32 1024)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[TL:%.+]] = load i32, i32* [[CAPE_ADDR2]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 2, {{.*}}, i32 [[TEAMS]], i32 [[TL]])
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[TL:%.+]] = load i32, i32* [[CAPE_ADDR]], align
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 1, {{.*}}, i32 0, i32 [[TL]])
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: define {{.*}}[[FTEMPLATE]]
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 0, {{.*}}, i32 0, i32 20)
-// CHECK-NEXT: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK-NEXT: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]
// CHECK: [[TEAMS:%.+]] = sext i16 [[T]] to i32
//
// CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_teams(i32 -1, i8* @{{[^,]+}}, i32 3, {{.*}}, i32 [[TEAMS]], i32 1024)
-// CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align
-// CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align
-// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
+// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
//
// CHECK: [[FAIL]]