declare i1 @llvm.vp.reduce.and.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_and_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_or_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_v1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_v1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_v1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_xor_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_v1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_v1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_v1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_and_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_or_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_v2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_v2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_xor_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_v2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_v2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_and_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_or_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_v4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_v4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_xor_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_v4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_v4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_and_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_or_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_v8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_v8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_xor_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_v8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_v8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.v10i1(i1, <10 x i1>, <10 x i1>, i32)
-define signext i1 @vpreduce_and_v10i1(i1 signext %s, <10 x i1> %v, <10 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_v10i1(i1 zeroext %s, <10 x i1> %v, <10 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v10i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v10i1(i1 %s, <10 x i1> %v, <10 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.and.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_and_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.and.v256i1(i1, <256 x i1>, <256 x i1>, i32)
-define signext i1 @vpreduce_and_v256i1(i1 signext %s, <256 x i1> %v, <256 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_v256i1(i1 zeroext %s, <256 x i1> %v, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v256i1:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: and a0, a0, a2
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.v256i1(i1 %s, <256 x i1> %v, <256 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_or_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_v16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_v16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_xor_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_v16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_v16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_add_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_v1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_v1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_v1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_add_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_v2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_v2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_add_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_v4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_v4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_add_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_v8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_v8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_add_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_v16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_v16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smax.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_smax_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_smax_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_smax_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_smax_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_smax_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.v32i1(i1, <32 x i1>, <32 x i1>, i32)
-define signext i1 @vpreduce_smax_v32i1(i1 signext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_v32i1(i1 zeroext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.v32i1(i1 %s, <32 x i1> %v, <32 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.v64i1(i1, <64 x i1>, <64 x i1>, i32)
-define signext i1 @vpreduce_smax_v64i1(i1 signext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_v64i1(i1 zeroext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_v64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smin.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_smin_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_v1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_v1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_v1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_smin_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_v2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_v2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_smin_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_v4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_v4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_smin_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_v8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_v8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_smin_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_v16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_v16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.v32i1(i1, <32 x i1>, <32 x i1>, i32)
-define signext i1 @vpreduce_smin_v32i1(i1 signext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_v32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_v32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_v32i1(i1 zeroext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_v32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.v32i1(i1 %s, <32 x i1> %v, <32 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.v64i1(i1, <64 x i1>, <64 x i1>, i32)
-define signext i1 @vpreduce_smin_v64i1(i1 signext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_v64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_v64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_v64i1(i1 zeroext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_v64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_umax_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_v1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_umax_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_umax_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_umax_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_umax_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.v32i1(i1, <32 x i1>, <32 x i1>, i32)
-define signext i1 @vpreduce_umax_v32i1(i1 signext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_v32i1(i1 zeroext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_v32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.v32i1(i1 %s, <32 x i1> %v, <32 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.v64i1(i1, <64 x i1>, <64 x i1>, i32)
-define signext i1 @vpreduce_umax_v64i1(i1 signext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_v64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_v64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_v64i1(i1 zeroext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_v64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umin.v1i1(i1, <1 x i1>, <1 x i1>, i32)
-define signext i1 @vpreduce_umin_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_v1i1(i1 zeroext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_umin_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_umin_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_umin_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_umin_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.v32i1(i1, <32 x i1>, <32 x i1>, i32)
-define signext i1 @vpreduce_umin_v32i1(i1 signext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_v32i1(i1 zeroext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.v32i1(i1 %s, <32 x i1> %v, <32 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.v64i1(i1, <64 x i1>, <64 x i1>, i32)
-define signext i1 @vpreduce_umin_v64i1(i1 signext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_v64i1(i1 zeroext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_v64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.v2i1(i1, <2 x i1>, <2 x i1>, i32)
-define signext i1 @vpreduce_mul_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_v2i1(i1 zeroext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.v4i1(i1, <4 x i1>, <4 x i1>, i32)
-define signext i1 @vpreduce_mul_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_v4i1(i1 zeroext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.v8i1(i1, <8 x i1>, <8 x i1>, i32)
-define signext i1 @vpreduce_mul_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_v8i1(i1 zeroext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.v16i1(i1, <16 x i1>, <16 x i1>, i32)
-define signext i1 @vpreduce_mul_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.v32i1(i1, <32 x i1>, <32 x i1>, i32)
-define signext i1 @vpreduce_mul_v32i1(i1 signext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_v32i1(i1 zeroext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.v32i1(i1 %s, <32 x i1> %v, <32 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.v64i1(i1, <64 x i1>, <64 x i1>, i32)
-define signext i1 @vpreduce_mul_v64i1(i1 signext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_v64i1(i1 zeroext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_v64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
ret i1 %r
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}
declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
-define signext i1 @vreduce_or_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_or_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_or_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
-define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_xor_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_xor_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
-define signext i1 @vreduce_and_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_and_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_and_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>)
-define signext i1 @vreduce_umax_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_umax_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_umax_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>)
-define signext i1 @vreduce_smax_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_smax_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_smax_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>)
-define signext i1 @vreduce_umin_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_umin_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_umin_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>)
-define signext i1 @vreduce_smin_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_smin_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_smin_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
-define signext i1 @vreduce_or_v2i1(<2 x i1> %v) {
+define zeroext i1 @vreduce_or_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_or_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
-define signext i1 @vreduce_xor_v2i1(<2 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_xor_v2i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_xor_v2i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_xor_v2i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_xor_v2i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
-define signext i1 @vreduce_and_v2i1(<2 x i1> %v) {
+define zeroext i1 @vreduce_and_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_and_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
-define signext i1 @vreduce_umax_v2i1(<2 x i1> %v) {
+define zeroext i1 @vreduce_umax_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_umax_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
-define signext i1 @vreduce_smax_v2i1(<2 x i1> %v) {
+define zeroext i1 @vreduce_smax_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_smax_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
-define signext i1 @vreduce_umin_v2i1(<2 x i1> %v) {
+define zeroext i1 @vreduce_umin_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_umin_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
-define signext i1 @vreduce_smin_v2i1(<2 x i1> %v) {
+define zeroext i1 @vreduce_smin_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_smin_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
-define signext i1 @vreduce_or_v4i1(<4 x i1> %v) {
+define zeroext i1 @vreduce_or_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_or_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
-define signext i1 @vreduce_xor_v4i1(<4 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_xor_v4i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_xor_v4i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_xor_v4i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_xor_v4i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_v4i1(<4 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
-define signext i1 @vreduce_and_v4i1(<4 x i1> %v) {
+define zeroext i1 @vreduce_and_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_and_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1>)
-define signext i1 @vreduce_umax_v4i1(<4 x i1> %v) {
+define zeroext i1 @vreduce_umax_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_umax_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.v4i1(<4 x i1>)
-define signext i1 @vreduce_smax_v4i1(<4 x i1> %v) {
+define zeroext i1 @vreduce_smax_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_smax_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.v4i1(<4 x i1>)
-define signext i1 @vreduce_umin_v4i1(<4 x i1> %v) {
+define zeroext i1 @vreduce_umin_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_umin_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.v4i1(<4 x i1>)
-define signext i1 @vreduce_smin_v4i1(<4 x i1> %v) {
+define zeroext i1 @vreduce_smin_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_smin_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
-define signext i1 @vreduce_or_v8i1(<8 x i1> %v) {
+define zeroext i1 @vreduce_or_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_or_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
-define signext i1 @vreduce_xor_v8i1(<8 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_xor_v8i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_xor_v8i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_xor_v8i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_xor_v8i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_v8i1(<8 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
-define signext i1 @vreduce_and_v8i1(<8 x i1> %v) {
+define zeroext i1 @vreduce_and_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_and_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.v8i1(<8 x i1>)
-define signext i1 @vreduce_umax_v8i1(<8 x i1> %v) {
+define zeroext i1 @vreduce_umax_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_umax_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.v8i1(<8 x i1>)
-define signext i1 @vreduce_smax_v8i1(<8 x i1> %v) {
+define zeroext i1 @vreduce_smax_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_smax_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.v8i1(<8 x i1>)
-define signext i1 @vreduce_umin_v8i1(<8 x i1> %v) {
+define zeroext i1 @vreduce_umin_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_umin_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.v8i1(<8 x i1>)
-define signext i1 @vreduce_smin_v8i1(<8 x i1> %v) {
+define zeroext i1 @vreduce_smin_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_smin_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
-define signext i1 @vreduce_or_v16i1(<16 x i1> %v) {
+define zeroext i1 @vreduce_or_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_or_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)
-define signext i1 @vreduce_xor_v16i1(<16 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_xor_v16i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_xor_v16i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_xor_v16i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_xor_v16i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_v16i1(<16 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
-define signext i1 @vreduce_and_v16i1(<16 x i1> %v) {
+define zeroext i1 @vreduce_and_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_and_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.v16i1(<16 x i1>)
-define signext i1 @vreduce_umax_v16i1(<16 x i1> %v) {
+define zeroext i1 @vreduce_umax_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_umax_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.v16i1(<16 x i1>)
-define signext i1 @vreduce_smax_v16i1(<16 x i1> %v) {
+define zeroext i1 @vreduce_smax_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_smax_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.v16i1(<16 x i1>)
-define signext i1 @vreduce_umin_v16i1(<16 x i1> %v) {
+define zeroext i1 @vreduce_umin_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_umin_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.v16i1(<16 x i1>)
-define signext i1 @vreduce_smin_v16i1(<16 x i1> %v) {
+define zeroext i1 @vreduce_smin_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_smin_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
-define signext i1 @vreduce_or_v32i1(<32 x i1> %v) {
+define zeroext i1 @vreduce_or_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_or_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmor.mm v8, v0, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: seqz a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_or_v32i1:
; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; LMULMAX8-NEXT: vcpop.m a0, v0
-; LMULMAX8-NEXT: seqz a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: snez a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>)
-define signext i1 @vreduce_xor_v32i1(<32 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_xor_v32i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV32-NEXT: vmxor.mm v8, v0, v8
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_xor_v32i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV64-NEXT: vmxor.mm v8, v0, v8
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_xor_v32i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: li a0, 32
-; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
+define zeroext i1 @vreduce_xor_v32i1(<32 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_xor_v32i1:
+; LMULMAX1: # %bb.0:
+; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX1-NEXT: vmxor.mm v8, v0, v8
+; LMULMAX1-NEXT: vcpop.m a0, v8
+; LMULMAX1-NEXT: andi a0, a0, 1
+; LMULMAX1-NEXT: ret
;
-; LMULMAX8-RV64-LABEL: vreduce_xor_v32i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: li a0, 32
-; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+; LMULMAX8-LABEL: vreduce_xor_v32i1:
+; LMULMAX8: # %bb.0:
+; LMULMAX8-NEXT: li a0, 32
+; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; LMULMAX8-NEXT: vcpop.m a0, v0
+; LMULMAX8-NEXT: andi a0, a0, 1
+; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
-define signext i1 @vreduce_and_v32i1(<32 x i1> %v) {
+define zeroext i1 @vreduce_and_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_and_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmnand.mm v8, v0, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: snez a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_and_v32i1:
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8
-; LMULMAX8-NEXT: snez a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.v32i1(<32 x i1>)
-define signext i1 @vreduce_umax_v32i1(<32 x i1> %v) {
+define zeroext i1 @vreduce_umax_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_umax_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmor.mm v8, v0, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: seqz a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_umax_v32i1:
; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; LMULMAX8-NEXT: vcpop.m a0, v0
-; LMULMAX8-NEXT: seqz a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: snez a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.v32i1(<32 x i1>)
-define signext i1 @vreduce_smax_v32i1(<32 x i1> %v) {
+define zeroext i1 @vreduce_smax_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_smax_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmnand.mm v8, v0, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: snez a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_smax_v32i1:
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8
-; LMULMAX8-NEXT: snez a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.v32i1(<32 x i1>)
-define signext i1 @vreduce_umin_v32i1(<32 x i1> %v) {
+define zeroext i1 @vreduce_umin_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_umin_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmnand.mm v8, v0, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: snez a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_umin_v32i1:
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8
-; LMULMAX8-NEXT: snez a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.v32i1(<32 x i1>)
-define signext i1 @vreduce_smin_v32i1(<32 x i1> %v) {
+define zeroext i1 @vreduce_smin_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_smin_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmor.mm v8, v0, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: seqz a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_smin_v32i1:
; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; LMULMAX8-NEXT: vcpop.m a0, v0
-; LMULMAX8-NEXT: seqz a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: snez a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
-define signext i1 @vreduce_or_v64i1(<64 x i1> %v) {
+define zeroext i1 @vreduce_or_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_or_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmor.mm v9, v0, v9
; LMULMAX1-NEXT: vmor.mm v8, v9, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: seqz a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_or_v64i1:
; LMULMAX8-NEXT: li a0, 64
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; LMULMAX8-NEXT: vcpop.m a0, v0
-; LMULMAX8-NEXT: seqz a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: snez a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.v64i1(<64 x i1>)
-define signext i1 @vreduce_xor_v64i1(<64 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_xor_v64i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV32-NEXT: vmxor.mm v8, v8, v10
-; LMULMAX1-RV32-NEXT: vmxor.mm v9, v0, v9
-; LMULMAX1-RV32-NEXT: vmxor.mm v8, v9, v8
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_xor_v64i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV64-NEXT: vmxor.mm v8, v8, v10
-; LMULMAX1-RV64-NEXT: vmxor.mm v9, v0, v9
-; LMULMAX1-RV64-NEXT: vmxor.mm v8, v9, v8
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_xor_v64i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: li a0, 64
-; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
+define zeroext i1 @vreduce_xor_v64i1(<64 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_xor_v64i1:
+; LMULMAX1: # %bb.0:
+; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX1-NEXT: vmxor.mm v8, v8, v10
+; LMULMAX1-NEXT: vmxor.mm v9, v0, v9
+; LMULMAX1-NEXT: vmxor.mm v8, v9, v8
+; LMULMAX1-NEXT: vcpop.m a0, v8
+; LMULMAX1-NEXT: andi a0, a0, 1
+; LMULMAX1-NEXT: ret
;
-; LMULMAX8-RV64-LABEL: vreduce_xor_v64i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: li a0, 64
-; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+; LMULMAX8-LABEL: vreduce_xor_v64i1:
+; LMULMAX8: # %bb.0:
+; LMULMAX8-NEXT: li a0, 64
+; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; LMULMAX8-NEXT: vcpop.m a0, v0
+; LMULMAX8-NEXT: andi a0, a0, 1
+; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.v64i1(<64 x i1>)
-define signext i1 @vreduce_and_v64i1(<64 x i1> %v) {
+define zeroext i1 @vreduce_and_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_and_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmand.mm v9, v0, v9
; LMULMAX1-NEXT: vmnand.mm v8, v9, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: snez a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_and_v64i1:
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8
-; LMULMAX8-NEXT: snez a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.v64i1(<64 x i1>)
-define signext i1 @vreduce_umax_v64i1(<64 x i1> %v) {
+define zeroext i1 @vreduce_umax_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_umax_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmor.mm v9, v0, v9
; LMULMAX1-NEXT: vmor.mm v8, v9, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: seqz a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_umax_v64i1:
; LMULMAX8-NEXT: li a0, 64
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; LMULMAX8-NEXT: vcpop.m a0, v0
-; LMULMAX8-NEXT: seqz a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: snez a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.v64i1(<64 x i1>)
-define signext i1 @vreduce_smax_v64i1(<64 x i1> %v) {
+define zeroext i1 @vreduce_smax_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_smax_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmand.mm v9, v0, v9
; LMULMAX1-NEXT: vmnand.mm v8, v9, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: snez a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_smax_v64i1:
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8
-; LMULMAX8-NEXT: snez a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.v64i1(<64 x i1>)
-define signext i1 @vreduce_umin_v64i1(<64 x i1> %v) {
+define zeroext i1 @vreduce_umin_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_umin_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmand.mm v9, v0, v9
; LMULMAX1-NEXT: vmnand.mm v8, v9, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: snez a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_umin_v64i1:
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; LMULMAX8-NEXT: vmnot.m v8, v0
; LMULMAX8-NEXT: vcpop.m a0, v8
-; LMULMAX8-NEXT: snez a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.v64i1(<64 x i1>)
-define signext i1 @vreduce_smin_v64i1(<64 x i1> %v) {
+define zeroext i1 @vreduce_smin_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_smin_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmor.mm v9, v0, v9
; LMULMAX1-NEXT: vmor.mm v8, v9, v8
; LMULMAX1-NEXT: vcpop.m a0, v8
-; LMULMAX1-NEXT: seqz a0, a0
-; LMULMAX1-NEXT: addi a0, a0, -1
+; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: ret
;
; LMULMAX8-LABEL: vreduce_smin_v64i1:
; LMULMAX8-NEXT: li a0, 64
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; LMULMAX8-NEXT: vcpop.m a0, v0
-; LMULMAX8-NEXT: seqz a0, a0
-; LMULMAX8-NEXT: addi a0, a0, -1
+; LMULMAX8-NEXT: snez a0, a0
; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>)
-define signext i1 @vreduce_add_v1i1(<1 x i1> %v) {
+define zeroext i1 @vreduce_add_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_add_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfirst.m a0, v0
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>)
-define signext i1 @vreduce_add_v2i1(<2 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_add_v2i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_add_v2i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_add_v2i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_add_v2i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_add_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1>)
-define signext i1 @vreduce_add_v4i1(<4 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_add_v4i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_add_v4i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_add_v4i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_add_v4i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_add_v4i1(<4 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.v8i1(<8 x i1>)
-define signext i1 @vreduce_add_v8i1(<8 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_add_v8i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_add_v8i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_add_v8i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_add_v8i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_add_v8i1(<8 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.v16i1(<16 x i1>)
-define signext i1 @vreduce_add_v16i1(<16 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_add_v16i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_add_v16i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_add_v16i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
-;
-; LMULMAX8-RV64-LABEL: vreduce_add_v16i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+define zeroext i1 @vreduce_add_v16i1(<16 x i1> %v) {
+; CHECK-LABEL: vreduce_add_v16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.v32i1(<32 x i1>)
-define signext i1 @vreduce_add_v32i1(<32 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_add_v32i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV32-NEXT: vmxor.mm v8, v0, v8
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_add_v32i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV64-NEXT: vmxor.mm v8, v0, v8
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_add_v32i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: li a0, 32
-; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
+define zeroext i1 @vreduce_add_v32i1(<32 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_add_v32i1:
+; LMULMAX1: # %bb.0:
+; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX1-NEXT: vmxor.mm v8, v0, v8
+; LMULMAX1-NEXT: vcpop.m a0, v8
+; LMULMAX1-NEXT: andi a0, a0, 1
+; LMULMAX1-NEXT: ret
;
-; LMULMAX8-RV64-LABEL: vreduce_add_v32i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: li a0, 32
-; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+; LMULMAX8-LABEL: vreduce_add_v32i1:
+; LMULMAX8: # %bb.0:
+; LMULMAX8-NEXT: li a0, 32
+; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; LMULMAX8-NEXT: vcpop.m a0, v0
+; LMULMAX8-NEXT: andi a0, a0, 1
+; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.v64i1(<64 x i1>)
-define signext i1 @vreduce_add_v64i1(<64 x i1> %v) {
-; LMULMAX1-RV32-LABEL: vreduce_add_v64i1:
-; LMULMAX1-RV32: # %bb.0:
-; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV32-NEXT: vmxor.mm v8, v8, v10
-; LMULMAX1-RV32-NEXT: vmxor.mm v9, v0, v9
-; LMULMAX1-RV32-NEXT: vmxor.mm v8, v9, v8
-; LMULMAX1-RV32-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV32-NEXT: slli a0, a0, 31
-; LMULMAX1-RV32-NEXT: srai a0, a0, 31
-; LMULMAX1-RV32-NEXT: ret
-;
-; LMULMAX1-RV64-LABEL: vreduce_add_v64i1:
-; LMULMAX1-RV64: # %bb.0:
-; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; LMULMAX1-RV64-NEXT: vmxor.mm v8, v8, v10
-; LMULMAX1-RV64-NEXT: vmxor.mm v9, v0, v9
-; LMULMAX1-RV64-NEXT: vmxor.mm v8, v9, v8
-; LMULMAX1-RV64-NEXT: vcpop.m a0, v8
-; LMULMAX1-RV64-NEXT: slli a0, a0, 63
-; LMULMAX1-RV64-NEXT: srai a0, a0, 63
-; LMULMAX1-RV64-NEXT: ret
-;
-; LMULMAX8-RV32-LABEL: vreduce_add_v64i1:
-; LMULMAX8-RV32: # %bb.0:
-; LMULMAX8-RV32-NEXT: li a0, 64
-; LMULMAX8-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; LMULMAX8-RV32-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV32-NEXT: slli a0, a0, 31
-; LMULMAX8-RV32-NEXT: srai a0, a0, 31
-; LMULMAX8-RV32-NEXT: ret
+define zeroext i1 @vreduce_add_v64i1(<64 x i1> %v) {
+; LMULMAX1-LABEL: vreduce_add_v64i1:
+; LMULMAX1: # %bb.0:
+; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX1-NEXT: vmxor.mm v8, v8, v10
+; LMULMAX1-NEXT: vmxor.mm v9, v0, v9
+; LMULMAX1-NEXT: vmxor.mm v8, v9, v8
+; LMULMAX1-NEXT: vcpop.m a0, v8
+; LMULMAX1-NEXT: andi a0, a0, 1
+; LMULMAX1-NEXT: ret
;
-; LMULMAX8-RV64-LABEL: vreduce_add_v64i1:
-; LMULMAX8-RV64: # %bb.0:
-; LMULMAX8-RV64-NEXT: li a0, 64
-; LMULMAX8-RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; LMULMAX8-RV64-NEXT: vcpop.m a0, v0
-; LMULMAX8-RV64-NEXT: slli a0, a0, 63
-; LMULMAX8-RV64-NEXT: srai a0, a0, 63
-; LMULMAX8-RV64-NEXT: ret
+; LMULMAX8-LABEL: vreduce_add_v64i1:
+; LMULMAX8: # %bb.0:
+; LMULMAX8-NEXT: li a0, 64
+; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; LMULMAX8-NEXT: vcpop.m a0, v0
+; LMULMAX8-NEXT: andi a0, a0, 1
+; LMULMAX8-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> %v)
ret i1 %red
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; LMULMAX1-RV32: {{.*}}
+; LMULMAX1-RV64: {{.*}}
+; LMULMAX8-RV32: {{.*}}
+; LMULMAX8-RV64: {{.*}}
declare i1 @llvm.vp.reduce.and.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_and_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_or_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_xor_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_nxv1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_nxv1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_and_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_or_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_xor_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_nxv2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_nxv2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_and_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_or_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_xor_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_nxv4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_nxv4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_and_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_or_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_xor_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_nxv8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_nxv8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_and_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_or_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_xor_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_nxv16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_nxv16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_and_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_or_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_xor_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_nxv32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_nxv32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.or.nxv40i1(i1, <vscale x 40 x i1>, <vscale x 40 x i1>, i32)
-define signext i1 @vpreduce_or_nxv40i1(i1 signext %s, <vscale x 40 x i1> %v, <vscale x 40 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv40i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv40i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv40i1(i1 zeroext %s, <vscale x 40 x i1> %v, <vscale x 40 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv40i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv40i1(i1 %s, <vscale x 40 x i1> %v, <vscale x 40 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.and.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_and_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_and_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.and.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.or.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_or_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.xor.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_xor_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_xor_nxv64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_xor_nxv64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_xor_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_xor_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.xor.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.or.nxv128i1(i1, <vscale x 128 x i1>, <vscale x 128 x i1>, i32)
-define signext i1 @vpreduce_or_nxv128i1(i1 signext %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_or_nxv128i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v11, v0
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: sub a3, a1, a2
-; RV32-NEXT: sltu a4, a1, a3
-; RV32-NEXT: addi a4, a4, -1
-; RV32-NEXT: and a3, a4, a3
-; RV32-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vcpop.m a3, v8, v0.t
-; RV32-NEXT: snez a3, a3
-; RV32-NEXT: bltu a1, a2, .LBB22_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: mv a1, a2
-; RV32-NEXT: .LBB22_2:
-; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vcpop.m a1, v11, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a3, a0
-; RV32-NEXT: or a0, a0, a1
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_or_nxv128i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v11, v0
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 3
-; RV64-NEXT: sub a3, a1, a2
-; RV64-NEXT: sltu a4, a1, a3
-; RV64-NEXT: addi a4, a4, -1
-; RV64-NEXT: and a3, a4, a3
-; RV64-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v10
-; RV64-NEXT: vcpop.m a3, v8, v0.t
-; RV64-NEXT: snez a3, a3
-; RV64-NEXT: bltu a1, a2, .LBB22_2
-; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a1, a2
-; RV64-NEXT: .LBB22_2:
-; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v9
-; RV64-NEXT: vcpop.m a1, v11, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a3, a0
-; RV64-NEXT: or a0, a0, a1
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_or_nxv128i1(i1 zeroext %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_or_nxv128i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vcpop.m a3, v8, v0.t
+; CHECK-NEXT: snez a3, a3
+; CHECK-NEXT: bltu a1, a2, .LBB22_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: .LBB22_2:
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vcpop.m a1, v11, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a3, a0
+; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv128i1(i1 %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_add_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_nxv1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_nxv1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_add_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_nxv2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_nxv2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_add_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_nxv4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_nxv4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_add_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_nxv8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_nxv8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_add_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_nxv16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_nxv16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_add_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_nxv32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_nxv32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.add.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_add_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_add_nxv64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: xor a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_add_nxv64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_add_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_add_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: xor a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.add.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smax.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_smax_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_smax_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_smax_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_smax_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_smax_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_smax_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smax.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_smax_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_smax_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_smax_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smax.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.smin.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_smin_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_nxv1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_nxv1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_smin_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_nxv2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_nxv2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_smin_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_nxv4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_nxv4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_smin_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_nxv8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_nxv8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_smin_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_nxv16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_nxv16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_smin_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_nxv32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_nxv32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.smin.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_smin_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_smin_nxv64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_smin_nxv64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_smin_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_smin_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.smin.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_umax_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_umax_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_umax_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_umax_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_umax_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_umax_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umax.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_umax_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpreduce_umax_nxv64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vcpop.m a1, v9, v0.t
-; RV32-NEXT: snez a1, a1
-; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpreduce_umax_nxv64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vcpop.m a1, v9, v0.t
-; RV64-NEXT: snez a1, a1
-; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vpreduce_umax_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpreduce_umax_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a1, v9, v0.t
+; CHECK-NEXT: snez a1, a1
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umax.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
}
declare i1 @llvm.vp.reduce.umin.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_umin_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_umin_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_umin_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_umin_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_umin_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_umin_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.umin.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_umin_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_umin_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umin_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.umin.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
-define signext i1 @vpreduce_mul_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
-define signext i1 @vpreduce_mul_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
-define signext i1 @vpreduce_mul_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
-define signext i1 @vpreduce_mul_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
-define signext i1 @vpreduce_mul_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
-define signext i1 @vpreduce_mul_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i1 %r
declare i1 @llvm.vp.reduce.mul.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
-define signext i1 @vpreduce_mul_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+define zeroext i1 @vpreduce_mul_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_mul_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.mul.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
ret i1 %r
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}
declare i1 @llvm.vector.reduce.or.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_or_nxv1i1(<vscale x 1 x i1> %v) {
+define zeroext i1 @vreduce_or_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_or_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_xor_nxv1i1(<vscale x 1 x i1> %v) {
-; RV32-LABEL: vreduce_xor_nxv1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_xor_nxv1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {
+define zeroext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_umax_nxv1i1(<vscale x 1 x i1> %v) {
+define zeroext i1 @vreduce_umax_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_smax_nxv1i1(<vscale x 1 x i1> %v) {
+define zeroext i1 @vreduce_smax_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_smax_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_umin_nxv1i1(<vscale x 1 x i1> %v) {
+define zeroext i1 @vreduce_umin_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_smin_nxv1i1(<vscale x 1 x i1> %v) {
+define zeroext i1 @vreduce_smin_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_smin_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_or_nxv2i1(<vscale x 2 x i1> %v) {
+define zeroext i1 @vreduce_or_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_or_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_xor_nxv2i1(<vscale x 2 x i1> %v) {
-; RV32-LABEL: vreduce_xor_nxv2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_xor_nxv2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {
+define zeroext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_umax_nxv2i1(<vscale x 2 x i1> %v) {
+define zeroext i1 @vreduce_umax_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_smax_nxv2i1(<vscale x 2 x i1> %v) {
+define zeroext i1 @vreduce_smax_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_smax_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_umin_nxv2i1(<vscale x 2 x i1> %v) {
+define zeroext i1 @vreduce_umin_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_smin_nxv2i1(<vscale x 2 x i1> %v) {
+define zeroext i1 @vreduce_smin_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_smin_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_or_nxv4i1(<vscale x 4 x i1> %v) {
+define zeroext i1 @vreduce_or_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_or_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_xor_nxv4i1(<vscale x 4 x i1> %v) {
-; RV32-LABEL: vreduce_xor_nxv4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_xor_nxv4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {
+define zeroext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_umax_nxv4i1(<vscale x 4 x i1> %v) {
+define zeroext i1 @vreduce_umax_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_smax_nxv4i1(<vscale x 4 x i1> %v) {
+define zeroext i1 @vreduce_smax_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_smax_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_umin_nxv4i1(<vscale x 4 x i1> %v) {
+define zeroext i1 @vreduce_umin_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_smin_nxv4i1(<vscale x 4 x i1> %v) {
+define zeroext i1 @vreduce_smin_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_smin_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_or_nxv8i1(<vscale x 8 x i1> %v) {
+define zeroext i1 @vreduce_or_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_or_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_xor_nxv8i1(<vscale x 8 x i1> %v) {
-; RV32-LABEL: vreduce_xor_nxv8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_xor_nxv8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {
+define zeroext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_umax_nxv8i1(<vscale x 8 x i1> %v) {
+define zeroext i1 @vreduce_umax_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_umax_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_smax_nxv8i1(<vscale x 8 x i1> %v) {
+define zeroext i1 @vreduce_smax_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_smax_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_umin_nxv8i1(<vscale x 8 x i1> %v) {
+define zeroext i1 @vreduce_umin_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_umin_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_smin_nxv8i1(<vscale x 8 x i1> %v) {
+define zeroext i1 @vreduce_smin_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_smin_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_or_nxv16i1(<vscale x 16 x i1> %v) {
+define zeroext i1 @vreduce_or_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_or_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_xor_nxv16i1(<vscale x 16 x i1> %v) {
-; RV32-LABEL: vreduce_xor_nxv16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_xor_nxv16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {
+define zeroext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_umax_nxv16i1(<vscale x 16 x i1> %v) {
+define zeroext i1 @vreduce_umax_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_umax_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_smax_nxv16i1(<vscale x 16 x i1> %v) {
+define zeroext i1 @vreduce_smax_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_smax_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_umin_nxv16i1(<vscale x 16 x i1> %v) {
+define zeroext i1 @vreduce_umin_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_umin_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_smin_nxv16i1(<vscale x 16 x i1> %v) {
+define zeroext i1 @vreduce_smin_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_smin_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_or_nxv32i1(<vscale x 32 x i1> %v) {
+define zeroext i1 @vreduce_or_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_or_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_xor_nxv32i1(<vscale x 32 x i1> %v) {
-; RV32-LABEL: vreduce_xor_nxv32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_xor_nxv32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {
+define zeroext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_umax_nxv32i1(<vscale x 32 x i1> %v) {
+define zeroext i1 @vreduce_umax_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_umax_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_smax_nxv32i1(<vscale x 32 x i1> %v) {
+define zeroext i1 @vreduce_smax_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_smax_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_umin_nxv32i1(<vscale x 32 x i1> %v) {
+define zeroext i1 @vreduce_umin_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_umin_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_smin_nxv32i1(<vscale x 32 x i1> %v) {
+define zeroext i1 @vreduce_smin_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_smin_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.or.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_or_nxv64i1(<vscale x 64 x i1> %v) {
+define zeroext i1 @vreduce_or_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_or_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.or.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_xor_nxv64i1(<vscale x 64 x i1> %v) {
-; RV32-LABEL: vreduce_xor_nxv64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_xor_nxv64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_xor_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_xor_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {
+define zeroext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umax.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_umax_nxv64i1(<vscale x 64 x i1> %v) {
+define zeroext i1 @vreduce_umax_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_umax_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umax.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smax.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_smax_nxv64i1(<vscale x 64 x i1> %v) {
+define zeroext i1 @vreduce_smax_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_smax_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smax.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.umin.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_umin_nxv64i1(<vscale x 64 x i1> %v) {
+define zeroext i1 @vreduce_umin_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_umin_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v8, v0
; CHECK-NEXT: vcpop.m a0, v8
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.umin.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_smin_nxv64i1(<vscale x 64 x i1> %v) {
+define zeroext i1 @vreduce_smin_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_smin_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a0, v0
-; CHECK-NEXT: seqz a0, a0
-; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
declare i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1>)
-define signext i1 @vreduce_add_nxv1i1(<vscale x 1 x i1> %v) {
-; RV32-LABEL: vreduce_add_nxv1i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_add_nxv1i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_add_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1>)
-define signext i1 @vreduce_add_nxv2i1(<vscale x 2 x i1> %v) {
-; RV32-LABEL: vreduce_add_nxv2i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_add_nxv2i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_add_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1>)
-define signext i1 @vreduce_add_nxv4i1(<vscale x 4 x i1> %v) {
-; RV32-LABEL: vreduce_add_nxv4i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_add_nxv4i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_add_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1>)
-define signext i1 @vreduce_add_nxv8i1(<vscale x 8 x i1> %v) {
-; RV32-LABEL: vreduce_add_nxv8i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_add_nxv8i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_add_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1>)
-define signext i1 @vreduce_add_nxv16i1(<vscale x 16 x i1> %v) {
-; RV32-LABEL: vreduce_add_nxv16i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_add_nxv16i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_add_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1>)
-define signext i1 @vreduce_add_nxv32i1(<vscale x 32 x i1> %v) {
-; RV32-LABEL: vreduce_add_nxv32i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_add_nxv32i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_add_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1>)
-define signext i1 @vreduce_add_nxv64i1(<vscale x 64 x i1> %v) {
-; RV32-LABEL: vreduce_add_nxv64i1:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; RV32-NEXT: vcpop.m a0, v0
-; RV32-NEXT: slli a0, a0, 31
-; RV32-NEXT: srai a0, a0, 31
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vreduce_add_nxv64i1:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; RV64-NEXT: vcpop.m a0, v0
-; RV64-NEXT: slli a0, a0, 63
-; RV64-NEXT: srai a0, a0, 63
-; RV64-NEXT: ret
+define zeroext i1 @vreduce_add_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_add_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: andi a0, a0, 1
+; CHECK-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}