[neurun] Introduce ITensor/ICLTensor (#3719)

* [neurun] Introduce ITensor/ICLTensor

This commit introduces `neurun::backend::operand::ITensor`/`neurun::backend::acl_cl::operand::ICLTensor` since we want to define internal interface of `ITensor` that is an common interface of all backends.
In case of `ACL` backend, It should be defined to `ACL` wrapper classes inherited to internal `ICLTensor`.

Signed-off-by: sjsujinkim <sjsujin.kim@samsung.com>
* Include some functions of derived classes

diff --git a/runtimes/neurun/src/backend/acl_cl/operand/ICLTensor.cc b/runtimes/neurun/src/backend/acl_cl/operand/ICLTensor.cc
new file mode 100644 (file)
index 0000000..a037222
--- /dev/null
+++ b/runtimes/neurun/src/backend/acl_cl/operand/ICLTensor.cc
@@ -0,0 +1,37 @@
+#include "ICLTensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+size_t ICLTensor::total_size() const { return info()->total_size(); }
+
+size_t ICLTensor::dimension(size_t index) const { return info()->dimension(index); }
+
+size_t ICLTensor::num_dimensions() const { return info()->num_dimensions(); }
+
+arm_compute::DataType ICLTensor::data_type() const { return info()->data_type(); }
+
+uint8_t *ICLTensor::buffer() const { return handle()->buffer(); }
+
+const cl::Buffer &ICLTensor::cl_buffer() const { return handle()->cl_buffer(); }
+
+arm_compute::ITensorInfo *ICLTensor::info() const { return handle()->info(); }
+
+arm_compute::ITensorInfo *ICLTensor::info() { return handle()->info(); }
+
+void ICLTensor::map(cl::CommandQueue &q, bool blocking) { return handle()->map(q, blocking); }
+
+void ICLTensor::unmap(cl::CommandQueue &q) { return handle()->unmap(q); }
+
+void ICLTensor::clear(cl::CommandQueue &q) { return handle()->clear(q); }
+
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun

diff --git a/runtimes/neurun/src/backend/acl_cl/operand/ICLTensor.h b/runtimes/neurun/src/backend/acl_cl/operand/ICLTensor.h
new file mode 100644 (file)
index 0000000..d98f4ff
--- /dev/null
+++ b/runtimes/neurun/src/backend/acl_cl/operand/ICLTensor.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_ACL_CL_OPERAND_I_CL_TENSOR_H__
+#define __NEURUN_BACKEND_ACL_CL_OPERAND_I_CL_TENSOR_H__
+
+#include <arm_compute/core/ITensorInfo.h>
+#include <arm_compute/core/CL/ICLTensor.h>
+#include "backend/interface/operand/ITensor.h"
+
+namespace neurun
+{
+namespace backend
+{
+namespace acl_cl
+{
+namespace operand
+{
+
+class ICLTensor : public ::neurun::backend::operand::ITensor
+{
+public:
+  ICLTensor() = default;
+  ICLTensor(const ICLTensor &) = delete;
+  ICLTensor &operator=(const ICLTensor &) = delete;
+  ICLTensor(ICLTensor &&) = default;
+  ICLTensor &operator=(ICLTensor &&) = default;
+  virtual ~ICLTensor() = default;
+
+public:
+  virtual arm_compute::ICLTensor *handle() = 0;
+  virtual arm_compute::ICLTensor *handle() const = 0;
+
+public:
+  uint8_t *buffer() const override;
+  size_t total_size() const override;
+  size_t dimension(size_t index) const override;
+  size_t num_dimensions() const override;
+
+public:
+  arm_compute::DataType data_type() const;
+  const cl::Buffer &cl_buffer() const;
+  arm_compute::ITensorInfo *info() const;
+  arm_compute::ITensorInfo *info();
+  void map(cl::CommandQueue &q, bool blocking = true);
+  void unmap(cl::CommandQueue &q);
+  void clear(cl::CommandQueue &q);
+
+protected:
+  virtual uint8_t *doMap(cl::CommandQueue &q, bool blocking) = 0;
+  virtual void doUnmap(cl::CommandQueue &q) = 0;
+};
+
+} // namespace operand
+} // namespace acl_cl
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_ACL_CL_OPERAND_I_CL_TENSOR_H__

diff --git a/runtimes/neurun/src/backend/interface/operand/ITensor.h b/runtimes/neurun/src/backend/interface/operand/ITensor.h
new file mode 100644 (file)
index 0000000..61e3687
--- /dev/null
+++ b/runtimes/neurun/src/backend/interface/operand/ITensor.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd. All Rights Reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NEURUN_BACKEND_OPERAND_I_TENSOR_H__
+#define __NEURUN_BACKEND_OPERAND_I_TENSOR_H__
+
+#include <cstring>
+#include <cstdint>
+
+namespace neurun
+{
+namespace backend
+{
+namespace operand
+{
+
+class ITensor
+{
+public:
+  virtual ~ITensor() = default;
+
+public:
+  virtual uint8_t *buffer() const = 0;
+  virtual size_t total_size() const = 0;
+  virtual size_t dimension(size_t index) const = 0;
+  virtual size_t num_dimensions() const = 0;
+};
+
+} // namespace operand
+} // namespace backend
+} // namespace neurun
+
+#endif // __NEURUN_BACKEND_OPERAND_I_TENSOR_H__