if (host->use_external_dma)
sdhci_external_dma_pre_transfer(host, cmd);
+ if (host->quirks2 & SDHCI_QUIRK2_SPURIOUS_INT_RESP) {
+ host->ier |= SDHCI_INT_RESPONSE;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
+
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
return true;
if (intmask & SDHCI_INT_TIMEOUT) {
host->cmd->error = -ETIMEDOUT;
sdhci_err_stats_inc(host, CMD_TIMEOUT);
+ if (host->quirks2 & SDHCI_QUIRK2_SPURIOUS_INT_RESP) {
+ host->ier &= ~SDHCI_INT_RESPONSE;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
} else {
host->cmd->error = -EILSEQ;
if (!mmc_op_tuning(host->cmd->opcode))
#define SDHCI_QUIRK2_NO_SDR50 (1<<20)
#define SDHCI_QUIRK2_NO_SDR104 (1<<21)
+/* Command timeouts may generate a trailing INT_RESPONSE later */
+#define SDHCI_QUIRK2_SPURIOUS_INT_RESP (1<<31)
+
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
phys_addr_t mapbase; /* physical address base */