arm926ejs, davinci: add cpuinfo for dm365

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 02819f6..9ea9785 100644 (file)
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -146,13 +146,15 @@ static inline unsigned pll_prediv(volatile void *pllbase)
                return 8;
        else
                return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+       return pll_div(pllbase, PLLC_PREDIV);
 #endif
        return 1;
 }
 
 static inline unsigned pll_postdiv(volatile void *pllbase)
 {
-#ifdef CONFIG_SOC_DM355
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
        return pll_div(pllbase, PLLC_POSTDIV);
 #elif defined(CONFIG_SOC_DM6446)
        if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
@@ -171,9 +173,13 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 #endif
 
        /* the PLL might be bypassed */
-       if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
+       if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
                base /= pll_prediv(pllbase);
+#if defined(CONFIG_SOC_DM365)
+               base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
+#else
                base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+#endif
                base /= pll_postdiv(pllbase);
        }
        return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
@@ -184,8 +190,13 @@ int print_cpuinfo(void)
        /* REVISIT fetch and display CPU ID and revision information
         * too ... that will matter as more revisions appear.
         */
+#if defined(CONFIG_SOC_DM365)
+       printf("Cores: ARM %d MHz",
+                       pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+#else
        printf("Cores: ARM %d MHz",
                        pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+#endif
 
 #ifdef DSP_PLLDIV
        printf(", DSP %d MHz",
@@ -194,8 +205,13 @@ int print_cpuinfo(void)
 
        printf("\nDDR:   %d MHz\n",
                        /* DDR PHY uses an x2 input clock */
+#if defined(CONFIG_SOC_DM365)
+                       pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
+                               / 2);
+#else
                        pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
                                / 2);
+#endif
        return 0;
 }
 
@@ -205,6 +221,13 @@ unsigned int davinci_arm_clk_get()
        return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
 }
 #endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+       return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
 #endif /* CONFIG_DISPLAY_CPUINFO */
 #endif /* !CONFIG_SOC_DA8XX */
 

diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index 5d37616..606ed0b 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -76,4 +76,8 @@ struct dv_pll_regs {
 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
 
+#define ARM_PLLDIV     (offsetof(struct dv_pll_regs, plldiv2))
+#define DDR_PLLDIV     (offsetof(struct dv_pll_regs, plldiv7))
+
+unsigned int davinci_clk_get(unsigned int div);
 #endif /* _DV_PLL_DEFS_H_ */