net: lan966x: Add offload support for ets
authorHoratiu Vultur <horatiu.vultur@microchip.com>
Sun, 25 Sep 2022 18:46:33 +0000 (20:46 +0200)
committerDavid S. Miller <davem@davemloft.net>
Wed, 28 Sep 2022 08:36:28 +0000 (09:36 +0100)
Add ets qdisc which allows to mix strict priority with bandwidth-sharing
bands. The ets qdisc needs to be attached as root qdisc.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/microchip/lan966x/Makefile
drivers/net/ethernet/microchip/lan966x/lan966x_ets.c [new file with mode: 0644]
drivers/net/ethernet/microchip/lan966x/lan966x_main.h
drivers/net/ethernet/microchip/lan966x/lan966x_regs.h
drivers/net/ethernet/microchip/lan966x/lan966x_tc.c

index bc76949..7360c1c 100644 (file)
@@ -10,4 +10,4 @@ lan966x-switch-objs  := lan966x_main.o lan966x_phylink.o lan966x_port.o \
                        lan966x_vlan.o lan966x_fdb.o lan966x_mdb.o \
                        lan966x_ptp.o lan966x_fdma.o lan966x_lag.o \
                        lan966x_tc.o lan966x_mqprio.o lan966x_taprio.o \
-                       lan966x_tbf.o lan966x_cbs.o
+                       lan966x_tbf.o lan966x_cbs.o lan966x_ets.o
diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_ets.c b/drivers/net/ethernet/microchip/lan966x/lan966x_ets.c
new file mode 100644 (file)
index 0000000..8310d3f
--- /dev/null
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "lan966x_main.h"
+
+#define DWRR_COST_BIT_WIDTH    BIT(5)
+
+static u32 lan966x_ets_hw_cost(u32 w_min, u32 weight)
+{
+       u32 res;
+
+       /* Round half up: Multiply with 16 before division,
+        * add 8 and divide result with 16 again
+        */
+       res = (((DWRR_COST_BIT_WIDTH << 4) * w_min / weight) + 8) >> 4;
+       return max_t(u32, 1, res) - 1;
+}
+
+int lan966x_ets_add(struct lan966x_port *port,
+                   struct tc_ets_qopt_offload *qopt)
+{
+       struct tc_ets_qopt_offload_replace_params *params;
+       struct lan966x *lan966x = port->lan966x;
+       u32 w_min = 100;
+       u8 count = 0;
+       u32 se_idx;
+       u8 i;
+
+       /* Check the input */
+       if (qopt->parent != TC_H_ROOT)
+               return -EINVAL;
+
+       params = &qopt->replace_params;
+       if (params->bands != NUM_PRIO_QUEUES)
+               return -EINVAL;
+
+       for (i = 0; i < params->bands; ++i) {
+               /* In the switch the DWRR is always on the lowest consecutive
+                * priorities. Due to this, the first priority must map to the
+                * first DWRR band.
+                */
+               if (params->priomap[i] != (7 - i))
+                       return -EINVAL;
+
+               if (params->quanta[i] && params->weights[i] == 0)
+                       return -EINVAL;
+       }
+
+       se_idx = SE_IDX_PORT + port->chip_port;
+
+       /* Find minimum weight */
+       for (i = 0; i < params->bands; ++i) {
+               if (params->quanta[i] == 0)
+                       continue;
+
+               w_min = min(w_min, params->weights[i]);
+       }
+
+       for (i = 0; i < params->bands; ++i) {
+               if (params->quanta[i] == 0)
+                       continue;
+
+               ++count;
+
+               lan_wr(lan966x_ets_hw_cost(w_min, params->weights[i]),
+                      lan966x, QSYS_SE_DWRR_CFG(se_idx, 7 - i));
+       }
+
+       lan_rmw(QSYS_SE_CFG_SE_DWRR_CNT_SET(count) |
+               QSYS_SE_CFG_SE_RR_ENA_SET(0),
+               QSYS_SE_CFG_SE_DWRR_CNT |
+               QSYS_SE_CFG_SE_RR_ENA,
+               lan966x, QSYS_SE_CFG(se_idx));
+
+       return 0;
+}
+
+int lan966x_ets_del(struct lan966x_port *port,
+                   struct tc_ets_qopt_offload *qopt)
+{
+       struct lan966x *lan966x = port->lan966x;
+       u32 se_idx;
+       int i;
+
+       se_idx = SE_IDX_PORT + port->chip_port;
+
+       for (i = 0; i < NUM_PRIO_QUEUES; ++i)
+               lan_wr(0, lan966x, QSYS_SE_DWRR_CFG(se_idx, i));
+
+       lan_rmw(QSYS_SE_CFG_SE_DWRR_CNT_SET(0) |
+               QSYS_SE_CFG_SE_RR_ENA_SET(0),
+               QSYS_SE_CFG_SE_DWRR_CNT |
+               QSYS_SE_CFG_SE_RR_ENA,
+               lan966x, QSYS_SE_CFG(se_idx));
+
+       return 0;
+}
index 168456f..78665eb 100644 (file)
@@ -476,6 +476,11 @@ int lan966x_cbs_add(struct lan966x_port *port,
 int lan966x_cbs_del(struct lan966x_port *port,
                    struct tc_cbs_qopt_offload *qopt);
 
+int lan966x_ets_add(struct lan966x_port *port,
+                   struct tc_ets_qopt_offload *qopt);
+int lan966x_ets_del(struct lan966x_port *port,
+                   struct tc_ets_qopt_offload *qopt);
+
 static inline void __iomem *lan_addr(void __iomem *base[],
                                     int id, int tinst, int tcnt,
                                     int gbase, int ginst,
index 01fa6bb..4f00f95 100644 (file)
@@ -1036,6 +1036,18 @@ enum lan966x_target {
 /*      QSYS:HSCH:SE_CFG */
 #define QSYS_SE_CFG(g)            __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4)
 
+#define QSYS_SE_CFG_SE_DWRR_CNT                  GENMASK(9, 6)
+#define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\
+       FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x)
+#define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\
+       FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x)
+
+#define QSYS_SE_CFG_SE_RR_ENA                    BIT(5)
+#define QSYS_SE_CFG_SE_RR_ENA_SET(x)\
+       FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x)
+#define QSYS_SE_CFG_SE_RR_ENA_GET(x)\
+       FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x)
+
 #define QSYS_SE_CFG_SE_AVB_ENA                   BIT(4)
 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\
        FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x)
@@ -1048,6 +1060,14 @@ enum lan966x_target {
 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\
        FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x)
 
+#define QSYS_SE_DWRR_CFG(g, r)    __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4)
+
+#define QSYS_SE_DWRR_CFG_DWRR_COST               GENMASK(4, 0)
+#define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\
+       FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x)
+#define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\
+       FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x)
+
 /*      QSYS:TAS_CONFIG:TAS_CFG_CTRL */
 #define QSYS_TAS_CFG_CTRL         __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4)
 
index 4b05535..336eb7e 100644 (file)
@@ -44,6 +44,21 @@ static int lan966x_tc_setup_qdisc_cbs(struct lan966x_port *port,
                              lan966x_cbs_del(port, qopt);
 }
 
+static int lan966x_tc_setup_qdisc_ets(struct lan966x_port *port,
+                                     struct tc_ets_qopt_offload *qopt)
+{
+       switch (qopt->command) {
+       case TC_ETS_REPLACE:
+               return lan966x_ets_add(port, qopt);
+       case TC_ETS_DESTROY:
+               return lan966x_ets_del(port, qopt);
+       default:
+               return -EOPNOTSUPP;
+       };
+
+       return -EOPNOTSUPP;
+}
+
 int lan966x_tc_setup(struct net_device *dev, enum tc_setup_type type,
                     void *type_data)
 {
@@ -58,6 +73,8 @@ int lan966x_tc_setup(struct net_device *dev, enum tc_setup_type type,
                return lan966x_tc_setup_qdisc_tbf(port, type_data);
        case TC_SETUP_QDISC_CBS:
                return lan966x_tc_setup_qdisc_cbs(port, type_data);
+       case TC_SETUP_QDISC_ETS:
+               return lan966x_tc_setup_qdisc_ets(port, type_data);
        default:
                return -EOPNOTSUPP;
        }