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[mips] Add virtualization ASE to P5600 scheduling definitions
author
Simon Atanasyan
<simon@atanasyan.com>
Mon, 1 Jul 2019 21:24:58 +0000
(21:24 +0000)
committer
Simon Atanasyan
<simon@atanasyan.com>
Mon, 1 Jul 2019 21:24:58 +0000
(21:24 +0000)
llvm-svn: 364849
llvm/lib/Target/Mips/MipsScheduleP5600.td
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diff --git
a/llvm/lib/Target/Mips/MipsScheduleP5600.td
b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index
239d18c
..
19d2631
100644
(file)
--- a/
llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/
llvm/lib/Target/Mips/MipsScheduleP5600.td
@@
-90,6
+90,11
@@
def : InstRW<[P5600COP2], (instrs MFC2, MTC2)> {
let Unsupported = 1;
}
+// MIPS Virtualization ASE
+// =======================
+def : InstRW<[P5600COP0], (instrs HYPCALL, MFGC0, MFHGC0, MTGC0, MTHGC0,
+ TLBGINV, TLBGINVF, TLBGP, TLBGR, TLBGWI, TLBGWR)>;
+
// LDST Pipeline
// -------------