+2013-01-29 Greta Yorsh <Greta.Yorsh@arm.com>
+
+ * config/arm/arm.md (type): Add ffmas and ffmad to "type" attribute.
+ * config/arm/vfp.md (fma,fmsub,fnmsub,fnmadd): Change type
+ from fmac to ffma.
+ * config/arm/vfp11.md (vfp_farith): Use ffmas.
+ (vfp_fmul): Use ffmad.
+ * config/arm/cortex-r4f.md (cortex_r4_fmacs): Use ffmas.
+ (cortex_r4_fmacd): Use ffmad.
+ * config/arm/cortex-m4-fpu.md (cortex_m4_fmacs): Use ffmas.
+ * config/arm/cortex-a9.md (cortex_a9_fmacs): Use ffmas.
+ (cortex_a9_fmacd): Use ffmad.
+ * config/arm/cortex-a8-neon.md (cortex_a8_vfp_macs): Use ffmas.
+ (cortex_a8_vfp_macd): Use ffmad.
+ * config/arm/cortex-a5.md (cortex_a5_fpmacs): Use ffmas.
+ (cortex_a5_fpmacd): Use ffmad.
+ * config/arm/cortex-a15-neon.md (cortex_a15_vfp_macs) Use ffmas.
+ (cortex_a15_vfp_macd): Use ffmad.
+ * config/arm/arm1020e.md (v10_fmul): Use ffmas and ffmad.
+
2013-01-29 Jason Merrill <jason@redhat.com>
PR libstdc++/54314
fmuld,\
fmacs,\
fmacd,\
+ ffmas,\
+ ffmad,\
f_rints,\
f_rintd,\
f_minmaxs,\
(define_insn_reservation "v10_fmul" 6
(and (eq_attr "vfp10" "yes")
- (eq_attr "type" "fmuls,fmacs,fmuld,fmacd"))
+ (eq_attr "type" "fmuls,fmacs,ffmas,fmuld,fmacd,ffmad"))
"1020a_e+v10_fmac*2")
(define_insn_reservation "v10_fdivs" 18
(define_insn_reservation "cortex_a15_vfp_macs" 6
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "fmacs"))
+ (eq_attr "type" "fmacs,ffmas"))
"ca15_issue1,ca15_cx_vfp")
(define_insn_reservation "cortex_a15_vfp_macd" 11
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "fmacd"))
+ (eq_attr "type" "fmacd,ffmad"))
"ca15_issue2,ca15_cx_vfp*2")
(define_insn_reservation "cortex_a15_vfp_cvt" 6
(define_insn_reservation "cortex_a5_fpmacs" 8
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "fmacs"))
+ (eq_attr "type" "fmacs,ffmas"))
"cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
;; Non-multiply instructions can issue in the middle two instructions of a
(define_insn_reservation "cortex_a5_fpmacd" 11
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "fmacd"))
+ (eq_attr "type" "fmacd,ffmad"))
"cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
(define_insn_reservation "cortex_a8_vfp_macs" 21
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "fmacs"))
+ (eq_attr "type" "fmacs,ffmas"))
"cortex_a8_vfp,cortex_a8_vfplite*20")
(define_insn_reservation "cortex_a8_vfp_macd" 26
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "fmacd"))
+ (eq_attr "type" "fmacd,ffmad"))
"cortex_a8_vfp,cortex_a8_vfplite*25")
(define_insn_reservation "cortex_a8_vfp_divs" 37
;; Pipeline Instruction Classification.
;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r
;; FP_ADD - fadds, faddd, fcmps (1)
-;; FPMUL - fmul{s,d}, fmac{s,d}
+;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d}
;; FPDIV - fdiv{s,d}
(define_cpu_unit "ca9fps" "cortex_a9")
(define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9")
(define_insn_reservation "cortex_a9_fmacs" 8
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fmacs"))
+ (eq_attr "type" "fmacs,ffmas"))
"ca9fmuls, ca9fp_add")
(define_insn_reservation "cortex_a9_fmacd" 9
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fmacd"))
+ (eq_attr "type" "fmacd,ffmad"))
"ca9fmuld, ca9fp_add")
;; Division pipeline description.
(define_insn_reservation "cortex_m4_fmacs" 4
(and (eq_attr "tune" "cortexm4")
- (eq_attr "type" "fmacs"))
+ (eq_attr "type" "fmacs,ffmas"))
"cortex_m4_ex_v*3")
(define_insn_reservation "cortex_m4_ffariths" 1
(define_insn_reservation "cortex_r4_fmacs" 6
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "fmacs"))
+ (eq_attr "type" "fmacs,ffmas"))
"(cortex_r4_issue_a+cortex_r4_v1)|(cortex_r4_issue_b+cortex_r4_vmla)")
(define_insn_reservation "cortex_r4_fdivs" 17
(define_insn_reservation "cortex_r4_fmacd" 20
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "fmacd"))
+ (eq_attr "type" "fmacd,ffmad"))
"cortex_r4_single_issue*13")
(define_insn_reservation "cortex_r4_farith" 10
;; fmuld Double precision multiply.
;; fmacs Single precision multiply-accumulate.
;; fmacd Double precision multiply-accumulate.
+;; ffmas Single precision fused multiply-accumulate.
+;; ffmad Double precision fused multiply-accumulate.
;; fdivs Single precision sqrt or division.
;; fdivd Double precision sqrt or division.
;; f_flag fmstat operation
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmac<vfp_type>")]
+ (set_attr "type" "ffma<vfp_type>")]
)
(define_insn "*fmsub<SDF:mode>4"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmac<vfp_type>")]
+ (set_attr "type" "ffma<vfp_type>")]
)
(define_insn "*fnmsub<SDF:mode>4"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmac<vfp_type>")]
+ (set_attr "type" "ffma<vfp_type>")]
)
(define_insn "*fnmadd<SDF:mode>4"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmac<vfp_type>")]
+ (set_attr "type" "ffma<vfp_type>")]
)
(define_insn_reservation "vfp_farith" 8
(and (eq_attr "generic_vfp" "yes")
- (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs"))
+ (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs,ffmas"))
"fmac")
(define_insn_reservation "vfp_fmul" 9
(and (eq_attr "generic_vfp" "yes")
- (eq_attr "type" "fmuld,fmacd"))
+ (eq_attr "type" "fmuld,fmacd,ffmad"))
"fmac*2")
(define_insn_reservation "vfp_fdivs" 19