drm/amd/display: Limit max DSC target bpp for specific monitors
authorRoman Li <Roman.Li@amd.com>
Fri, 30 Jul 2021 22:30:41 +0000 (18:30 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 25 Nov 2021 08:49:04 +0000 (09:49 +0100)
commit 55eea8ef98641f6e1e1c202bd3a49a57c1dd4059 upstream.

[Why]
Some monitors exhibit corruption at 16bpp DSC.

[How]
- Add helpers for patching edid caps.
- Use it for limiting DSC target bitrate to 15bpp for known monitors

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Cc: stable@vger.kernel.org
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

index 6fee12c..d793eec 100644 (file)
 
 #include "dm_helpers.h"
 
+struct monitor_patch_info {
+       unsigned int manufacturer_id;
+       unsigned int product_id;
+       void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param);
+       unsigned int patch_param;
+};
+static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param);
+
+static const struct monitor_patch_info monitor_patch_table[] = {
+{0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15},
+{0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15},
+};
+
+static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param)
+{
+       if (edid_caps)
+               edid_caps->panel_patch.max_dsc_target_bpp_limit = param;
+}
+
+static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps)
+{
+       int i, ret = 0;
+
+       for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++)
+               if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id)
+                       &&  (edid_caps->product_id == monitor_patch_table[i].product_id)) {
+                       monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param);
+                       ret++;
+               }
+
+       return ret;
+}
+
 /* dm_helpers_parse_edid_caps
  *
  * Parse edid caps
@@ -125,6 +158,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
        kfree(sads);
        kfree(sadb);
 
+       amdgpu_dm_patch_edid_caps(edid_caps);
+
        return result;
 }