{
bool ret = false;
- if (is_meson_tl1_cpu()) {
- if ((RDMA_RD(VPU_ARB_DBG_STAT_L1C1_TL1) &
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
+ if ((RDMA_RD(DI_ARB_DBG_STAT_L1C1) &
PRE_ID_MASK_TL1) == PRE_ID_MASK_TL1)
ret = true;
} else {
- if ((RDMA_RD(VPU_ARB_DBG_STAT_L1C1) &
+ if ((RDMA_RD(DI_ARB_DBG_STAT_L1C1_OLD) &
PRE_ID_MASK) == PRE_ID_MASK)
ret = true;
}
u32 WRARB_onval;
u32 WRARB_offval;
- if (is_meson_tl1_cpu()) {
- REG_VPU_WRARB_REQEN_SLV_L1C1 = VPU_WRARB_REQEN_SLV_L1C1_TL1;
- REG_VPU_RDARB_REQEN_SLV_L1C1 = VPU_RDARB_REQEN_SLV_L1C1_TL1;
- REG_VPU_ARB_DBG_STAT_L1C1 = VPU_ARB_DBG_STAT_L1C1_TL1;
+ if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) {
+ REG_VPU_WRARB_REQEN_SLV_L1C1 = DI_WRARB_REQEN_SLV_L1C1;
+ REG_VPU_RDARB_REQEN_SLV_L1C1 = DI_RDARB_REQEN_SLV_L1C1;
+ REG_VPU_ARB_DBG_STAT_L1C1 = DI_ARB_DBG_STAT_L1C1;
if (on)
WRARB_onval = 0x3f;
else
WRARB_offval = 0x3e;
} else {
- REG_VPU_WRARB_REQEN_SLV_L1C1 = VPU_WRARB_REQEN_SLV_L1C1;
- REG_VPU_RDARB_REQEN_SLV_L1C1 = VPU_RDARB_REQEN_SLV_L1C1;
- REG_VPU_ARB_DBG_STAT_L1C1 = VPU_ARB_DBG_STAT_L1C1;
+ REG_VPU_WRARB_REQEN_SLV_L1C1 = DI_WRARB_REQEN_SLV_L1C1_OLD;
+ REG_VPU_RDARB_REQEN_SLV_L1C1 = DI_RDARB_REQEN_SLV_L1C1_OLD;
+ REG_VPU_ARB_DBG_STAT_L1C1 = DI_ARB_DBG_STAT_L1C1_OLD;
if (on)
WRARB_onval = 0x3f;
else
#define HHI_VPU_CLKB_CNTL 0x83
-#define VPU_WRARB_REQEN_SLV_L1C1 0x2795
-#define VPU_RDARB_REQEN_SLV_L1C1 0x2791
-#define VPU_ARB_DBG_STAT_L1C1 0x27b4
-
-#define VPU_WRARB_REQEN_SLV_L1C1_TL1 0x2055
-#define VPU_RDARB_REQEN_SLV_L1C1_TL1 0x2051
-#define VPU_ARB_DBG_STAT_L1C1_TL1 0x205a
-
+#define DI_WRARB_REQEN_SLV_L1C1_OLD 0x2795
+#define DI_RDARB_REQEN_SLV_L1C1_OLD 0x2791
+#define DI_ARB_DBG_STAT_L1C1_OLD 0x27b4
#define VIUB_SW_RESET 0x2001
#define VIUB_SW_RESET0 0x2002