+2003-04-18 Gerald Pfeifer <pfeifer@dbai.tuwien.ac.at>
+
+ * Makefile.tpl (MAKEINFOFLAGS): Default to --split-size=5000000.
+ * Makefile.in: Regenerate.
+
+2003-04-18 Jakub Jelinek <jakub@redhat.com>
+
+ * configure.in (powerpc64*-*-linux*): Remove.
+ * configure: Rebuilt.
+
+2003-04-17 Phil Edwards <pme@gcc.gnu.org>
+
+ * Makefile.tpl (GCC_STRAP_TARGETS): New variable containing all the
+ previous bootstrap targets, plus bubblestrap, quickstrap, cleanstrap,
+ and restrap.
+ * Makefile.in: Regenerate.
+
+2003-04-16 Richard Earnshaw <rearnsha@arm.com>
+
+ * configure.in (arm-*-netbsdelf*): Enable building java libraries.
+ * configure: Regenerated.
+
+2003-04-11 Alexandre Oliva <aoliva@redhat.com>
+
+ * libtool.m4 (lt_cv_deplibs_check_method): Use pass_all on mips*.
+ * */configure: Rebuilt.
+
2003-03-14 Nathanael Nerode <neroden@gcc.gnu.org>
* Makefile.tpl: Move .NOEXPORT, MAKEOVERRIDES back down.
# This just becomes part of the MAKEINFO definition passed down to
# sub-makes. It lets flags be given on the command line while still
# using the makeinfo from the object tree.
-MAKEINFOFLAGS =
+# (Default to avoid splitting info files by setting the threshold high.)
+MAKEINFOFLAGS = --split-size=5000000
EXPECT = `if [ -f $$r/expect/expect ] ; \
then echo $$r/expect/expect ; \
# In theory, on an SMP all those dependencies can be resolved
# in parallel.
#
-.PHONY: bootstrap bootstrap-lean bootstrap2 bootstrap2-lean bootstrap3 bootstrap3-lean bootstrap4 bootstrap4-lean bubblestrap quickstrap cleanstrap restrap
-bootstrap bootstrap-lean bootstrap2 bootstrap2-lean bootstrap3 bootstrap3-lean bootstrap4 bootstrap4-lean bubblestrap quickstrap cleanstrap restrap: all-bootstrap configure-gcc
+GCC_STRAP_TARGETS = bootstrap bootstrap-lean bootstrap2 bootstrap2-lean bootstrap3 bootstrap3-lean bootstrap4 bootstrap4-lean bubblestrap quickstrap cleanstrap restrap
+.PHONY: $(GCC_STRAP_TARGETS)
+$(GCC_STRAP_TARGETS): all-bootstrap configure-gcc
@r=`${PWD}`; export r; \
s=`cd $(srcdir); ${PWD}`; export s; \
$(SET_LIB_PATH) \
# This just becomes part of the MAKEINFO definition passed down to
# sub-makes. It lets flags be given on the command line while still
# using the makeinfo from the object tree.
-MAKEINFOFLAGS =
+# (Default to avoid splitting info files by setting the threshold high.)
+MAKEINFOFLAGS = --split-size=5000000
EXPECT = `if [ -f $$r/expect/expect ] ; \
then echo $$r/expect/expect ; \
# In theory, on an SMP all those dependencies can be resolved
# in parallel.
#
-.PHONY: bootstrap bootstrap-lean bootstrap2 bootstrap2-lean bootstrap3 bootstrap3-lean bootstrap4 bootstrap4-lean bubblestrap quickstrap cleanstrap restrap
-bootstrap bootstrap-lean bootstrap2 bootstrap2-lean bootstrap3 bootstrap3-lean bootstrap4 bootstrap4-lean bubblestrap quickstrap cleanstrap restrap: all-bootstrap configure-gcc
+GCC_STRAP_TARGETS = bootstrap bootstrap-lean bootstrap2 bootstrap2-lean bootstrap3 bootstrap3-lean bootstrap4 bootstrap4-lean bubblestrap quickstrap cleanstrap restrap
+.PHONY: $(GCC_STRAP_TARGETS)
+$(GCC_STRAP_TARGETS): all-bootstrap configure-gcc
@r=`${PWD}`; export r; \
s=`cd $(srcdir); ${PWD}`; export s; \
$(SET_LIB_PATH) \
+2003-04-18 Nick Clifton <nickc@redhat.com>
+
+ * format.c (bfd_check_format_matches): Only check associated
+ vector if the matching_vector has been created.
+
+2003-04-15 Alexandre Oliva <aoliva@redhat.com>
+
+ * dwarf2.c (_bfd_dwarf2_find_nearest_line): Fix typo in
+ 2003-04-09's change.
+
+2003-04-15 Brian Ford <ford@vss.fsi.com>
+
+ * peicode.h (coff_swap_scnhdr_in): If a section holds
+ uninitialized data and is from an object file or from an
+ executable image that has not initialized the s_size field, or if
+ the physical size is padded, use the virtual size (stored in
+ s_paddr) instead.
+
+2003-04-15 H.J. Lu <hjl@gnu.org>
+
+ * elflink.h (elf_link_add_object_symbols): Properly report
+ filename for alignment reduction.
+
+2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+ * archures.c: Replace occurrances of 'Hitachi' with 'Renesas'.
+ * reloc.c: Likewise.
+ * coff-h8300.c: Likewise.
+ * coff-h8500.c: Likewise.
+ * coff-sh.c: Likewise.
+ * cpu-h8300.c: Likewise.
+ * cpu-sh.c: Likewise.
+ * elf32-h8300.c: Likewise.
+ * elf32-sh.c: Likewise.
+ * elf32-sh64-com.c: Likewise.
+ * elf32-sh64.c: Likewise.
+ * elf64-sh64.c: Likewise.
+ * bfd-in2.h: Regenerate.
+
+2003-04-14 H.J. Lu <hjl@gnu.org>
+
+ * elflink.h (elf_link_add_object_symbols): Maintain maximum
+ alignment for common symbols. Warn reducing alignment for
+ common symbols. Report old filename when symbol size changes.
+
+2003-04-12 Alexandre Oliva <aoliva@redhat.com>
+
+ * elfxx-mips.c (mips_elf_calculate_relocation): Adjust two other
+ occurrences of the same test changed in the previous patch.
+ Optimize.
+
+2003-04-11 Alexandre Oliva <aoliva@redhat.com>
+
+ * elfxx-mips.c (mips_elf_get_global_gotsym_index): New.
+ (mips_elf_calculate_relocation): Decay GOT_PAGE/GOT_OFST to
+ GOT_DISP/addend only if the symbol got a global GOT entry.
+
+2003-04-10 Alexandre Oliva <aoliva@redhat.com>
+
+ * elfxx-mips.c (mips_elf_calculate_relocation): Decay
+ GOT_PAGE/GOT_OFST referencing overridable symbol to
+ GOT_DISP/addend.
+ (_bfd_mips_elf_check_relocs): Handle GOT_PAGE referencing
+ global symbol as GOT_DISP.
+
+2003-04-10 Bob Wilson <bob.wilson@acm.org>
+
+ * elf32-xtensa.c (elf_xtensa_relocate_section): Don't continue to the
+ next relocation on an undefined symbol.
+
+2003-04-09 Richard Henderson <rth@redhat.com>
+
+ * elf64-alpha.c (elf64_alpha_relocate_section) <R_ALPHA_GPREL32>:
+ Ignore relocations against r_symndx == 0.
+
+2003-04-09 H.J. Lu <hjl@gnu.org>
+
+ * elf64-alpha.c (elf64_alpha_relocate_section): Don't return
+ FALSE for undefined symbols.
+ * elfxx-ia64.c (elfNN_ia64_relocate_section): Likewise.
+
+2003-04-09 Alexandre Oliva <aoliva@redhat.com>
+
+ * dwarf2.c (_bfd_dwarf2_find_nearest_line): Try DWARF3-standard
+ and IRIX-specific shift-to-64-bit 4-byte lengths before following
+ addr_size.
+
+2003-04-08 Alexandre Oliva <aoliva@redhat.com>
+
+ * elf32-mips.c (bfd_elf32_bfd_reloc_type_lookup): Detect (ctor)
+ pointer size from ABI, not arch_bits_per_address.
+
+2003-04-07 Kevin Buettner <kevinb@redhat.com>
+
+ * elfn32-mips.c (elf32_mips_grok_prstatus): Adjust core file related
+ constants for n32 ABI.
+
2003-04-06 Andrew Cagney <cagney@redhat.com>
* simple.c (bfd_simple_get_relocated_section_contents): Disable
. bfd_arch_m88k, {* Motorola 88xxx *}
. bfd_arch_m98k, {* Motorola 98xxx *}
. bfd_arch_pyramid, {* Pyramid Technology *}
-. bfd_arch_h8300, {* Hitachi H8/300 *}
+. bfd_arch_h8300, {* Renesas H8/300 (formerly Hitachi H8/300) *}
.#define bfd_mach_h8300 1
.#define bfd_mach_h8300h 2
.#define bfd_mach_h8300s 3
. bfd_arch_z8k, {* Zilog Z8000 *}
.#define bfd_mach_z8001 1
.#define bfd_mach_z8002 2
-. bfd_arch_h8500, {* Hitachi H8/500 *}
-. bfd_arch_sh, {* Hitachi SH *}
+. bfd_arch_h8500, {* Renesas H8/500 (formerly Hitachi H8/500) *}
+. bfd_arch_sh, {* Renesas SH (formerly Hitachi SH) *}
.#define bfd_mach_sh 1
.#define bfd_mach_sh2 0x20
.#define bfd_mach_sh_dsp 0x2d
bfd_arch_m88k, /* Motorola 88xxx */
bfd_arch_m98k, /* Motorola 98xxx */
bfd_arch_pyramid, /* Pyramid Technology */
- bfd_arch_h8300, /* Hitachi H8/300 */
+ bfd_arch_h8300, /* Renesas H8/300 (formerly Hitachi H8/300) */
#define bfd_mach_h8300 1
#define bfd_mach_h8300h 2
#define bfd_mach_h8300s 3
bfd_arch_z8k, /* Zilog Z8000 */
#define bfd_mach_z8001 1
#define bfd_mach_z8002 2
- bfd_arch_h8500, /* Hitachi H8/500 */
- bfd_arch_sh, /* Hitachi SH */
+ bfd_arch_h8500, /* Renesas H8/500 (formerly Hitachi H8/500) */
+ bfd_arch_sh, /* Renesas SH (formerly Hitachi SH) */
#define bfd_mach_sh 1
#define bfd_mach_sh2 0x20
#define bfd_mach_sh_dsp 0x2d
BFD_RELOC_ARM_GOTOFF,
BFD_RELOC_ARM_GOTPC,
-/* Hitachi SH relocs. Not all of these appear in object files. */
+/* Renesas SH relocs. Not all of these appear in object files. */
BFD_RELOC_SH_PCDISP8BY2,
BFD_RELOC_SH_PCDISP12BY2,
BFD_RELOC_SH_IMM4,
-/* BFD back-end for Hitachi H8/300 COFF binaries.
+/* BFD back-end for Renesas H8/300 COFF binaries.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003
Free Software Foundation, Inc.
-/* BFD back-end for Hitachi H8/500 COFF binaries.
- Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2002
+/* BFD back-end for Renesas H8/500 COFF binaries.
+ Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Cygnus Support.
Written by Steve Chamberlain, <sac@cygnus.com>.
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
-/* BFD back-end for Hitachi Super-H COFF binaries.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+/* BFD back-end for Renesas Super-H COFF binaries.
+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Cygnus Support.
Written by Steve Chamberlain, <sac@cygnus.com>.
Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
-/* BFD library support routines for the Hitachi H8/300 architecture.
- Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 2000, 2001, 2002
+/* BFD library support routines for the Renesas H8/300 architecture.
+ Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
-/* BFD library support routines for the Hitachi-SH architecture.
+/* BFD library support routines for the Renesas SH architecture.
Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
bfd_boolean found;
unsigned int offset_size = addr_size;
- if (addr_size == 4)
+ length = read_4_bytes (abfd, stash->info_ptr);
+ /* A 0xffffff length is the DWARF3 way of indicating we use
+ 64-bit offsets, instead of 32-bit offsets. */
+ if (length == 0xffffffff)
{
- length = read_4_bytes (abfd, stash->info_ptr);
- if (length == 0xffffffff)
- {
- offset_size = 8;
- length = read_8_bytes (abfd, stash->info_ptr + 4);
- stash->info_ptr += 8;
- }
- else if (length == 0)
- {
- /* Handle (non-standard) 64-bit DWARF2 formats. */
- offset_size = 8;
- length = read_4_bytes (abfd, stash->info_ptr + 4);
- stash->info_ptr += 4;
- }
+ offset_size = 8;
+ length = read_8_bytes (abfd, stash->info_ptr + 4);
+ stash->info_ptr += 12;
+ }
+ /* A zero length is the IRIX way of indicating 64-bit offsets,
+ mostly because the 64-bit length will generally fit in 32
+ bits, and the endianness helps. */
+ else if (length == 0)
+ {
+ offset_size = 8;
+ length = read_4_bytes (abfd, stash->info_ptr + 4);
+ stash->info_ptr += 8;
+ }
+ /* In the absence of the hints above, we assume addr_size-sized
+ offsets, for backward-compatibility with pre-DWARF3 64-bit
+ platforms. */
+ else if (addr_size == 8)
+ {
+ length = read_8_bytes (abfd, stash->info_ptr);
+ stash->info_ptr += 8;
}
else
- length = read_8_bytes (abfd, stash->info_ptr);
- stash->info_ptr += addr_size;
+ stash->info_ptr += 4;
if (length > 0)
{
-/* Generic support for 32-bit ELF
- Copyright 1993, 1995, 1998, 1999, 2001, 2002
+/* BFD back-end for Renesas H8/300 ELF binaries.
+ Copyright 1993, 1995, 1998, 1999, 2001, 2002, 2003
Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
case BFD_RELOC_CTOR:
/* We need to handle BFD_RELOC_CTOR specially.
Select the right relocation (R_MIPS_32 or R_MIPS_64) based on the
- size of addresses on this architecture. */
- if (bfd_arch_bits_per_address (abfd) == 32)
- return &howto_table[(int) R_MIPS_32];
- else
+ size of addresses of the ABI. */
+ if ((elf_elfheader (abfd)->e_flags & (E_MIPS_ABI_O64
+ | E_MIPS_ABI_EABI64)) != 0)
return &elf_mips_ctor64_howto;
+ else
+ return &howto_table[(int) R_MIPS_32];
case BFD_RELOC_MIPS16_JMP:
return &elf_mips16_jump_howto;
-/* Hitachi SH specific support for 32-bit ELF
+/* Renesas SH specific support for 32-bit ELF
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Ian Lance Taylor, Cygnus Support.
-/* Hitachi SH64-specific support for 32-bit ELF
+/* Renesas SH64-specific support for 32-bit ELF
Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
-/* Hitachi SH64-specific support for 32-bit ELF
+/* Renesas SH64-specific support for 32-bit ELF
Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
bfd_reloc_status_type r;
bfd_boolean is_weak_undef;
bfd_boolean unresolved_reloc;
+ bfd_boolean warned;
r_type = ELF32_R_TYPE (rel->r_info);
if (r_type == (int) R_XTENSA_GNU_VTINHERIT
sec = NULL;
is_weak_undef = FALSE;
unresolved_reloc = FALSE;
+ warned = FALSE;
if (howto->partial_inplace)
{
(!info->shared || info->no_undefined
|| ELF_ST_VISIBILITY (h->other)))))
return FALSE;
-
- /* To avoid any more warning messages, like "call out of
- range", we continue immediately to the next relocation. */
- continue;
+ warned = TRUE;
}
}
contents, rel->r_offset, is_weak_undef,
&error_message);
- if (r != bfd_reloc_ok)
+ if (r != bfd_reloc_ok && !warned)
{
const char *name;
(!info->shared || info->no_undefined
|| ELF_ST_VISIBILITY (h->root.other)))))
return FALSE;
- ret_val = FALSE;
continue;
}
value -= gp;
goto default_reloc;
- case R_ALPHA_GPREL16:
case R_ALPHA_GPREL32:
+ /* If the target section was a removed linkonce section,
+ r_symndx will be zero. In this case, assume that the
+ switch will not be used, so don't fill it in. If we
+ do nothing here, we'll get relocation truncated messages,
+ due to the placement of the application above 4GB. */
+ if (r_symndx == 0)
+ {
+ r = bfd_reloc_ok;
+ break;
+ }
+ /* FALLTHRU */
+
+ case R_ALPHA_GPREL16:
case R_ALPHA_GPRELLOW:
if (dynamic_symbol_p)
{
-/* Hitachi SH64-specific support for 64-bit ELF
- Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
+/* Renesas SH64-specific support for 64-bit ELF
+ Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
const char *name;
struct elf_link_hash_entry *h;
bfd_boolean definition;
- bfd_boolean size_change_ok, type_change_ok;
+ bfd_boolean size_change_ok;
+ bfd_boolean type_change_ok;
bfd_boolean new_weakdef;
- unsigned int old_alignment;
bfd_boolean override;
+ unsigned int old_alignment;
+ bfd *old_bfd;
override = FALSE;
size_change_ok = FALSE;
type_change_ok = get_elf_backend_data (abfd)->type_change_ok;
old_alignment = 0;
+ old_bfd = NULL;
+
if (info->hash->creator->flavour == bfd_target_elf_flavour)
{
Elf_Internal_Versym iver;
that we don't reduce the alignment later on. We can't
check later, because _bfd_generic_link_add_one_symbol
will set a default for the alignment which we want to
- override. */
- if (h->root.type == bfd_link_hash_common)
- old_alignment = h->root.u.c.p->alignment_power;
+ override. We also remember the old bfd where the existing
+ definition comes from. */
+ switch (h->root.type)
+ {
+ default:
+ break;
+
+ case bfd_link_hash_defined:
+ case bfd_link_hash_defweak:
+ old_bfd = h->root.u.def.section->owner;
+ break;
+
+ case bfd_link_hash_common:
+ old_bfd = h->root.u.c.p->section->owner;
+ old_alignment = h->root.u.c.p->alignment_power;
+ break;
+ }
if (elf_tdata (abfd)->verdef != NULL
&& ! override
is specified and no other alignments have been specified. */
|| (isym->st_value == 1 && old_alignment == 0))
h->root.u.c.p->alignment_power = align;
+ else
+ h->root.u.c.p->alignment_power = old_alignment;
}
if (info->hash->creator->flavour == bfd_target_elf_flavour)
bfd_boolean dynsym;
int new_flag;
+ /* Check the alignment when a common symbol is involved. This
+ can change when a common symbol is overriden by a normal
+ definition or a common symbol is ignored due to the old
+ normal definition. We need to make sure the maximum
+ alignment is maintained. */
+ if ((old_alignment || isym->st_shndx == SHN_COMMON)
+ && h->root.type != bfd_link_hash_common)
+ {
+ unsigned int common_align;
+ unsigned int normal_align;
+ unsigned int symbol_align;
+ bfd *normal_bfd;
+ bfd *common_bfd;
+
+ symbol_align = ffs (h->root.u.def.value) - 1;
+ if ((h->root.u.def.section->owner->flags & DYNAMIC) == 0)
+ {
+ normal_align = h->root.u.def.section->alignment_power;
+ if (normal_align > symbol_align)
+ normal_align = symbol_align;
+ }
+ else
+ normal_align = symbol_align;
+
+ if (old_alignment)
+ {
+ common_align = old_alignment;
+ common_bfd = old_bfd;
+ normal_bfd = abfd;
+ }
+ else
+ {
+ common_align = bfd_log2 (isym->st_value);
+ common_bfd = abfd;
+ normal_bfd = old_bfd;
+ }
+
+ if (normal_align < common_align)
+ (*_bfd_error_handler)
+ (_("Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s"),
+ 1 << normal_align,
+ name,
+ bfd_archive_filename (normal_bfd),
+ 1 << common_align,
+ bfd_archive_filename (common_bfd));
+ }
+
/* Remember the symbol size and type. */
if (isym->st_size != 0
&& (definition || h->size == 0))
{
if (h->size != 0 && h->size != isym->st_size && ! size_change_ok)
(*_bfd_error_handler)
- (_("Warning: size of symbol `%s' changed from %lu to %lu in %s"),
+ (_("Warning: size of symbol `%s' changed from %lu in %s to %lu in %s"),
name, (unsigned long) h->size,
- (unsigned long) isym->st_size, bfd_archive_filename (abfd));
+ bfd_archive_filename (old_bfd),
+ (unsigned long) isym->st_size,
+ bfd_archive_filename (abfd));
h->size = isym->st_size;
}
default:
return FALSE;
- case 256: /* Linux/MIPS */
+ case 440: /* Linux/MIPS N32 */
/* pr_cursig */
elf_tdata (abfd)->core_signal = bfd_get_16 (abfd, note->descdata + 12);
/* pr_reg */
offset = 72;
- raw_size = 180;
+ raw_size = 360;
break;
}
(!info->shared || info->no_undefined
|| ELF_ST_VISIBILITY (h->other)))))
return FALSE;
- ret_val = FALSE;
continue;
}
}
static asection * mips_elf_got_section PARAMS ((bfd *, bfd_boolean));
static struct mips_got_info *mips_elf_got_info
PARAMS ((bfd *, asection **));
+static long mips_elf_get_global_gotsym_index PARAMS ((bfd *abfd));
static bfd_vma mips_elf_local_got_index
PARAMS ((bfd *, bfd *, struct bfd_link_info *, bfd_vma));
static bfd_vma mips_elf_global_got_index
return g;
}
+/* Obtain the lowest dynamic index of a symbol that was assigned a
+ global GOT entry. */
+static long
+mips_elf_get_global_gotsym_index (abfd)
+ bfd *abfd;
+{
+ asection *sgot;
+ struct mips_got_info *g;
+
+ if (abfd == NULL)
+ return 0;
+
+ sgot = mips_elf_got_section (abfd, TRUE);
+ if (sgot == NULL || mips_elf_section_data (sgot) == NULL)
+ return 0;
+
+ g = mips_elf_section_data (sgot)->u.got_info;
+ if (g == NULL || g->global_gotsym == NULL)
+ return 0;
+
+ return g->global_gotsym->dynindx;
+}
+
/* Returns the GOT offset at which the indicated address can be found.
If there is not yet a GOT entry for this value, create one. Returns
-1 if no satisfactory GOT offset can be found. */
and we're going to need it, get it now. */
switch (r_type)
{
+ case R_MIPS_GOT_PAGE:
+ case R_MIPS_GOT_OFST:
+ /* If this symbol got a global GOT entry, we have to decay
+ GOT_PAGE/GOT_OFST to GOT_DISP/addend. */
+ local_p = local_p || ! h
+ || (h->root.dynindx
+ < mips_elf_get_global_gotsym_index (elf_hash_table (info)
+ ->dynobj));
+ if (local_p || r_type == R_MIPS_GOT_OFST)
+ break;
+ /* Fall through. */
+
case R_MIPS_CALL16:
case R_MIPS_GOT16:
case R_MIPS_GOT_DISP:
/* Find the index into the GOT where this value is located. */
if (!local_p)
{
- BFD_ASSERT (addend == 0);
+ /* GOT_PAGE may take a non-zero addend, that is ignored in a
+ GOT_PAGE relocation that decays to GOT_DISP because the
+ symbol turns out to be global. The addend is then added
+ as GOT_OFST. */
+ BFD_ASSERT (addend == 0 || r_type == R_MIPS_GOT_PAGE);
g = mips_elf_global_got_index (elf_hash_table (info)->dynobj,
input_bfd,
(struct elf_link_hash_entry *) h);
We must initialize this entry in the GOT. */
bfd *tmpbfd = elf_hash_table (info)->dynobj;
asection *sgot = mips_elf_got_section (tmpbfd, FALSE);
- MIPS_ELF_PUT_WORD (tmpbfd, symbol + addend, sgot->contents + g);
+ MIPS_ELF_PUT_WORD (tmpbfd, symbol, sgot->contents + g);
}
}
else if (r_type == R_MIPS_GOT16 || r_type == R_MIPS_CALL16)
/* Fall through. */
case R_MIPS_GOT_DISP:
+ got_disp:
value = g;
overflowed_p = mips_elf_overflow_p (value, 16);
break;
break;
case R_MIPS_GOT_PAGE:
+ /* GOT_PAGE relocations that reference non-local symbols decay
+ to GOT_DISP. The corresponding GOT_OFST relocation decays to
+ 0. */
+ if (! local_p)
+ goto got_disp;
value = mips_elf_got_page (abfd, input_bfd, info, symbol + addend, NULL);
if (value == MINUS_ONE)
return bfd_reloc_outofrange;
break;
case R_MIPS_GOT_OFST:
- mips_elf_got_page (abfd, input_bfd, info, symbol + addend, &value);
+ if (local_p)
+ mips_elf_got_page (abfd, input_bfd, info, symbol + addend, &value);
+ else
+ value = addend;
overflowed_p = mips_elf_overflow_p (value, 16);
break;
}
break;
+ case R_MIPS_GOT_PAGE:
+ /* If this is a global, overridable symbol, GOT_PAGE will
+ decay to GOT_DISP, so we'll need a GOT entry for it. */
+ if (h == NULL)
+ break;
+ else
+ {
+ struct mips_elf_link_hash_entry *hmips =
+ (struct mips_elf_link_hash_entry *) h;
+
+ while (hmips->root.root.type == bfd_link_hash_indirect
+ || hmips->root.root.type == bfd_link_hash_warning)
+ hmips = (struct mips_elf_link_hash_entry *)
+ hmips->root.root.u.i.link;
+
+ if ((hmips->root.root.type == bfd_link_hash_defined
+ || hmips->root.root.type == bfd_link_hash_defweak)
+ && hmips->root.root.u.def.section
+ && ! (info->shared && ! info->symbolic
+ && ! (hmips->root.elf_link_hash_flags
+ & ELF_LINK_FORCED_LOCAL))
+ /* If we've encountered any other relocation
+ referencing the symbol, we'll have marked it as
+ dynamic, and, even though we might be able to get
+ rid of the GOT entry should we know for sure all
+ previous relocations were GOT_PAGE ones, at this
+ point we can't tell, so just keep using the
+ symbol as dynamic. This is very important in the
+ multi-got case, since we don't decide whether to
+ decay GOT_PAGE to GOT_DISP on a per-GOT basis: if
+ the symbol is dynamic, we'll need a GOT entry for
+ every GOT in which the symbol is referenced with
+ a GOT_PAGE relocation. */
+ && hmips->root.dynindx == -1)
+ break;
+ }
+ /* Fall through. */
+
case R_MIPS_GOT16:
case R_MIPS_GOT_HI16:
case R_MIPS_GOT_LO16:
}
}
- if (match_count > 1 && bfd_associated_vector != NULL)
+ if (match_count > 1
+ && bfd_associated_vector != NULL
+ && matching)
{
const bfd_target * const *assoc = bfd_associated_vector;
}
#ifndef COFF_NO_HACK_SCNHDR_SIZE
- /* If this section holds uninitialized data, use the virtual size
- (stored in s_paddr) instead of the physical size. */
- if ((scnhdr_int->s_flags & IMAGE_SCN_CNT_UNINITIALIZED_DATA) != 0
- && (scnhdr_int->s_paddr > 0))
+ /* If this section holds uninitialized data and is from an object file
+ or from an executable image that has not initialized the field,
+ or if the physical size is padded, use the virtual size (stored in
+ s_paddr) instead. */
+ if (scnhdr_int->s_paddr > 0
+ && (((scnhdr_int->s_flags & IMAGE_SCN_CNT_UNINITIALIZED_DATA) != 0
+ && (! bfd_pe_executable_p (abfd) || scnhdr_int->s_size == 0))
+ || scnhdr_int->s_size > scnhdr_int->s_paddr))
{
- /* Always set it for non pe-obj files, and don't overwrite it
- if it's zero for object files. */
- if (! bfd_pe_executable_p (abfd) || !scnhdr_int->s_size)
- scnhdr_int->s_size = scnhdr_int->s_paddr;
+ scnhdr_int->s_size = scnhdr_int->s_paddr;
/* This code used to set scnhdr_int->s_paddr to 0. However,
coff_set_alignment_hook stores s_paddr in virt_size, which
ENUMX
BFD_RELOC_SH_TLS_TPOFF32
ENUMDOC
- Hitachi SH relocs. Not all of these appear in object files.
+ Renesas SH relocs. Not all of these appear in object files.
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH9
-#define BFD_VERSION_DATE 20030406
+#define BFD_VERSION_DATE 20030419
#define BFD_VERSION @bfd_version@
#define BFD_VERSION_STRING @bfd_version_string@
# Skip some stuff that's unsupported on some NetBSD configurations.
case "${target}" in
i*86-*-netbsdelf*) ;;
+ arm*-*-netbsdelf*) ;;
*)
noconfigdirs="$noconfigdirs ${libgcj}"
;;
powerpc-*-eabi)
noconfigdirs="$noconfigdirs ${libgcj}"
;;
- powerpc64*-*-linux*)
- noconfigdirs="$noconfigdirs target-newlib target-libgloss"
- # not yet ported.
- noconfigdirs="$noconfigdirs target-libffi"
- ;;
rs6000-*-lynxos*)
noconfigdirs="$noconfigdirs target-newlib gprof ${libgcj}"
;;
# Skip some stuff that's unsupported on some NetBSD configurations.
case "${target}" in
i*86-*-netbsdelf*) ;;
+ arm*-*-netbsdelf*) ;;
*)
noconfigdirs="$noconfigdirs ${libgcj}"
;;
powerpc-*-eabi)
noconfigdirs="$noconfigdirs ${libgcj}"
;;
- powerpc64*-*-linux*)
- noconfigdirs="$noconfigdirs target-newlib target-libgloss"
- # not yet ported.
- noconfigdirs="$noconfigdirs target-libffi"
- ;;
rs6000-*-lynxos*)
noconfigdirs="$noconfigdirs target-newlib gprof ${libgcj}"
;;
+2003-04-19 Mark Kettenis <kettenis@gnu.org>
+
+ * i386-tdep.c (i386_num_register_names): New variable.
+ (i386_num_mmx_regs): Renamed from mmx_num_regs.
+ (MM0_REGNUM): Remove redundant parentheses in define.
+ (i386_mmx_regnum_p): Use i386_mmx_regnum instead of mmx_num_regs.
+ (i386_fp_regnum_p, i386_fpc_regnum_p, i386_sse_regnum_p,
+ i386_mxcsr_regnum_p): Remove redundant parentheses.
+ (i386_register_name): Use i386_num_register_names.
+
+ * i386-tdep.c (i386_extract_return_value,
+ i386_store_return_value): Correct check for availability of
+ floating-point registers.
+
+ * i386-tdep.c (i386_frame_num_args): Remove function.
+ (i386_gdbarch_init): Set frame_num_args to frame_num_args_unknown.
+
+ * i386-tdep.c (i386_mmx_regnum_to_fp_regnum): Renamed from
+ mmx_regnum_to_fp_regnum. Adjust all callers.
+
+ * i386-tdep.c (i386_get_longjmp_target): Use
+ TYPE_LENGTH(builtin_type_void_func_ptr) instead of TARGET_PTR_BIT
+ and TARGET_CHAR_BIT. Use extract_typed_address instead of
+ extract_address.
+
+2003-04-19 Mark Kettenis <kettenis@gnu.org>
+
+ * core-regset.c: Update comments to reflect reality. Re-order
+ includes.
+ (fetch_core_registers): Use switch instead of if. Remove
+ redundant prototype.
+
+2003-04-18 Jim Blandy <jimb@redhat.com>
+
+ * s390-tdep.c (s390_frame_align): New function.
+ (s390_gdbarch_init): Register it with the gdbarch object.
+
+2003-04-17 Richard Henderson <rth@redhat.com>
+
+ * remote.c (minitelnet): Don't redeclare escape_count, echo_check.
+
+2003-04-17 Michael Snyder <msnyder@redhat.com>
+ Karen Bennet <bennet@redhat.com>
+
+ Committed by Elena Zannoni <ezannoni@redhat.com>
+ * gdb_gcore.sh: New script to create a core dump of a process.
+
+2003-04-17 Elena Zannoni <ezannoni@redhat.com>
+
+ * values.c (value_being_returned): Don't fetch the return
+ value if the return type is void.
+
+2003-04-17 Jeff Johnston <jjohnstn@redhat.com>
+
+ * thread-db.c: Reindented.
+
+2003-04-17 Jeff Johnston <jjohnstn@redhat.com>
+
+ * gdb_indent.sh: Recognize td_thrhandle_t, td_event_msg_t,
+ td_thr_events_t, td_notify_t, td_thr_iter_f, and td_thrinfo_t
+ as types.
+
+2003-04-16 Kevin Buettner <kevinb@redhat.com>
+
+ * rs6000-tdep.c (rs6000_gdbarch_init): For the SysV ABI, set
+ the size of ``long double'' to 16, instead of 8.
+
+2003-04-16 Mark Kettenis <kettenis@gnu.org>
+
+ * i386-linux-nat.c: Add some whitespace to make things more
+ readable.
+ (fetch_register, store_register, fetch_inferior_registers,
+ store_inferior_registers): Get rid of assignment in if-statement.
+ (store_register): Fix typo in error message.
+
+2003-04-16 Andrew Cagney <cagney@redhat.com>
+
+ * utils.c (xmmalloc): Always allocate something, matches
+ libiberty/xmalloc's semantics.
+ (xmrealloc, xmcalloc): Ditto.
+
+2003-04-16 Andrew Cagney <cagney@redhat.com>
+
+ * frame.c (get_prev_frame): Do not initialize "unwind" or "type",
+ update comments.
+ (get_frame_type): Initialize unwind and type when needed.
+ (get_frame_id, frame_register_unwind): Ditto.
+
+2003-04-16 Andrew Cagney <cagney@redhat.com>
+
+ * NEWS: Mention that sparclet-*-* and sparclite-*-* have been made
+ obsolete.
+ * sparc-tdep.c: Obsolete SPARCLET and SPARCLITE code.
+ * sparcl-stub.c: Obsolete file.
+ * config/sparc/tm-sparclet.h: Obsolete file.
+ * sparclet-stub.c: Obsolete file.
+ * sparclet-rom.c: Obsolete file.
+ * sparcl-tdep.c: Obsolete file.
+ * config/sparc/tm-sparclite.h: Obsolete file.
+ * config/sparc/sparclite.mt: Obsolete file.
+ * config/sparc/sparclet.mt: Obsolete file.
+ * configure.tgt: Make sparclet-*-*, sparclite-*-*, and
+ sparc86x-*-* obsolete.
+
+2003-04-15 David Carlton <carlton@math.stanford.edu>
+
+ * Makefile.in (SFILES): Add cp-namespace.c.
+ (COMMON_OBS): Add cp-namespace.o.
+ (block.o): Depend on gdb_obstack_h and cp_support_h.
+ (buildsym.o): Depend on cp_support_h.
+ (cp-namespace.o): New.
+ (cp-support.o): Depend on gdb_string_h, demangle_h, gdb_assert_h,
+ gdb_obstack_h, symtab_h, symfile_h, and gdbcmd_h.
+ (dwarf2read.o): Depend on cp_support_h.
+ * jv-lang.c (get_java_class_symtab): Set BLOCK_NAMESPACE.
+ * dwarf2read.c (process_die): Set processing_has_namespace_info,
+ processing_current_namespace.
+ (read_namespace): Update processing_current_namespace; check for
+ anonymous namespaces.
+ (dwarf2_name): New function.
+ (dwarf2_extension): Ditto.
+ * cp-support.h: Update copyright, contributors.
+ Add inclusion guards.
+ Add opaque declaration for structs obstack, block, symbol.
+ (struct using_direct): New struct.
+ Add declarations for cp_find_first_component,
+ cp_entire_prefix_len, processing_has_namespace_info,
+ processing_current_namespace, cp_is_anonymous,
+ cp_add_using_directive, cp_initialize_namespace,
+ cp_finalize_namespace, cp_set_block_scope,
+ cp_scan_for_anonymous_namespaces.
+ * cp-namespace.c: New file.
+ * cp-support.c: Update copyright.
+ Include ctype.h, gdb_assert.h, gdbcmd.h.
+ New variable maint_cplus_cmd_list.
+ (cp_find_first_component): New function.
+ (cp_entire_prefix_len, maint_cplus_command)
+ (first_component_command, _initialize_cp_support): Ditto.
+ * buildsym.c: Include cp-support.h.
+ New variable using_list.
+ (add_symbol_to_list): Check for anonymous namespaces.
+ (finish_block): Set block's scope.
+ (start_symtab): Initialize C++ namespace support.
+ (end_symtab): Finalize C++ namespace support.
+ * block.h: Add opaque declarations for structs
+ block_namespace_info, using_direct, and obstack.
+ Add declarations for block_set_scope and block_set_using.
+ (struct block): Add 'language_specific' member.
+ (BLOCK_NAMESPACE): New macro.
+ * block.c: Include gdb_obstack.h and cp-support.h.
+ (struct block_namespace_info): New struct.
+ (block_set_scope): New function.
+ (block_set_using, block_initialize_namespace): Ditto.
+
+2003-04-14 Kevin Buettner <kevinb@redhat.com>
+
+ * solib-svr4.c (svr4_have_link_map_offsets): New function.
+ (locate_base): Return early if there aren't any link map offsets.
+ (svr4_solib_create_inferior_hook): Warn if shared library support
+ is unavailable.
+
+2003-04-14 David Carlton <carlton@math.stanford.edu>
+
+ * symtab.c (symbol_set_names): Add prefix when storing Java names
+ in hash table. Fix for PR java/1039.
+
+2003-04-14 David Carlton <carlton@math.stanford.edu>
+
+ * symtab.c (symbol_set_names): Rename 'name' arg to
+ 'linkage_name', and 'tmpname' variable to 'linkage_name_copy'.
+ * symtab.h: Change 'name' argument in declaration of
+ symbol_set_names to 'linkage_name'.
+ (SYMBOL_SET_NAMES): Change 'name' argument to 'linkage_name'.
+
+2003-04-14 Andrew Cagney <cagney@redhat.com>
+
+ * mips-tdep.c (mips_read_sp): Do not apply ADDR_BITS_REMOVE,
+ return the fully sign-extended register value.
+ (get_frame_pointer): Ditto.
+ (mips_pop_frame): Initialize "proc_desc" after checking for a
+ dummy frame.
+
+2003-04-14 Andrew Cagney <cagney@redhat.com>
+
+ * mips-tdep.c (mips_push_dummy_frame): Delete function.
+ (MASK, PUSH_FP_REGNUM, GEN_REG_SAVE_MASK): Delete macros.
+ (FLOAT_REG_SAVE_MASK, FLOAT_SINGLE_REG_SAVE_MASK): Delete macro.
+ (mips_push_register): Delete function.
+ (mips_dump_tdep): Delete references to GEN_REG_SAVE_MASK and
+ PUSH_FP_REGNUM.
+
+2003-04-14 Jim Blandy <jimb@redhat.com>
+
+ * symmisc.c: #include "gdb_regex.h".
+ (maintenance_list_symtabs, maintenance_list_psymtabs): New
+ functions.
+ * maint.c (maintenance_list_command): New function.
+ (_initialize_maint_cmds): Register the above as commands.
+ * symtab.h (maintenance_list_symtabs,
+ maintenance_list_psymtabs): New declarations.
+ * cli/cli-cmds.c (maintenancelistlist): New variable.
+ (init_cmd_lists): Initialize it.
+ * cli/cli-cmds.h (maintenancelistlist): New declaration.
+ * gdbcmd.h (maintenancelistlist): New declaration.
+ * Makefile.in (symmisc.o): Update dependencies.
+
+2003-04-14 Elena Zannoni <ezannoni@redhat.com>
+
+ * s390-nat.c: Include asm/types.h for addr_t.
+
+2003-04-14 Corinna Vinschen <vinschen@redhat.com>
+
+ * cp-valprint.c (cp_print_class_method): Call unpack_pointer() with
+ actually incoming type.
+
+2003-04-13 Andrew Cagney <cagney@redhat.com>
+
+ * ppc-linux-tdep.c: Use get_frame_base, get_frame_pc,
+ get_next_frame and get_frame_saved_regs.
+
+2003-04-13 Andrew Cagney <cagney@redhat.com>
+
+ * reggroups.c (default_register_reggroup_p): Use NUM_REGS instead
+ of gdbarch_num_regs.
+
+2003-04-13 Andrew Cagney <cagney@redhat.com>
+
+ * frame.h: Mention what replaced what in "struct frame_info".
+ * hppa-hpux-tdep.c: Use get_frame_base, get_frame_pc and
+ deprecated_update_frame_base_hack and
+ deprecated_update_frame_pc_hack.
+ * hppa-tdep.c: Ditto.
+
+2003-04-13 Daniel Jacobowitz <drow@mvista.com>
+
+ * dwarf2expr.h (struct dwarf_expr_context): Remove extra arguments
+ to read_reg and update its comment. Remove regnum member.
+ * dwarf2expr.c (execute_stack_op): Remove memaddr and expr_lval.
+ Don't call read_reg when setting in_reg. Call read_reg to get
+ the frame base if it's in a register. Return the register number
+ on the stack instead of in the context. Remove extra arguments
+ to read_reg.
+ * dwarf2loc.c (dwarf_expr_read_reg): Remove extra arguments.
+ (dwarf2_evaluate_loc_desc): Call value_from_register. Expect
+ the register number on the expression stack.
+ (needs_frame_read_reg): Remove extra arguments.
+
+2003-04-13 Daniel Jacobowitz <drow@mvista.com>
+
+ * dwarf2expr.c (dwarf2_read_address): Renamed from read_address;
+ made non-static.
+ (execute_stack_op): All callers updated.
+ * dwarf2expr.h: Add prototype for dwarf2_read_address.
+ * dwarf2loc.c (find_location_expression): New function.
+ (dwarf_expr_frame_base): Call it.
+ (dwarf2_evaluate_loc_desc): Handle 0-length location expressions.
+ (dwarf2_tracepoint_var_ref): New function, broken out from
+ locexpr_tracepoint_var_ref.
+ (locexpr_tracepoint_var_ref): Call dwarf2_tracepoint_var_ref.
+ Make static.
+ (loclist_read_variable, loclist_read_needs_frame): New functions.
+ (loclist_describe_location, loclist_tracepoint_var_ref): New
+ functions.
+ (dwarf2_loclist_funcs): New struct location_funcs.
+ * dwarf2loc.h (struct dwarf2_loclist_baton): New type.
+ (struct dwarf2_locexpr_baton): Add comments.
+ (dwarf2_loclist_funcs): New extern.
+ * dwarf2read.c (struct comp_unit_head): Remove DIE member, add
+ base_address and base_known.
+ (dwarf_loc_buffer): New variable.
+ (struct dwarf2_pinfo): Add dwarf_loc_buffer and dwarf_loc_size.
+ (DWARF_LOC_BUFFER, DWARF_LOC_SIZE): New macros.
+ (dwarf2_has_info): Initialize dwarf_loc_offset.
+ (dwarf2_build_psymtabs): Read in .debug_loc.
+ (dwarf2_build_psymtabs_hard): Use DWARF_LOC_BUFFER and
+ DWARF_LOC_SIZE.
+ (psymtab_to_symtab_1): Likewise. Move base address calculation
+ here, from...
+ (dwarf2_get_pc_bounds): ... here. Use the base address from
+ cu_header.
+ (dwarf2_symbol_mark_computed): Handle location lists.
+
+2003-04-13 Daniel Jacobowitz <drow@mvista.com>
+
+ * minsyms.c (install_minimal_symbols): Only switch to gnu-v3 mode
+ if the linkage name demangled successfully.
+
+2003-04-13 Mark Kettenis <kettenis@gnu.org>
+
+ * x86-64-tdep.c (att_flavour, intel_flavour, valid_flavours,
+ disassmbly_flavour): Removed.
+
+ * x86-64-tdep.c (gdb_print_insn_x86_64): Removed.
+
+2003-04-13 Mark Kettenis <kettenis@gnu.org>
+
+ * x86-64-tdep.c (x86_64_breakpoint_from_pc): Removed.
+
+2003-04-12 Andrew Cagney <cagney@redhat.com>
+
+ * frame.h (struct frame_info): Move definition from here ...
+ * frame.c (struct frame_info): ... to here.
+
+2003-04-12 Andrew Cagney <cagney@redhat.com>
+
+ * gdbthread.h (save_infrun_state): Delete parameter
+ "prev_func_start".
+ (struct thread_info): Delete field "prev_func_start".
+ (load_infrun_state): Ditto.
+ * thread.c (load_infrun_state, save_infrun_state): Update.
+ * infrun.c (prev_func_start): Delete variable.
+ (context_switch, init_wait_for_inferior): Update.
+ (stop_stepping, keep_going): Update.
+
+2003-04-12 Andrew Cagney <cagney@redhat.com>
+
+ * gdbarch.sh: Add missing opaque declarations.
+ * gdbarch.h: Regnerate.
+ * symtab.h: Add missing opaque declarations.
+ * value.h, target.h, symfile.h, stabsread.h: Ditto.
+ * x86-64-tdep.h, xmodem.h, monitor.h, typeprint.h: Ditto.
+ * srec.h, solib-svr4.h, source.h, inferior.h: Ditto.
+ * ser-unix.h, serial.h, remote-utils.h, gdbcore.h: Ditto.
+ * ppc-tdep.h, ocd.h, mips-tdep.h, gdbtypes.h: Ditto.
+ * buildsym.h, builtin-regs.h, linespec.h, language.h: Ditto.
+ * i387-tdep.h, gdbthread.h, event-top.h, gdb.h: Ditto.
+ * dwarf2cfi.h, doublest.h, disasm.h, cp-abi.h: Ditto.
+ * cli-out.h, c-lang.h, ax-gdb.h, arch-utils.h: Ditto.
+ * ada-lang.h, config/nm-lynx.h, config/nm-linux.h: Ditto.
+ * config/sparc/tm-sp64.h, config/rs6000/tm-rs6000.h: Ditto.
+ * config/pa/tm-hppah.h, config/m68k/tm-delta68.h: Ditto.
+ * cli/cli-setshow.h, cli/cli-script.h: Ditto.
+
+2003-04-11 Andrew Cagney <cagney@redhat.com>
+
+ * frame.c (get_frame_id): Return this frame's "id".
+ (legacy_get_prev_frame): Set prev's frame ID code_addr to the
+ function start.
+ (legacy_saved_regs_this_id): Replace function body with
+ internal-error.
+ (deprecated_frame_xmalloc): Mark the frame ID as valid, use
+ FRAME_OBSTACK_ZALLOC.
+ (create_new_frame): Mark the frame ID as valid.
+
+2003-04-11 Alexandre Oliva <aoliva@redhat.com>
+
+ * Makefile.in (libbfd_h): Added missing setting.
+ * mips-tdep.c (mips_gdbarch_init): Set disassembler_options
+ according to the selected ABI.
+
+2003-04-11 Jeff Johnston <jjohnstn@redhat.com>
+
+ * gdb_indent.sh: Recognize pid_t and sigset_t as types.
+
+2003-04-11 Andrew Cagney <cagney@redhat.com>
+
+ * gdbarch.sh (DEPRECATED_SAVED_PC_AFTER_CALL): Deprecate
+ SAVED_PC_AFTER_CALL.
+ * gdbarch.h, gdbarch.c: Regenerate.
+ * xstormy16-tdep.c (xstormy16_gdbarch_init): Update.
+ * x86-64-tdep.c (x86_64_init_abi): Update.
+ * vax-tdep.c (vax_gdbarch_init): Update.
+ * v850-tdep.c (v850_gdbarch_init): Update.
+ * sparc-tdep.c (sparc_gdbarch_init): Update.
+ * sh-tdep.c (sh_gdbarch_init): Update.
+ * s390-tdep.c (s390_gdbarch_init): Update.
+ * rs6000-tdep.c (rs6000_gdbarch_init): Update.
+ * ns32k-tdep.c (ns32k_gdbarch_init): Update.
+ * mn10300-tdep.c (mn10300_gdbarch_init): Update.
+ * mips-tdep.c (mips_gdbarch_init): Update.
+ * mcore-tdep.c (mcore_gdbarch_init): Update.
+ * m68k-tdep.c (m68k_gdbarch_init): Update.
+ * m68hc11-tdep.c (m68hc11_gdbarch_init): Update.
+ * ia64-tdep.c (ia64_gdbarch_init): Update.
+ (ia64_saved_pc_after_call): Update declaration.
+ * i386ly-tdep.c (i386lynx_init_abi): Update.
+ * i386-tdep.c (i386_gdbarch_init): Update.
+ * hppa-tdep.c (hppa_gdbarch_init): Update.
+ * h8300-tdep.c (h8300_gdbarch_init): Update.
+ * frv-tdep.c (frv_gdbarch_init): Update.
+ * cris-tdep.c (cris_gdbarch_init): Update.
+ * avr-tdep.c (avr_gdbarch_init): Update.
+ * arm-tdep.c (arm_gdbarch_init): Update.
+ * alpha-tdep.c (alpha_gdbarch_init): Update.
+ * ns32knbsd-nat.c (frame_num_args): Update.
+ * ns32k-tdep.c (umax_frame_num_args): Update.
+ * mips-tdep.c (mips_init_frame_pc_first): Update.
+ * infrun.c (step_over_function): Update.
+ * i386-linux-tdep.c (skip_hurd_resolver): Update.
+ * i386-interix-tdep.c (i386_interix_back_one_frame): Update.
+ * config/sparc/tm-sparc.h (DEPRECATED_SAVED_PC_AFTER_CALL): Update.
+ (DEPRECATED_INIT_FRAME_PC_FIRST): Update.
+ * config/rs6000/tm-rs6000.h (DEPRECATED_INIT_FRAME_PC_FIRST): Update.
+ * config/pa/tm-hppa.h (DEPRECATED_SAVED_PC_AFTER_CALL): Update.
+ * arm-linux-tdep.c (skip_hurd_resolver): Update.
+ * arch-utils.c (init_frame_pc_default): Update.
+ * alpha-tdep.c (alpha_init_frame_pc_first): Update.
+ * x86-64-tdep.h (x86_64_linux_saved_pc_after_call): Update
+ declaration.
+
+2003-04-11 Andrew Cagney <cagney@redhat.com>
+
+ * i387-tdep.c: Update copyright.
+ (i387_to_double): Delete function.
+ (double_to_i387): Delete function.
+
+2003-04-10 Andrew Cagney <cagney@redhat.com>
+
+ * d10v-tdep.c (d10v_frame_this_id): Set the code addr to the
+ frame's function's address. Simplify.
+ (d10v_frame_unwind_cache): Check that the frame's function is
+ non-zero.
+
+2003-04-10 Jim Blandy <jimb@redhat.com>
+
+ * s390-tdep.c (s390_gdbarch_init): Put back accidentally deleted
+ call to set_gdbarch_deprecated_push_arguments.
+
+2003-04-10 Andrew Cagney <cagney@redhat.com>
+
+ * frame.c (fprint_frame_id): New function.
+ (fprint_frame_type, fprint_frame): New function.
+ (frame_pc_unwind, frame_func_unwind): Add/update trace code.
+ (create_sentinel_frame, get_frame_id): Ditto.
+ (frame_id_p, frame_id_eq): Ditto.
+ (frame_id_inner, create_new_frame): Ditto.
+ (legacy_get_prev_frame, get_prev_frame): Ditto.
+ (deprecated_update_frame_pc_hack): Ditto.
+ (frame_register_unwind): Ditto.
+ (deprecated_update_frame_base_hack): Ditto.
+
+2003-04-10 Corinna Vinschen <vinschen@redhat.com>
+
+ * i386-cygwin-tdep.c (i386_cygwin_frame_chain): New function.
+ (i386_cygwin_init_abi): Set i386_cygwin_frame_chain as new
+ frame_chain function.
+ * Makefile.in: Add dependencies due to above change.
+
+2003-04-10 Corinna Vinschen <vinschen@redhat.com>
+
+ * blockframe.c (legacy_frame_chain_valid): Move call to
+ DEPRECATED_FRAME_CHAIN_VALID before calls to inside_entry_func and
+ inside_entry_file.
+
+2003-04-09 Andrew Cagney <cagney@redhat.com>
+
+ * frame.h (struct frame_id): Replace "pc" and "base" with
+ "stack_addr" and "code_addr". Update comments.
+ (frame_id_build): Update parameter names and comment.
+ (struct frame_info): Replace "id_p" and "id" with "this_id".
+ * dummy-frame.c (dummy_frame_this_id): Update.
+ * breakpoint.c (print_one_breakpoint): Update.
+ * frame.c (get_frame_id): Update.
+ (get_frame_base, frame_id_build): Update.
+ (create_sentinel_frame, legacy_get_prev_frame): Update.
+ (deprecated_update_frame_base_hack): Update.
+ (frame_id_p, frame_id_eq): Rework, return 0 when an invalid ID.
+ (frame_id_inner): Ditto.
+
+2003-04-09 Andrew Cagney <cagney@redhat.com>
+
+ * defs.h (gdb_print_host_address): Make "addr" parameter a
+ pointer constant.
+ * utils.c (gdb_print_host_address): Update.
+
+2003-04-09 Kevin Buettner <kevinb@redhat.com>
+
+ * rs6000-tdep.c (frame_get_saved_regs): Don't assume that the
+ register number for R0 is 0.
+
+2003-04-09 J. Brobecker <brobecker@gnat.com>
+
+ * frame.h (struct gdbarch): Add opaque structure definition
+ to avoid a compilation warning on LynxOS 4.0.
+
+2003-04-09 Andrew Cagney <cagney@redhat.com>
+
+ * frame.h (struct frame_info): Delete field "pc". Replace
+ "pc_unwind_cache" and "pc_unwind_cache_p" with "prev_pc"
+ structure.
+ * frame.c (frame_pc_unwind): Update.
+ (create_sentinel_frame): Do not set "pc".
+ (get_prev_frame): Do not set "pc". Use frame_pc_unwind.
+ (get_frame_pc): Call frame_pc_unwind.
+ (deprecated_update_frame_pc_hack): Update.
+ (create_new_frame): Use "pc" not "->pc".
+
+2003-04-09 Andrew Cagney <cagney@redhat.com>
+
+ * frame.c (get_frame_id): Eliminate code updating "frame".
+ (legacy_get_prev_frame): Ditto.
+ (get_frame_base): Return id.base directly.
+ (deprecated_update_frame_base_hack): Update "id.base".
+ * frame.h (struct frame_info): Delete field "frame".
+
+2003-04-09 Andrew Cagney <cagney@redhat.com>
+
+ * NEWS: Mention that the "Sequent family" is obsolete.
+ * configure.tgt: Obsolete i[3456]86-sequent-bsd*,
+ i[3456]86-sequent-sysv4*, and i[3456]86-sequent-sysv*.
+ * configure.host: Obsolete i[3456]86-sequent-bsd*,
+ i[3456]86-sequent-sysv4*, and i[3456]86-sequent-sysv*.
+ * config/i386/tm-ptx4.h: Obsolete file.
+ * config/i386/tm-ptx.h: Obsolete file.
+ * symm-tdep.c: Obsolete file.
+ * config/i386/symmetry.mt: Obsolete file.
+ * config/i386/tm-symmetry.h: Obsolete file.
+ * symm-nat.c: Obsolete file.
+ * config/i386/nm-symmetry.h: Obsolete file.
+ * config/i386/xm-symmetry.h: Obsolete file.
+ * config/i386/symmetry.mh: Obsolete file.
+ * config/i386/nm-ptx4.h: Obsolete file.
+ * config/i386/ptx4.mh: Obsolete file.
+ * config/i386/ptx.mt: Obsolete file.
+ * config/i386/ptx.mh: Obsolete file.
+ * config/i386/xm-ptx4.h: Obsolete file.
+ * config/i386/xm-ptx.h: Obsolete file.
+
+2003-04-09 Andrew Cagney <cagney@redhat.com>
+
+ Obsolete mips*-*-mach3*.
+ * NEWS: Mention that mips*-*-mach3* is obsolete.
+ * m3-nat.c: Obsolete file.
+ * config/nm-m3.h: Obsolete file.
+ * config/mips/tm-mipsm3.h: Obsolete file.
+ * config/mips/mipsm3.mt: Obsolete file.
+ * config/mips/mipsm3.mh: Obsolete file.
+ * config/mips/xm-mipsm3.h: Obsolete file.
+ * mipsm3-nat.c: Obsolete file.
+ * configure.host: Obsolete mips-dec-mach3*.
+ * configure.tgt: Obsolete mips*-*-mach3*.
+
+2003-04-09 Andrew Cagney <cagney@redhat.com>
+
+ * doublest.h: Update copyright.
+ (deprecated_store_floating, deprecated_extract_floating): Rename
+ store_floating and extract_floating. Update comments.
+ * doublest.c: Update copyright.
+ (extract_floating_by_length): Replace extract_floating.
+ (store_floating_by_length): Replace store_floating.
+ (deprecated_extract_floating): New function.
+ (deprecated_store_floating): New function.
+ (extract_typed_floating): Call extract_floating_by_length.
+ (store_typed_floating): Call store_floating_by_length.
+ * x86-64-tdep.c (x86_64_store_return_value): Update.
+ * sh-tdep.c (sh3e_sh4_extract_return_value): Update.
+ (sh64_extract_return_value): Update.
+ (sh_sh4_register_convert_to_virtual): Update.
+ (sh_sh64_register_convert_to_virtual): Update.
+ (sh_sh4_register_convert_to_raw): Update.
+ (sh_sh64_register_convert_to_raw): Update.
+ * rs6000-tdep.c (rs6000_register_convert_to_virtual): Update.
+ (rs6000_register_convert_to_raw): Update.
+ * ia64-tdep.c (ia64_register_convert_to_virtual): Update.
+ (ia64_register_convert_to_raw): Update.
+ * config/i386/tm-symmetry.h (REGISTER_CONVERT_TO_RAW): Update.
+ (REGISTER_CONVERT_TO_VIRTUAL): Update.
+ * arm-linux-tdep.c (arm_linux_push_arguments): Update.
+ * alpha-tdep.c (alpha_register_convert_to_virtual): Update.
+ (alpha_register_convert_to_raw): Update.
+
+2003-04-08 Andrew Cagney <cagney@redhat.com>
+
+ * gdbarch.sh (SAVED_PC_AFTER_CALL): Add a predicate.
+ * gdbarch.h, gdbarch.c: Re-generate.
+ * d10v-tdep.c (d10v_saved_pc_after_call): Delete function.
+ (d10v_gdbarch_init): Do not set saved_pc_after_call.
+ * infrun.c (step_over_function): Call SAVED_PC_AFTER_CALL_P
+ conditionally, use frame_pc_unwind as an alternative. Add
+ comments.
+ * arch-utils.c (init_frame_pc_default): Only call
+ SAVED_PC_AFTER_CALL when available.
+
+2003-04-08 Elena Zannoni <ezannoni@redhat.com>
+
+ * infrun.c (stop_soon): Rename from stop_soon_quietly.
+ (struct inferior_status): Rename stop_soon_quietly field to stop_soon.
+ (clear_proceed_status): Rename stop_soon_quietly to stop_soon.
+ (start_remote): Ditto.
+ (handle_inferior_event): Ditto.
+ (save_inferior_status): Ditto.
+ (restore_inferior_status): Ditto.
+ * infcmd.c (attach_command): Ditto.
+ * fork-child.c (startup_inferior): Ditto.
+ * inferior.h (stop_soon): Rename from stop_soon_quietly.
+ * alpha-tdep.c (heuristic_proc_start): Ditto.
+ * mips-tdep.c (heuristic_proc_start): Ditto.
+ * solib-svr4.c (svr4_solib_create_inferior_hook): Ditto.
+ * solib-sunos.c (sunos_solib_create_inferior_hook): Ditto.
+ * solib-osf.c (osf_solib_create_inferior_hook): Ditto.
+ * solib-irix.c (irix_solib_create_inferior_hook): Ditto.
+ * remote-vx.c (vx_create_inferior): Ditto.
+
+2003-04-08 Elena Zannoni <ezannoni@redhat.com>
+
+ * infrun.c (stop_soon_quietly): Make it an enum, to better
+ override the default behavior of handle_inferior_event.
+ (clear_proceed_status): Update uses of stop_soon_quietly to
+ reflect that it is now an enum.
+ (start_remote): Ditto.
+ (handle_inferior_event): Change logic a bit if stop_soon_quietly
+ is set to handle the new GNU/Linux kernel behavior for
+ attach/sigstop. Update uses of stop_soon_quietly.
+ * inferior.h (enum stop_kind): New enum.
+ * infcmd.c (attach_command): Use STOP_QUIETLY_NO_SIGSTOP.
+ Reset normal handle_inferior_event behavior, afterwards.
+ * fork-child.c (startup_inferior): Update.
+ * alpha-tdep.c (heuristic_proc_start): Update.
+ * solib-svr4.c (svr4_solib_create_inferior_hook): Update.
+ * solib-sunos.c (sunos_solib_create_inferior_hook): Update.
+ * solib-osf.c (osf_solib_create_inferior_hook): Update.
+ * solib-irix.c (irix_solib_create_inferior_hook): Update.
+ * remote-vx.c (vx_create_inferior): Update.
+ * mips-tdep.c (heuristic_proc_start): Update.
+
+2003-04-07 Elena Zannoni <ezannoni@redhat.com>
+
+ * disasm.c (dump_insns): Move variables inside loop, or they will
+ be freed more than once, causing wild memory corruptions.
+ (gdb_disassembly): Look for the substring "-thread",
+ instead of "-threads" in the target name, to make sure to find
+ the 'multi-thread' target. Also, make sure we do the right thing
+ with the "core" target.
+
+2003-04-07 Kevin Buettner <kevinb@redhat.com>
+
+ * mips-tdep.c (mips_print_fp_register): New function, created from
+ do_fp_register_row(). Registers are now (also) printed as hex.
+ Only one register is printed per row.
+ (mips_print_register, do_fp_register_row): Print floating point
+ registers with mips_print_fp_register().
+
+2003-04-06 Andrew Cagney <cagney@redhat.com>
+
+ * valprint.h (inspect_it): Add extern declaration.
+ * objc-lang.c (value_nsstring): Avoid assignment inside of "if".
+ (selectors_info, classes_info): Ditto.
+ (find_objc_msgcall): Fix indentation.
+ (objc_printstr): Delete extern declarations.
+
+ * arm-tdep.c (arm_frameless_function_invocation): Fix typo.
+
+2003-04-06 Andrew Cagney <cagney@redhat.com>
+
+ * frame.h (legacy_frame_chain_valid): Rename frame_chain_valid.
+ Update comment.
+ * frame.c (legacy_saved_regs_this_id): Update.
+ (legacy_get_prev_frame): Update.
+ * xstormy16-tdep.c: Update comment.
+ * sparc-tdep.c (sparc_frame_chain): Update comment.
+ * blockframe.c (legacy_frame_chain_valid): Update.
+
2003-04-06 Andrew Cagney <cagney@redhat.com>
* valprint.c (val_print_type_code_int): Delete #ifdef
c-exp.y c-lang.c c-typeprint.c c-valprint.c \
charset.c cli-out.c coffread.c coff-pe-read.c \
complaints.c completer.c corefile.c \
- cp-abi.c cp-support.c cp-valprint.c \
+ cp-abi.c cp-support.c cp-namespace.c cp-valprint.c \
dbxread.c demangle.c disasm.c doublest.c \
dummy-frame.c dwarfread.c dwarf2expr.c dwarf2loc.c dwarf2read.c \
elfread.c environ.c eval.c event-loop.c event-top.c expprint.c \
elf_arm_h = $(INCLUDE_DIR)/elf/arm.h $(elf_reloc_macros_h)
elf_bfd_h = $(BFD_SRC)/elf-bfd.h
libaout_h = $(BFD_SRC)/libaout.h
+libbfd_h = $(BFD_SRC)/libbfd.h
remote_sim_h = $(INCLUDE_DIR)/gdb/remote-sim.h
demangle_h = $(INCLUDE_DIR)/demangle.h
obstack_h = $(INCLUDE_DIR)/obstack.h
frame.o frame-unwind.o doublest.o \
frame-base.o \
gnu-v2-abi.o gnu-v3-abi.o hpacc-abi.o cp-abi.o cp-support.o \
+ cp-namespace.o \
reggroups.o
OBS = $(COMMON_OBS) $(ANNOTATE_OBS)
$(regcache_h)
ax-general.o: ax-general.c $(defs_h) $(ax_h) $(value_h) $(gdb_string_h)
bcache.o: bcache.c $(defs_h) $(gdb_obstack_h) $(bcache_h) $(gdb_string_h)
-block.o: block.c $(defs_h) $(block_h) $(symtab_h) $(symfile_h)
+block.o: block.c $(defs_h) $(block_h) $(symtab_h) $(symfile_h) \
+ $(gdb_obstack_h) $(cp_support_h)
blockframe.o: blockframe.c $(defs_h) $(symtab_h) $(bfd_h) $(symfile_h) \
$(objfiles_h) $(frame_h) $(gdbcore_h) $(value_h) $(target_h) \
$(inferior_h) $(annotate_h) $(regcache_h) $(gdb_assert_h) \
$(symfile_h) $(objfiles_h) $(gdbtypes_h) $(gdb_assert_h) \
$(complaints_h) $(gdb_string_h) $(expression_h) $(language_h) \
$(bcache_h) $(filenames_h) $(macrotab_h) $(demangle_h) $(buildsym_h) \
- $(stabsread_h) $(block_h)
+ $(stabsread_h) $(block_h) $(cp_support_h)
builtin-regs.o: builtin-regs.c $(defs_h) $(builtin_regs_h) $(gdbtypes_h) \
$(gdb_string_h) $(gdb_assert_h)
c-lang.o: c-lang.c $(defs_h) $(symtab_h) $(gdbtypes_h) $(expression_h) \
$(gdbthread_h) $(regcache_h) $(symfile_h) $(readline_h)
cp-abi.o: cp-abi.c $(defs_h) $(value_h) $(cp_abi_h) $(command_h) \
$(gdbcmd_h) $(ui_out_h) $(gdb_string_h)
-cp-support.o: cp-support.c $(defs_h) $(cp_support_h)
+cp-namespace.o: cp-namespace.c $(defs_h) $(cp_support_h) $(gdb_obstack_h) \
+ $(symtab_h) $(symfile_h) $(gdb_assert_h) $(block_h)
+cp-support.o: cp-support.c $(defs_h) $(cp_support_h) $(gdb_string_h) \
+ $(demangle_h) $(gdb_assert_h) $(gdbcmd_h)
cp-valprint.o: cp-valprint.c $(defs_h) $(gdb_obstack_h) $(symtab_h) \
$(gdbtypes_h) $(expression_h) $(value_h) $(command_h) $(gdbcmd_h) \
$(demangle_h) $(annotate_h) $(gdb_string_h) $(c_lang_h) $(target_h) \
$(symfile_h) $(objfiles_h) $(elf_dwarf2_h) $(buildsym_h) \
$(demangle_h) $(expression_h) $(filenames_h) $(macrotab_h) \
$(language_h) $(complaints_h) $(bcache_h) $(dwarf2expr_h) \
- $(dwarf2loc_h) $(gdb_string_h) $(gdb_assert_h)
+ $(dwarf2loc_h) $(cp_support_h) $(gdb_string_h) $(gdb_assert_h)
dwarfread.o: dwarfread.c $(defs_h) $(symtab_h) $(gdbtypes_h) $(symfile_h) \
$(objfiles_h) $(elf_dwarf_h) $(buildsym_h) $(demangle_h) \
$(expression_h) $(language_h) $(complaints_h) $(gdb_string_h)
i386ly-tdep.o: i386ly-tdep.c $(defs_h) $(gdbcore_h) $(inferior_h) \
$(regcache_h) $(target_h) $(i386_tdep_h) $(osabi_h)
i386-cygwin-tdep.o: i386-cygwin-tdep.c $(defs_h) $(gdb_string_h) \
- $(i386_tdep_h) $(osabi_h)
+ $(i386_tdep_h) $(osabi_h) $(gdbcore_h) $(frame_h) $(dummy_frame_h)
i386nbsd-tdep.o: i386nbsd-tdep.c $(defs_h) $(gdbtypes_h) $(gdbcore_h) \
$(regcache_h) $(arch_utils_h) $(i386_tdep_h) $(i387_tdep_h) \
$(nbsd_tdep_h) $(solib_svr4_h) $(osabi_h)
symmisc.o: symmisc.c $(defs_h) $(symtab_h) $(gdbtypes_h) $(bfd_h) \
$(symfile_h) $(objfiles_h) $(breakpoint_h) $(command_h) \
$(gdb_obstack_h) $(language_h) $(bcache_h) $(gdb_string_h) \
- $(readline_h) $(block_h)
+ $(readline_h) $(block_h) $(gdb_regex_h)
symtab.o: symtab.c $(defs_h) $(symtab_h) $(gdbtypes_h) $(gdbcore_h) \
$(frame_h) $(target_h) $(value_h) $(symfile_h) $(objfiles_h) \
$(gdbcmd_h) $(call_cmds_h) $(gdb_regex_h) $(expression_h) \
HP/PA running BSD hppa*-*-bsd*
HP/PA running OSF/1 hppa*-*-osf*
HP/PA Pro target hppa*-*-pro*
+PMAX (MIPS) running Mach 3.0 mips*-*-mach3*
+Sequent family i[3456]86-sequent-sysv4*
+ i[3456]86-sequent-sysv*
+ i[3456]86-sequent-bsd*
+Tsqware Sparclet sparclet-*-*
+Fujitsu SPARClite sparclite-fujitsu-none or sparclite
* REMOVED configurations and files
#if !defined (ADA_LANG_H)
#define ADA_LANG_H 1
+struct partial_symbol;
+
#include "value.h"
#include "gdbtypes.h"
static gdbarch_frame_locals_address_ftype alpha_frame_locals_address;
static gdbarch_skip_prologue_ftype alpha_skip_prologue;
-static gdbarch_saved_pc_after_call_ftype alpha_saved_pc_after_call;
static gdbarch_fix_call_dummy_ftype alpha_fix_call_dummy;
static CORE_ADDR
alpha_init_frame_pc_first (int fromleaf, struct frame_info *prev)
{
- return (fromleaf ? SAVED_PC_AFTER_CALL (get_next_frame (prev))
- : get_next_frame (prev) ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev))
+ return (fromleaf
+ ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev))
+ : get_next_frame (prev)
+ ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev))
: read_pc ());
}
if (start_pc < fence)
{
/* It's not clear to me why we reach this point when
- stop_soon_quietly, but with this test, at least we
+ stop_soon, but with this test, at least we
don't print out warnings for every child forked (eg, on
decstation). 22apr93 rich@cygnus.com. */
- if (!stop_soon_quietly)
+ if (stop_soon == NO_STOP_QUIETLY)
{
static int blurb_printed = 0;
if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
{
- double d = extract_floating (raw_buffer, REGISTER_RAW_SIZE (regnum));
- store_floating (virtual_buffer, TYPE_LENGTH (valtype), d);
+ double d = deprecated_extract_floating (raw_buffer, REGISTER_RAW_SIZE (regnum));
+ deprecated_store_floating (virtual_buffer, TYPE_LENGTH (valtype), d);
}
else if (TYPE_CODE (valtype) == TYPE_CODE_INT && TYPE_LENGTH (valtype) <= 4)
{
if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
{
- double d = extract_floating (virtual_buffer, TYPE_LENGTH (valtype));
- store_floating (raw_buffer, REGISTER_RAW_SIZE (regnum), d);
+ double d = deprecated_extract_floating (virtual_buffer, TYPE_LENGTH (valtype));
+ deprecated_store_floating (raw_buffer, REGISTER_RAW_SIZE (regnum), d);
}
else if (TYPE_CODE (valtype) == TYPE_CODE_INT && TYPE_LENGTH (valtype) <= 4)
{
set_gdbarch_frameless_function_invocation (gdbarch,
generic_frameless_function_invocation_not);
- set_gdbarch_saved_pc_after_call (gdbarch, alpha_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, alpha_saved_pc_after_call);
set_gdbarch_deprecated_frame_chain (gdbarch, alpha_frame_chain);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, alpha_frame_saved_pc);
CORE_ADDR
init_frame_pc_default (int fromleaf, struct frame_info *prev)
{
- if (fromleaf)
- return SAVED_PC_AFTER_CALL (get_next_frame (prev));
+ if (fromleaf && DEPRECATED_SAVED_PC_AFTER_CALL_P ())
+ return DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev));
else if (get_next_frame (prev) != NULL)
return DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev));
else
#ifndef GDBARCH_UTILS_H
#define GDBARCH_UTILS_H
+struct gdbarch;
+struct frame_info;
+struct minimal_symbol;
+struct type;
+struct gdbarch_info;
+
/* gdbarch trace variable */
extern int gdbarch_debug;
if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len)
{
DOUBLEST dblval;
- dblval = extract_floating (val, len);
+ dblval = deprecated_extract_floating (val, len);
len = TARGET_DOUBLE_BIT / TARGET_CHAR_BIT;
val = alloca (len);
- store_floating (val, len, dblval);
+ deprecated_store_floating (val, len, dblval);
}
/* If the argument is a pointer to a function, and it is a Thumb
= lookup_minimal_symbol ("fixup", NULL, objfile);
if (fixup && SYMBOL_VALUE_ADDRESS (fixup) == pc)
- return (SAVED_PC_AFTER_CALL (get_current_frame ()));
+ return (DEPRECATED_SAVED_PC_AFTER_CALL (get_current_frame ()));
}
return 0;
stmdb sp!, {}
sub sp, ip, #4. */
- func_start = (get_frame_func (fi)) + FUNCTION_START_OFFSET);
+ func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET);
after_prologue = SKIP_PROLOGUE (func_start);
/* There are some frameless functions whose first two instructions
set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
/* Get the PC when a frame might not be available. */
- set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
/* The stack grows downward. */
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, avr_frame_saved_pc);
set_gdbarch_frame_args_address (gdbarch, avr_frame_address);
set_gdbarch_frame_locals_address (gdbarch, avr_frame_address);
- set_gdbarch_saved_pc_after_call (gdbarch, avr_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, avr_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
set_gdbarch_convert_from_func_ptr_addr (gdbarch,
#ifndef AX_GDB_H
#define AX_GDB_H
-\f
+
+struct expression;
/* Types and enums */
#include "block.h"
#include "symtab.h"
#include "symfile.h"
+#include "gdb_obstack.h"
+#include "cp-support.h"
+
+/* This is used by struct block to store namespace-related info for
+ C++ files, namely using declarations and the current namespace in
+ scope. */
+
+struct block_namespace_info
+{
+ const char *scope;
+ struct using_direct *using;
+};
+
+static void block_initialize_namespace (struct block *block,
+ struct obstack *obstack);
/* Return Nonzero if block a is lexically nested within block b,
or if a and b have the same pc range.
{
return block_for_pc_sect (pc, find_pc_mapped_section (pc));
}
+
+/* Now come some functions designed to deal with C++ namespace
+ issues. */
+
+/* Set BLOCK's scope member to SCOPE; if needed, allocate memory via
+ OBSTACK. (It won't make a copy of SCOPE, however, so that already
+ has to be allocated correctly.) */
+
+void
+block_set_scope (struct block *block, const char *scope,
+ struct obstack *obstack)
+{
+ block_initialize_namespace (block, obstack);
+
+ BLOCK_NAMESPACE (block)->scope = scope;
+}
+
+/* Set BLOCK's using member to USING; if needed, allocate memory via
+ OBSTACK. (It won't make a copy of USING, however, so that already
+ has to be allocated correctly.) */
+
+void
+block_set_using (struct block *block,
+ struct using_direct *using,
+ struct obstack *obstack)
+{
+ block_initialize_namespace (block, obstack);
+
+ BLOCK_NAMESPACE (block)->using = using;
+}
+
+/* If BLOCK_NAMESPACE (block) is NULL, allocate it via OBSTACK and
+ ititialize its members to zero. */
+
+static void
+block_initialize_namespace (struct block *block, struct obstack *obstack)
+{
+ if (BLOCK_NAMESPACE (block) == NULL)
+ {
+ BLOCK_NAMESPACE (block)
+ = obstack_alloc (obstack, sizeof (struct block_namespace_info));
+ BLOCK_NAMESPACE (block)->scope = NULL;
+ BLOCK_NAMESPACE (block)->using = NULL;
+ }
+}
struct symbol;
struct symtab;
+struct block_namespace_info;
+struct using_direct;
+struct obstack;
/* All of the name-scope contours of the program
are represented by `struct block' objects.
struct block *superblock;
+ /* Used for language-specific info. */
+
+ union
+ {
+ struct
+ {
+ /* Contains information about namespace-related info relevant to
+ this block: using directives and the current namespace
+ scope. */
+
+ struct block_namespace_info *namespace;
+ }
+ cplus_specific;
+ }
+ language_specific;
+
/* Version of GCC used to compile the function corresponding
to this block, or 0 if not compiled with GCC. When possible,
GCC should be compatible with the native compiler, or if that
#define BLOCK_FUNCTION(bl) (bl)->function
#define BLOCK_SUPERBLOCK(bl) (bl)->superblock
#define BLOCK_GCC_COMPILED(bl) (bl)->gcc_compile_flag
+#define BLOCK_NAMESPACE(bl) (bl)->language_specific.cplus_specific.namespace
#define BLOCK_HASHTABLE(bl) (bl)->hashtable
/* For blocks without a hashtable (BLOCK_HASHTABLE (bl) == 0) only. */
extern struct block *block_for_pc_sect (CORE_ADDR, asection *);
+extern void block_set_scope (struct block *block, const char *scope,
+ struct obstack *obstack);
+
+extern void block_set_using (struct block *block,
+ struct using_direct *using,
+ struct obstack *obstack);
+
#endif /* BLOCK_H */
&& (pc) <= (CALL_DUMMY_ADDRESS () + DECR_PC_AFTER_BREAK));
}
-/* Function: frame_chain_valid
- Returns true for a user frame or a call_function_by_hand dummy frame,
- and false for the CRT0 start-up frame. Purpose is to terminate backtrace. */
+/* Returns true for a user frame or a call_function_by_hand dummy
+ frame, and false for the CRT0 start-up frame. Purpose is to
+ terminate backtrace. */
int
-frame_chain_valid (CORE_ADDR fp, struct frame_info *fi)
+legacy_frame_chain_valid (CORE_ADDR fp, struct frame_info *fi)
{
/* Don't prune CALL_DUMMY frames. */
if (DEPRECATED_USE_GENERIC_DUMMY_FRAMES
if (INNER_THAN (fp, get_frame_base (fi)))
return 0;
+ /* If the architecture has a custom DEPRECATED_FRAME_CHAIN_VALID,
+ call it now. */
+ if (DEPRECATED_FRAME_CHAIN_VALID_P ())
+ return DEPRECATED_FRAME_CHAIN_VALID (fp, fi);
+
/* If we're already inside the entry function for the main objfile, then it
isn't valid. */
if (inside_entry_func (get_frame_pc (fi)))
if (inside_entry_file (frame_pc_unwind (fi)))
return 0;
- /* If the architecture has a custom DEPRECATED_FRAME_CHAIN_VALID,
- call it now. */
- if (DEPRECATED_FRAME_CHAIN_VALID_P ())
- return DEPRECATED_FRAME_CHAIN_VALID (fp, fi);
-
return 1;
}
ui_out_text (uiout, "\tstop only in stack frame at ");
/* FIXME: cagney/2002-12-01: Shouldn't be poeking around inside
the frame ID. */
- ui_out_field_core_addr (uiout, "frame", b->frame_id.base);
+ ui_out_field_core_addr (uiout, "frame", b->frame_id.stack_addr);
ui_out_text (uiout, "\n");
}
#include "macrotab.h"
#include "demangle.h" /* Needed by SYMBOL_INIT_DEMANGLED_NAME. */
#include "block.h"
+#include "cp-support.h"
+
/* Ask buildsym.h to define the vars it normally declares `extern'. */
#define EXTERN
/**/
}
}
-/* Add a symbol to one of the lists of symbols. */
+/* Add a symbol to one of the lists of symbols. While we're at it, if
+ we're in the C++ case and don't have full namespace debugging info,
+ check to see if it references an anonymous namespace; if so, add an
+ appropriate using directive. */
void
add_symbol_to_list (struct symbol *symbol, struct pending **listhead)
}
(*listhead)->symbol[(*listhead)->nsyms++] = symbol;
+
+ /* Check to see if we might need to look for a mention of anonymous
+ namespaces. */
+
+ if (SYMBOL_LANGUAGE (symbol) == language_cplus)
+ cp_scan_for_anonymous_namespaces (symbol);
}
/* Find a symbol named NAME on a LIST. NAME need not be
BLOCK_END (block) = end;
/* Superblock filled in when containing block is made */
BLOCK_SUPERBLOCK (block) = NULL;
+ BLOCK_NAMESPACE (block) = NULL;
BLOCK_GCC_COMPILED (block) = processing_gcc_compilation;
}
}
}
+
+ /* If we're in the C++ case, set the block's scope. */
+ if (SYMBOL_LANGUAGE (symbol) == language_cplus)
+ {
+ cp_set_block_scope (symbol, block, &objfile->symbol_obstack);
+ }
}
else
{
}
context_stack_depth = 0;
+ /* Set up support for C++ namespace support, in case we need it. */
+
+ cp_initialize_namespace ();
+
/* Initialize the list of sub source files with one entry for this
file (the top-level source file). */
finish_block (0, &global_symbols, 0, last_source_start_addr, end_addr,
objfile);
blockvector = make_blockvector (objfile);
+ cp_finalize_namespace (BLOCKVECTOR_BLOCK (blockvector, STATIC_BLOCK),
+ &objfile->symbol_obstack);
}
#ifndef PROCESS_LINENUMBER_HOOK
#if !defined (BUILDSYM_H)
#define BUILDSYM_H 1
+struct objfile;
+struct symbol;
+
/* This module provides definitions used for creating and adding to
the symbol table. These routines are called from various symbol-
file-reading routines.
#ifndef BUILTIN_REGS_H
#define BUILTIN_REGS_H
+struct frame_info;
+
extern int builtin_reg_map_name_to_regnum (const char *str, int len);
extern const char *builtin_reg_map_regnum_to_name (int regnum);
#if !defined (C_LANG_H)
#define C_LANG_H 1
+struct ui_file;
+
#include "value.h"
#include "macroexp.h"
#ifndef CLI_OUT_H
#define CLI_OUT_H
+struct ui_file;
+
extern struct ui_out *cli_out_new (struct ui_file *stream);
extern struct ui_file *cli_out_set_stream (struct ui_out *uiout,
struct cmd_list_element *maintenanceprintlist;
+/* Chain containing all defined "maintenance list" subcommands. */
+
+struct cmd_list_element *maintenancelistlist;
+
struct cmd_list_element *setprintlist;
struct cmd_list_element *showprintlist;
maintenancelist = NULL;
maintenanceinfolist = NULL;
maintenanceprintlist = NULL;
+ maintenancelistlist = NULL;
setprintlist = NULL;
showprintlist = NULL;
setchecklist = NULL;
extern struct cmd_list_element *maintenanceprintlist;
+/* Chain containing all defined "maintenance list" subcommands. */
+
+extern struct cmd_list_element *maintenancelistlist;
+
extern struct cmd_list_element *setprintlist;
extern struct cmd_list_element *showprintlist;
#if !defined (CLI_SCRIPT_H)
#define CLI_SCRIPT_H 1
+struct ui_file;
+struct command_line;
+struct cmd_list_element;
+
/* Exported to cli/cli-cmds.c */
extern void script_from_file (FILE *stream, char *file);
#if !defined (CLI_SETSHOW_H)
#define CLI_SETSHOW_H 1
+struct cmd_list_element;
+
/* Exported to cli/cli-cmds.c and gdb/top.c */
/* Do a "set" or "show" command. ARG is NULL if no argument, or the text
-/* Definitions to make GDB run on a Sequent Symmetry under ptx
- with Weitek 1167 and i387 support.
- Copyright 1986, 1987, 1989, 1992, 1994, 1996, 2000
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#include "regcache.h"
-
-#include "config/nm-sysv4.h"
-
-#undef USE_PROC_FS
-
-#include "i386/nm-symmetry.h"
-
-#define PTRACE_READ_REGS(pid,regaddr) mptrace (XPT_RREGS, (pid), (regaddr), 0)
-#define PTRACE_WRITE_REGS(pid,regaddr) \
- mptrace (XPT_WREGS, (pid), (regaddr), 0)
-
-/* Override copies of {fetch,store}_inferior_registers in infptrace.c. */
-
-#define FETCH_INFERIOR_REGISTERS
-
-/* We must fetch all the regs before storing, since we store all at once. */
-
-#define CHILD_PREPARE_TO_STORE() deprecated_read_register_bytes (0, NULL, REGISTER_BYTES)
-
-#define CHILD_WAIT
-struct target_waitstatus;
-extern ptid_t child_wait (ptid_t, struct target_waitstatus *);
-
-/*
- * ptx does attach as of ptx version 2.1. Prior to that, the interface
- * exists but does not work.
- *
- * FIXME: Using attach/detach requires using the ptx MPDEBUGGER
- * interface. There are still problems with that, so for now don't
- * enable attach/detach. If you turn it on anyway, it will mostly
- * work, but has a number of bugs. -fubar, 2/94.
- */
-/*#define ATTACH_DETACH 1 */
-#undef ATTACH_DETACH
-#define PTRACE_ATTACH XPT_DEBUG
-#define PTRACE_DETACH XPT_UNDEBUG
-/*
- * The following drivel is needed because there are two ptrace-ish
- * calls on ptx: ptrace() and mptrace(), each of which does about half
- * of the ptrace functions.
- */
-#define PTRACE_ATTACH_CALL(pid) ptx_do_attach(pid)
-#define PTRACE_DETACH_CALL(pid, signo) ptx_do_detach(pid, signo)
+// OBSOLETE /* Definitions to make GDB run on a Sequent Symmetry under ptx
+// OBSOLETE with Weitek 1167 and i387 support.
+// OBSOLETE Copyright 1986, 1987, 1989, 1992, 1994, 1996, 2000
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE #include "config/nm-sysv4.h"
+// OBSOLETE
+// OBSOLETE #undef USE_PROC_FS
+// OBSOLETE
+// OBSOLETE #include "i386/nm-symmetry.h"
+// OBSOLETE
+// OBSOLETE #define PTRACE_READ_REGS(pid,regaddr) mptrace (XPT_RREGS, (pid), (regaddr), 0)
+// OBSOLETE #define PTRACE_WRITE_REGS(pid,regaddr) \
+// OBSOLETE mptrace (XPT_WREGS, (pid), (regaddr), 0)
+// OBSOLETE
+// OBSOLETE /* Override copies of {fetch,store}_inferior_registers in infptrace.c. */
+// OBSOLETE
+// OBSOLETE #define FETCH_INFERIOR_REGISTERS
+// OBSOLETE
+// OBSOLETE /* We must fetch all the regs before storing, since we store all at once. */
+// OBSOLETE
+// OBSOLETE #define CHILD_PREPARE_TO_STORE() deprecated_read_register_bytes (0, NULL, REGISTER_BYTES)
+// OBSOLETE
+// OBSOLETE #define CHILD_WAIT
+// OBSOLETE struct target_waitstatus;
+// OBSOLETE extern ptid_t child_wait (ptid_t, struct target_waitstatus *);
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * ptx does attach as of ptx version 2.1. Prior to that, the interface
+// OBSOLETE * exists but does not work.
+// OBSOLETE *
+// OBSOLETE * FIXME: Using attach/detach requires using the ptx MPDEBUGGER
+// OBSOLETE * interface. There are still problems with that, so for now don't
+// OBSOLETE * enable attach/detach. If you turn it on anyway, it will mostly
+// OBSOLETE * work, but has a number of bugs. -fubar, 2/94.
+// OBSOLETE */
+// OBSOLETE /*#define ATTACH_DETACH 1 */
+// OBSOLETE #undef ATTACH_DETACH
+// OBSOLETE #define PTRACE_ATTACH XPT_DEBUG
+// OBSOLETE #define PTRACE_DETACH XPT_UNDEBUG
+// OBSOLETE /*
+// OBSOLETE * The following drivel is needed because there are two ptrace-ish
+// OBSOLETE * calls on ptx: ptrace() and mptrace(), each of which does about half
+// OBSOLETE * of the ptrace functions.
+// OBSOLETE */
+// OBSOLETE #define PTRACE_ATTACH_CALL(pid) ptx_do_attach(pid)
+// OBSOLETE #define PTRACE_DETACH_CALL(pid, signo) ptx_do_detach(pid, signo)
-/* Definitions to make GDB run on a Sequent Symmetry under dynix 3.0,
- with Weitek 1167 and i387 support.
- Copyright 1986, 1987, 1989, 1992, 1994, 1996, 1998, 2000
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#include "regcache.h"
-
-/* Override copies of {fetch,store}_inferior_registers in infptrace.c. */
-
-#define FETCH_INFERIOR_REGISTERS
-
-/* We must fetch all the regs before storing, since we store all at once. */
-
-#define CHILD_PREPARE_TO_STORE() deprecated_read_register_bytes (0, NULL, REGISTER_BYTES)
-
-#ifdef _SEQUENT_
-#define CHILD_WAIT
-extern ptid_t child_wait (ptid_t, struct target_waitstatus *);
-#endif
-
-/* This is the amount to subtract from u.u_ar0
- to get the offset in the core file of the register values. */
-
-#ifdef _SEQUENT_
-#include <sys/param.h>
-#include <sys/user.h>
-#include <sys/mc_vmparam.h>
-/* VA_UAREA is defined in <sys/mc_vmparam.h>, and is dependant upon
- sizeof(struct user) */
-#define KERNEL_U_ADDR (VA_UAREA) /* ptx */
-#else
-#define KERNEL_U_ADDR (0x80000000 - (UPAGES * NBPG)) /* dynix */
-#endif
+// OBSOLETE /* Definitions to make GDB run on a Sequent Symmetry under dynix 3.0,
+// OBSOLETE with Weitek 1167 and i387 support.
+// OBSOLETE Copyright 1986, 1987, 1989, 1992, 1994, 1996, 1998, 2000
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE /* Override copies of {fetch,store}_inferior_registers in infptrace.c. */
+// OBSOLETE
+// OBSOLETE #define FETCH_INFERIOR_REGISTERS
+// OBSOLETE
+// OBSOLETE /* We must fetch all the regs before storing, since we store all at once. */
+// OBSOLETE
+// OBSOLETE #define CHILD_PREPARE_TO_STORE() deprecated_read_register_bytes (0, NULL, REGISTER_BYTES)
+// OBSOLETE
+// OBSOLETE #ifdef _SEQUENT_
+// OBSOLETE #define CHILD_WAIT
+// OBSOLETE extern ptid_t child_wait (ptid_t, struct target_waitstatus *);
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* This is the amount to subtract from u.u_ar0
+// OBSOLETE to get the offset in the core file of the register values. */
+// OBSOLETE
+// OBSOLETE #ifdef _SEQUENT_
+// OBSOLETE #include <sys/param.h>
+// OBSOLETE #include <sys/user.h>
+// OBSOLETE #include <sys/mc_vmparam.h>
+// OBSOLETE /* VA_UAREA is defined in <sys/mc_vmparam.h>, and is dependant upon
+// OBSOLETE sizeof(struct user) */
+// OBSOLETE #define KERNEL_U_ADDR (VA_UAREA) /* ptx */
+// OBSOLETE #else
+// OBSOLETE #define KERNEL_U_ADDR (0x80000000 - (UPAGES * NBPG)) /* dynix */
+// OBSOLETE #endif
-# Host: Sequent Symmetry running ptx 1.3, with Weitek 1167 or i387
-
-XM_FILE= xm-ptx.h
-NATDEPFILES= inftarg.o fork-child.o symm-nat.o corelow.o core-aout.o
-XM_CLIBS= -lPW -lseq
-
-NAT_FILE= nm-symmetry.h
+# OBSOLETE # Host: Sequent Symmetry running ptx 1.3, with Weitek 1167 or i387
+# OBSOLETE
+# OBSOLETE XM_FILE= xm-ptx.h
+# OBSOLETE NATDEPFILES= inftarg.o fork-child.o symm-nat.o corelow.o core-aout.o
+# OBSOLETE XM_CLIBS= -lPW -lseq
+# OBSOLETE
+# OBSOLETE NAT_FILE= nm-symmetry.h
-# Target: Sequent Symmetry running ptx 2.0, with Weitek 1167 or i387.
-TDEPFILES= symm-tdep.o i387-tdep.o i386-tdep.o
-TM_FILE= tm-ptx.h
+# OBSOLETE # Target: Sequent Symmetry running ptx 2.0, with Weitek 1167 or i387.
+# OBSOLETE TDEPFILES= symm-tdep.o i387-tdep.o i386-tdep.o
+# OBSOLETE TM_FILE= tm-ptx.h
-# Host: Sequent Symmetry running ptx 1.3, with Weitek 1167 or i387
-
-XM_FILE= xm-ptx4.h
-NATDEPFILES= inftarg.o fork-child.o symm-nat.o corelow.o core-aout.o \
- core-regset.o solib.o solib-svr4.o solib-legacy.o
-XM_CLIBS= -lseq
-
-NAT_FILE= nm-ptx4.h
+# OBSOLETE # Host: Sequent Symmetry running ptx 1.3, with Weitek 1167 or i387
+# OBSOLETE
+# OBSOLETE XM_FILE= xm-ptx4.h
+# OBSOLETE NATDEPFILES= inftarg.o fork-child.o symm-nat.o corelow.o core-aout.o \
+# OBSOLETE core-regset.o solib.o solib-svr4.o solib-legacy.o
+# OBSOLETE XM_CLIBS= -lseq
+# OBSOLETE
+# OBSOLETE NAT_FILE= nm-ptx4.h
-# Target: Sequent Symmetry running ptx 4.0, with Weitek 1167 or i387.
-TDEPFILES= symm-tdep.o i387-tdep.o i386-tdep.o
-TM_FILE= tm-ptx4.h
+# OBSOLETE # Target: Sequent Symmetry running ptx 4.0, with Weitek 1167 or i387.
+# OBSOLETE TDEPFILES= symm-tdep.o i387-tdep.o i386-tdep.o
+# OBSOLETE TM_FILE= tm-ptx4.h
-# Host: Sequent Symmetry running Dynix 3.0, with Weitek 1167 or i387.
-XM_FILE= xm-symmetry.h
-NAT_FILE= nm-symmetry.h
-NATDEPFILES= inftarg.o fork-child.o corelow.o core-aout.o symm-nat.o
+# OBSOLETE # Host: Sequent Symmetry running Dynix 3.0, with Weitek 1167 or i387.
+# OBSOLETE XM_FILE= xm-symmetry.h
+# OBSOLETE NAT_FILE= nm-symmetry.h
+# OBSOLETE NATDEPFILES= inftarg.o fork-child.o corelow.o core-aout.o symm-nat.o
-# Target: Sequent Symmetry running Dynix 3.0, with Weitek 1167 or i387.
-TDEPFILES= i386-tdep.o symm-tdep.o i387-tdep.o
-TM_FILE= tm-symmetry.h
+# OBSOLETE # Target: Sequent Symmetry running Dynix 3.0, with Weitek 1167 or i387.
+# OBSOLETE TDEPFILES= i386-tdep.o symm-tdep.o i387-tdep.o
+# OBSOLETE TM_FILE= tm-symmetry.h
-/* Target machine definitions for GDB on a Sequent Symmetry under ptx
- with Weitek 1167 and i387 support.
-
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 2000,
- 2003 Free Software Foundation, Inc.
-
- Symmetry version by Jay Vosburgh (fubar@sequent.com).
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#ifndef TM_PTX_H
-#define TM_PTX_H 1
-
-/* I don't know if this will work for cross-debugging, even if you do get
- a copy of the right include file. */
-
-#include <sys/reg.h>
-
-#ifdef SEQUENT_PTX4
-#include "i386/tm-i386.h"
-#else /* !SEQUENT_PTX4 */
-#include "i386/tm-i386.h"
-#endif
-
-/* Amount PC must be decremented by after a breakpoint. This is often the
- number of bytes in BREAKPOINT but not always (such as now). */
-
-#undef DECR_PC_AFTER_BREAK
-#define DECR_PC_AFTER_BREAK 0
-
-/* Number of machine registers */
-
-#undef NUM_REGS
-#define NUM_REGS 49
-
-/* Initializer for an array of names of registers. There should be at least
- NUM_REGS strings in this initializer. Any excess ones are simply ignored.
- The order of the first 8 registers must match the compiler's numbering
- scheme (which is the same as the 386 scheme) and also regmap in the various
- *-nat.c files. */
-
-#undef REGISTER_NAME
-#define REGISTER_NAMES { "eax", "ecx", "edx", "ebx", \
- "esp", "ebp", "esi", "edi", \
- "eip", "eflags", "st0", "st1", \
- "st2", "st3", "st4", "st5", \
- "st6", "st7", "fp1", "fp2", \
- "fp3", "fp4", "fp5", "fp6", \
- "fp7", "fp8", "fp9", "fp10", \
- "fp11", "fp12", "fp13", "fp14", \
- "fp15", "fp16", "fp17", "fp18", \
- "fp19", "fp20", "fp21", "fp22", \
- "fp23", "fp24", "fp25", "fp26", \
- "fp27", "fp28", "fp29", "fp30", \
- "fp31" }
-
-/* Register numbers of various important registers.
- Note that some of these values are "real" register numbers,
- and correspond to the general registers of the machine,
- and some are "phony" register numbers which are too large
- to be actual register numbers as far as the user is concerned
- but do serve to get the desired values when passed to read_register. */
-
-#define EAX_REGNUM 0
-#define ECX_REGNUM 1
-#define EDX_REGNUM 2
-#define EBX_REGNUM 3
-
-#define ESP_REGNUM 4
-#define EBP_REGNUM 5
-
-#define ESI_REGNUM 6
-#define EDI_REGNUM 7
-
-#define EIP_REGNUM 8
-#define EFLAGS_REGNUM 9
-
-#define ST0_REGNUM 10
-#define ST1_REGNUM 11
-#define ST2_REGNUM 12
-#define ST3_REGNUM 13
-
-#define ST4_REGNUM 14
-#define ST5_REGNUM 15
-#define ST6_REGNUM 16
-#define ST7_REGNUM 17
-
-#define FP1_REGNUM 18 /* first 1167 register */
-/* Get %fp2 - %fp31 by addition, since they are contiguous */
-
-#undef SP_REGNUM
-#define SP_REGNUM ESP_REGNUM /* Contains address of top of stack */
-#undef FP_REGNUM
-#define FP_REGNUM EBP_REGNUM /* Contains address of executing stack frame */
-#undef PC_REGNUM
-#define PC_REGNUM EIP_REGNUM /* Contains program counter */
-#undef PS_REGNUM
-#define PS_REGNUM EFLAGS_REGNUM /* Contains processor status */
-
-/*
- * For ptx, this is a little bit bizarre, since the register block
- * is below the u area in memory. This means that blockend here ends
- * up being negative (for the call from coredep.c) since the value in
- * u.u_ar0 will be less than KERNEL_U_ADDR (and coredep.c passes us
- * u.u_ar0 - KERNEL_U_ADDR in blockend). Since we also define
- * FETCH_INFERIOR_REGISTERS (and supply our own functions for that),
- * the core file case will be the only use of this function.
- */
-
-#define REGISTER_U_ADDR(addr, blockend, regno) \
-{ (addr) = ptx_register_u_addr((blockend), (regno)); }
-
-extern int ptx_register_u_addr (int, int);
-
-/* Total amount of space needed to store our copies of the machine's
- register state, the array `registers'. 10 i*86 registers, 8 i387
- registers, and 31 Weitek 1167 registers */
-
-#undef REGISTER_BYTES
-#define REGISTER_BYTES ((10 * 4) + (8 * 10) + (31 * 4))
-
-/* Largest value REGISTER_RAW_SIZE can have. */
-
-#undef DEPRECATED_MAX_REGISTER_RAW_SIZE
-#define DEPRECATED_MAX_REGISTER_RAW_SIZE 10
-
-/* Nonzero if register N requires conversion
- from raw format to virtual format. */
-
-#undef REGISTER_CONVERTIBLE
-#define REGISTER_CONVERTIBLE(N) \
-((N < ST0_REGNUM) ? 0 : \
- (N < FP1_REGNUM) ? 1 : \
- 0)
-
-/* Convert data from raw format for register REGNUM
- to virtual format for register REGNUM. */
-extern const struct floatformat floatformat_i387_ext; /* from floatformat.h */
-
-#undef REGISTER_CONVERT_TO_VIRTUAL
-#define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \
-((REGNUM < ST0_REGNUM) ? (void)memcpy ((TO), (FROM), 4) : \
- (REGNUM < FP1_REGNUM) ? (void)floatformat_to_double(&floatformat_i387_ext, \
- (FROM),(TO)) : \
- (void)memcpy ((TO), (FROM), 4))
-
-/* Convert data from virtual format for register REGNUM
- to raw format for register REGNUM. */
-
-#undef REGISTER_CONVERT_TO_RAW
-#define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \
-((REGNUM < ST0_REGNUM) ? (void)memcpy ((TO), (FROM), 4) : \
- (REGNUM < FP1_REGNUM) ? (void)floatformat_from_double(&floatformat_i387_ext, \
- (FROM),(TO)) : \
- (void)memcpy ((TO), (FROM), 4))
-
-/* Return the GDB type object for the "standard" data type
- of data in register N. */
-/*
- * Note: the 1167 registers (the last line, builtin_type_float) are
- * generally used in pairs, with each pair being treated as a double.
- * It it also possible to use them singly as floats. I'm not sure how
- * in gdb to treat the register pair pseudo-doubles. -fubar
- */
-#undef REGISTER_VIRTUAL_TYPE
-#define REGISTER_VIRTUAL_TYPE(N) \
-((N < ST0_REGNUM) ? builtin_type_int : \
- (N < FP1_REGNUM) ? builtin_type_double : \
- builtin_type_float)
-
-/* Extract from an array REGBUF containing the (raw) register state
- a function return value of type TYPE, and copy that, in virtual format,
- into VALBUF. */
-
-#undef DEPRECATED_EXTRACT_RETURN_VALUE
-#define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
- symmetry_extract_return_value(TYPE, REGBUF, VALBUF)
-
-#endif /* ifndef TM_PTX_H */
+// OBSOLETE /* Target machine definitions for GDB on a Sequent Symmetry under ptx
+// OBSOLETE with Weitek 1167 and i387 support.
+// OBSOLETE
+// OBSOLETE Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 2000,
+// OBSOLETE 2003 Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE Symmetry version by Jay Vosburgh (fubar@sequent.com).
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #ifndef TM_PTX_H
+// OBSOLETE #define TM_PTX_H 1
+// OBSOLETE
+// OBSOLETE /* I don't know if this will work for cross-debugging, even if you do get
+// OBSOLETE a copy of the right include file. */
+// OBSOLETE
+// OBSOLETE #include <sys/reg.h>
+// OBSOLETE
+// OBSOLETE #ifdef SEQUENT_PTX4
+// OBSOLETE #include "i386/tm-i386.h"
+// OBSOLETE #else /* !SEQUENT_PTX4 */
+// OBSOLETE #include "i386/tm-i386.h"
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* Amount PC must be decremented by after a breakpoint. This is often the
+// OBSOLETE number of bytes in BREAKPOINT but not always (such as now). */
+// OBSOLETE
+// OBSOLETE #undef DECR_PC_AFTER_BREAK
+// OBSOLETE #define DECR_PC_AFTER_BREAK 0
+// OBSOLETE
+// OBSOLETE /* Number of machine registers */
+// OBSOLETE
+// OBSOLETE #undef NUM_REGS
+// OBSOLETE #define NUM_REGS 49
+// OBSOLETE
+// OBSOLETE /* Initializer for an array of names of registers. There should be at least
+// OBSOLETE NUM_REGS strings in this initializer. Any excess ones are simply ignored.
+// OBSOLETE The order of the first 8 registers must match the compiler's numbering
+// OBSOLETE scheme (which is the same as the 386 scheme) and also regmap in the various
+// OBSOLETE *-nat.c files. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_NAME
+// OBSOLETE #define REGISTER_NAMES { "eax", "ecx", "edx", "ebx", \
+// OBSOLETE "esp", "ebp", "esi", "edi", \
+// OBSOLETE "eip", "eflags", "st0", "st1", \
+// OBSOLETE "st2", "st3", "st4", "st5", \
+// OBSOLETE "st6", "st7", "fp1", "fp2", \
+// OBSOLETE "fp3", "fp4", "fp5", "fp6", \
+// OBSOLETE "fp7", "fp8", "fp9", "fp10", \
+// OBSOLETE "fp11", "fp12", "fp13", "fp14", \
+// OBSOLETE "fp15", "fp16", "fp17", "fp18", \
+// OBSOLETE "fp19", "fp20", "fp21", "fp22", \
+// OBSOLETE "fp23", "fp24", "fp25", "fp26", \
+// OBSOLETE "fp27", "fp28", "fp29", "fp30", \
+// OBSOLETE "fp31" }
+// OBSOLETE
+// OBSOLETE /* Register numbers of various important registers.
+// OBSOLETE Note that some of these values are "real" register numbers,
+// OBSOLETE and correspond to the general registers of the machine,
+// OBSOLETE and some are "phony" register numbers which are too large
+// OBSOLETE to be actual register numbers as far as the user is concerned
+// OBSOLETE but do serve to get the desired values when passed to read_register. */
+// OBSOLETE
+// OBSOLETE #define EAX_REGNUM 0
+// OBSOLETE #define ECX_REGNUM 1
+// OBSOLETE #define EDX_REGNUM 2
+// OBSOLETE #define EBX_REGNUM 3
+// OBSOLETE
+// OBSOLETE #define ESP_REGNUM 4
+// OBSOLETE #define EBP_REGNUM 5
+// OBSOLETE
+// OBSOLETE #define ESI_REGNUM 6
+// OBSOLETE #define EDI_REGNUM 7
+// OBSOLETE
+// OBSOLETE #define EIP_REGNUM 8
+// OBSOLETE #define EFLAGS_REGNUM 9
+// OBSOLETE
+// OBSOLETE #define ST0_REGNUM 10
+// OBSOLETE #define ST1_REGNUM 11
+// OBSOLETE #define ST2_REGNUM 12
+// OBSOLETE #define ST3_REGNUM 13
+// OBSOLETE
+// OBSOLETE #define ST4_REGNUM 14
+// OBSOLETE #define ST5_REGNUM 15
+// OBSOLETE #define ST6_REGNUM 16
+// OBSOLETE #define ST7_REGNUM 17
+// OBSOLETE
+// OBSOLETE #define FP1_REGNUM 18 /* first 1167 register */
+// OBSOLETE /* Get %fp2 - %fp31 by addition, since they are contiguous */
+// OBSOLETE
+// OBSOLETE #undef SP_REGNUM
+// OBSOLETE #define SP_REGNUM ESP_REGNUM /* Contains address of top of stack */
+// OBSOLETE #undef FP_REGNUM
+// OBSOLETE #define FP_REGNUM EBP_REGNUM /* Contains address of executing stack frame */
+// OBSOLETE #undef PC_REGNUM
+// OBSOLETE #define PC_REGNUM EIP_REGNUM /* Contains program counter */
+// OBSOLETE #undef PS_REGNUM
+// OBSOLETE #define PS_REGNUM EFLAGS_REGNUM /* Contains processor status */
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * For ptx, this is a little bit bizarre, since the register block
+// OBSOLETE * is below the u area in memory. This means that blockend here ends
+// OBSOLETE * up being negative (for the call from coredep.c) since the value in
+// OBSOLETE * u.u_ar0 will be less than KERNEL_U_ADDR (and coredep.c passes us
+// OBSOLETE * u.u_ar0 - KERNEL_U_ADDR in blockend). Since we also define
+// OBSOLETE * FETCH_INFERIOR_REGISTERS (and supply our own functions for that),
+// OBSOLETE * the core file case will be the only use of this function.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE #define REGISTER_U_ADDR(addr, blockend, regno) \
+// OBSOLETE { (addr) = ptx_register_u_addr((blockend), (regno)); }
+// OBSOLETE
+// OBSOLETE extern int ptx_register_u_addr (int, int);
+// OBSOLETE
+// OBSOLETE /* Total amount of space needed to store our copies of the machine's
+// OBSOLETE register state, the array `registers'. 10 i*86 registers, 8 i387
+// OBSOLETE registers, and 31 Weitek 1167 registers */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_BYTES
+// OBSOLETE #define REGISTER_BYTES ((10 * 4) + (8 * 10) + (31 * 4))
+// OBSOLETE
+// OBSOLETE /* Largest value REGISTER_RAW_SIZE can have. */
+// OBSOLETE
+// OBSOLETE #undef DEPRECATED_MAX_REGISTER_RAW_SIZE
+// OBSOLETE #define DEPRECATED_MAX_REGISTER_RAW_SIZE 10
+// OBSOLETE
+// OBSOLETE /* Nonzero if register N requires conversion
+// OBSOLETE from raw format to virtual format. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_CONVERTIBLE
+// OBSOLETE #define REGISTER_CONVERTIBLE(N) \
+// OBSOLETE ((N < ST0_REGNUM) ? 0 : \
+// OBSOLETE (N < FP1_REGNUM) ? 1 : \
+// OBSOLETE 0)
+// OBSOLETE
+// OBSOLETE /* Convert data from raw format for register REGNUM
+// OBSOLETE to virtual format for register REGNUM. */
+// OBSOLETE extern const struct floatformat floatformat_i387_ext; /* from floatformat.h */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_CONVERT_TO_VIRTUAL
+// OBSOLETE #define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \
+// OBSOLETE ((REGNUM < ST0_REGNUM) ? (void)memcpy ((TO), (FROM), 4) : \
+// OBSOLETE (REGNUM < FP1_REGNUM) ? (void)floatformat_to_double(&floatformat_i387_ext, \
+// OBSOLETE (FROM),(TO)) : \
+// OBSOLETE (void)memcpy ((TO), (FROM), 4))
+// OBSOLETE
+// OBSOLETE /* Convert data from virtual format for register REGNUM
+// OBSOLETE to raw format for register REGNUM. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_CONVERT_TO_RAW
+// OBSOLETE #define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \
+// OBSOLETE ((REGNUM < ST0_REGNUM) ? (void)memcpy ((TO), (FROM), 4) : \
+// OBSOLETE (REGNUM < FP1_REGNUM) ? (void)floatformat_from_double(&floatformat_i387_ext, \
+// OBSOLETE (FROM),(TO)) : \
+// OBSOLETE (void)memcpy ((TO), (FROM), 4))
+// OBSOLETE
+// OBSOLETE /* Return the GDB type object for the "standard" data type
+// OBSOLETE of data in register N. */
+// OBSOLETE /*
+// OBSOLETE * Note: the 1167 registers (the last line, builtin_type_float) are
+// OBSOLETE * generally used in pairs, with each pair being treated as a double.
+// OBSOLETE * It it also possible to use them singly as floats. I'm not sure how
+// OBSOLETE * in gdb to treat the register pair pseudo-doubles. -fubar
+// OBSOLETE */
+// OBSOLETE #undef REGISTER_VIRTUAL_TYPE
+// OBSOLETE #define REGISTER_VIRTUAL_TYPE(N) \
+// OBSOLETE ((N < ST0_REGNUM) ? builtin_type_int : \
+// OBSOLETE (N < FP1_REGNUM) ? builtin_type_double : \
+// OBSOLETE builtin_type_float)
+// OBSOLETE
+// OBSOLETE /* Extract from an array REGBUF containing the (raw) register state
+// OBSOLETE a function return value of type TYPE, and copy that, in virtual format,
+// OBSOLETE into VALBUF. */
+// OBSOLETE
+// OBSOLETE #undef DEPRECATED_EXTRACT_RETURN_VALUE
+// OBSOLETE #define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
+// OBSOLETE symmetry_extract_return_value(TYPE, REGBUF, VALBUF)
+// OBSOLETE
+// OBSOLETE #endif /* ifndef TM_PTX_H */
-/* Target machine definitions for GDB on a Sequent Symmetry under ptx
- with Weitek 1167 and i387 support.
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994
- Free Software Foundation, Inc.
- Symmetry version by Jay Vosburgh (fubar@sequent.com).
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#define SEQUENT_PTX4
-
-#include "i386/tm-ptx.h"
+// OBSOLETE /* Target machine definitions for GDB on a Sequent Symmetry under ptx
+// OBSOLETE with Weitek 1167 and i387 support.
+// OBSOLETE Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE Symmetry version by Jay Vosburgh (fubar@sequent.com).
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #define SEQUENT_PTX4
+// OBSOLETE
+// OBSOLETE #include "i386/tm-ptx.h"
-/* Target machine definitions for GDB on a Sequent Symmetry under dynix 3.0,
- with Weitek 1167 and i387 support.
-
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 2003 Free
- Software Foundation, Inc.
-
- Symmetry version by Jay Vosburgh (fubar@sequent.com).
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#ifndef TM_SYMMETRY_H
-#define TM_SYMMETRY_H 1
-
-#include "regcache.h"
-#include "doublest.h"
-
-/* I don't know if this will work for cross-debugging, even if you do get
- a copy of the right include file. */
-#include <machine/reg.h>
-
-#include "i386/tm-i386.h"
-
-/* Amount PC must be decremented by after a breakpoint. This is often the
- number of bytes in BREAKPOINT but not always (such as now). */
-
-#undef DECR_PC_AFTER_BREAK
-#define DECR_PC_AFTER_BREAK 0
-
-/* Number of machine registers */
-
-#undef NUM_REGS
-#define NUM_REGS 49
-
-/* Initializer for an array of names of registers.
- There should be NUM_REGS strings in this initializer. */
-
-/* Initializer for an array of names of registers. There should be at least
- NUM_REGS strings in this initializer. Any excess ones are simply ignored.
- Symmetry registers are in this weird order to match the register numbers
- in the symbol table entries. If you change the order, things will probably
- break mysteriously for no apparent reason. Also note that the st(0)...
- st(7) 387 registers are represented as st0...st7. */
-
-#undef REGISTER_NAME
-#define REGISTER_NAMES { "eax", "edx", "ecx", "st0", "st1", \
- "ebx", "esi", "edi", "st2", "st3", \
- "st4", "st5", "st6", "st7", "esp", \
- "ebp", "eip", "eflags","fp1", "fp2", \
- "fp3", "fp4", "fp5", "fp6", "fp7", \
- "fp8", "fp9", "fp10", "fp11", "fp12", \
- "fp13", "fp14", "fp15", "fp16", "fp17", \
- "fp18", "fp19", "fp20", "fp21", "fp22", \
- "fp23", "fp24", "fp25", "fp26", "fp27", \
- "fp28", "fp29", "fp30", "fp31" }
-
-/* Register numbers of various important registers.
- Note that some of these values are "real" register numbers,
- and correspond to the general registers of the machine,
- and some are "phony" register numbers which are too large
- to be actual register numbers as far as the user is concerned
- but do serve to get the desired values when passed to read_register. */
-
-#define EAX_REGNUM 0
-#define EDX_REGNUM 1
-#define ECX_REGNUM 2
-#define ST0_REGNUM 3
-#define ST1_REGNUM 4
-#define EBX_REGNUM 5
-#define ESI_REGNUM 6
-#define EDI_REGNUM 7
-#define ST2_REGNUM 8
-#define ST3_REGNUM 9
-
-#define ST4_REGNUM 10
-#define ST5_REGNUM 11
-#define ST6_REGNUM 12
-#define ST7_REGNUM 13
-
-#define FP1_REGNUM 18 /* first 1167 register */
-/* Get %fp2 - %fp31 by addition, since they are contiguous */
-
-#undef SP_REGNUM
-#define SP_REGNUM 14 /* (usp) Contains address of top of stack */
-#define ESP_REGNUM 14
-#undef FP_REGNUM
-#define FP_REGNUM 15 /* (ebp) Contains address of executing stack frame */
-#define EBP_REGNUM 15
-#undef PC_REGNUM
-#define PC_REGNUM 16 /* (eip) Contains program counter */
-#define EIP_REGNUM 16
-#undef PS_REGNUM
-#define PS_REGNUM 17 /* (ps) Contains processor status */
-#define EFLAGS_REGNUM 17
-
-/*
- * Following macro translates i386 opcode register numbers to Symmetry
- * register numbers. This is used by i386_frame_find_saved_regs.
- *
- * %eax %ecx %edx %ebx %esp %ebp %esi %edi
- * i386 0 1 2 3 4 5 6 7
- * Symmetry 0 2 1 5 14 15 6 7
- *
- */
-#define I386_REGNO_TO_SYMMETRY(n) \
-((n)==0?0 :(n)==1?2 :(n)==2?1 :(n)==3?5 :(n)==4?14 :(n)==5?15 :(n))
-
-/* The magic numbers below are offsets into u_ar0 in the user struct.
- * They live in <machine/reg.h>. Gdb calls this macro with blockend
- * holding u.u_ar0 - KERNEL_U_ADDR. Only the registers listed are
- * saved in the u area (along with a few others that aren't useful
- * here. See <machine/reg.h>).
- */
-
-#define REGISTER_U_ADDR(addr, blockend, regno) \
-{ struct user foo; /* needed for finding fpu regs */ \
-switch (regno) { \
- case 0: \
- addr = blockend + EAX * sizeof(int); break; \
- case 1: \
- addr = blockend + EDX * sizeof(int); break; \
- case 2: \
- addr = blockend + ECX * sizeof(int); break; \
- case 3: /* st(0) */ \
- addr = ((int)&foo.u_fpusave.fpu_stack[0][0] - (int)&foo); \
- break; \
- case 4: /* st(1) */ \
- addr = ((int) &foo.u_fpusave.fpu_stack[1][0] - (int)&foo); \
- break; \
- case 5: \
- addr = blockend + EBX * sizeof(int); break; \
- case 6: \
- addr = blockend + ESI * sizeof(int); break; \
- case 7: \
- addr = blockend + EDI * sizeof(int); break; \
- case 8: /* st(2) */ \
- addr = ((int) &foo.u_fpusave.fpu_stack[2][0] - (int)&foo); \
- break; \
- case 9: /* st(3) */ \
- addr = ((int) &foo.u_fpusave.fpu_stack[3][0] - (int)&foo); \
- break; \
- case 10: /* st(4) */ \
- addr = ((int) &foo.u_fpusave.fpu_stack[4][0] - (int)&foo); \
- break; \
- case 11: /* st(5) */ \
- addr = ((int) &foo.u_fpusave.fpu_stack[5][0] - (int)&foo); \
- break; \
- case 12: /* st(6) */ \
- addr = ((int) &foo.u_fpusave.fpu_stack[6][0] - (int)&foo); \
- break; \
- case 13: /* st(7) */ \
- addr = ((int) &foo.u_fpusave.fpu_stack[7][0] - (int)&foo); \
- break; \
- case 14: \
- addr = blockend + ESP * sizeof(int); break; \
- case 15: \
- addr = blockend + EBP * sizeof(int); break; \
- case 16: \
- addr = blockend + EIP * sizeof(int); break; \
- case 17: \
- addr = blockend + FLAGS * sizeof(int); break; \
- case 18: /* fp1 */ \
- case 19: /* fp2 */ \
- case 20: /* fp3 */ \
- case 21: /* fp4 */ \
- case 22: /* fp5 */ \
- case 23: /* fp6 */ \
- case 24: /* fp7 */ \
- case 25: /* fp8 */ \
- case 26: /* fp9 */ \
- case 27: /* fp10 */ \
- case 28: /* fp11 */ \
- case 29: /* fp12 */ \
- case 30: /* fp13 */ \
- case 31: /* fp14 */ \
- case 32: /* fp15 */ \
- case 33: /* fp16 */ \
- case 34: /* fp17 */ \
- case 35: /* fp18 */ \
- case 36: /* fp19 */ \
- case 37: /* fp20 */ \
- case 38: /* fp21 */ \
- case 39: /* fp22 */ \
- case 40: /* fp23 */ \
- case 41: /* fp24 */ \
- case 42: /* fp25 */ \
- case 43: /* fp26 */ \
- case 44: /* fp27 */ \
- case 45: /* fp28 */ \
- case 46: /* fp29 */ \
- case 47: /* fp30 */ \
- case 48: /* fp31 */ \
- addr = ((int) &foo.u_fpasave.fpa_regs[(regno)-18] - (int)&foo); \
- } \
-}
-
-/* Total amount of space needed to store our copies of the machine's
- register state, the array `registers'. 10 i*86 registers, 8 i387
- registers, and 31 Weitek 1167 registers */
-
-#undef REGISTER_BYTES
-#define REGISTER_BYTES ((10 * 4) + (8 * 10) + (31 * 4))
-
-/* Nonzero if register N requires conversion
- from raw format to virtual format. */
-
-#undef REGISTER_CONVERTIBLE
-#define REGISTER_CONVERTIBLE(N) \
-(((N) < 3) ? 0 : \
-((N) < 5) ? 1 : \
-((N) < 8) ? 0 : \
-((N) < 14) ? 1 : \
- 0)
-
-#include "floatformat.h"
-
-/* Convert data from raw format for register REGNUM in buffer FROM
- to virtual format with type TYPE in buffer TO. */
-
-#undef REGISTER_CONVERT_TO_VIRTUAL
-#define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \
-{ \
- DOUBLEST val; \
- floatformat_to_doublest (&floatformat_i387_ext, (FROM), &val); \
- store_floating ((TO), TYPE_LENGTH (TYPE), val); \
-}
-
-/* Convert data from virtual format with type TYPE in buffer FROM
- to raw format for register REGNUM in buffer TO. */
-
-#undef REGISTER_CONVERT_TO_RAW
-#define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \
-{ \
- DOUBLEST val = extract_floating ((FROM), TYPE_LENGTH (TYPE)); \
- floatformat_from_doublest (&floatformat_i387_ext, &val, (TO)); \
-}
-
-/* Return the GDB type object for the "standard" data type
- of data in register N. */
-
-#undef REGISTER_VIRTUAL_TYPE
-#define REGISTER_VIRTUAL_TYPE(N) \
-((N < 3) ? builtin_type_int : \
-(N < 5) ? builtin_type_double : \
-(N < 8) ? builtin_type_int : \
-(N < 14) ? builtin_type_double : \
- builtin_type_int)
-
-/* Store the address of the place in which to copy the structure the
- subroutine will return. This is called from call_function.
- Native cc passes the address in eax, gcc (up to version 2.5.8)
- passes it on the stack. gcc should be fixed in future versions to
- adopt native cc conventions. */
-
-#undef DEPRECATED_PUSH_ARGUMENTS
-#undef STORE_STRUCT_RETURN
-#define STORE_STRUCT_RETURN(ADDR, SP) write_register(0, (ADDR))
-
-/* Extract from an array REGBUF containing the (raw) register state
- a function return value of type TYPE, and copy that, in virtual format,
- into VALBUF. */
-
-#undef DEPRECATED_EXTRACT_RETURN_VALUE
-#define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
- symmetry_extract_return_value(TYPE, REGBUF, VALBUF)
-
-/* The following redefines make backtracing through sigtramp work.
- They manufacture a fake sigtramp frame and obtain the saved pc in sigtramp
- from the sigcontext structure which is pushed by the kernel on the
- user stack, along with a pointer to it. */
-
-#define IN_SIGTRAMP(pc, name) ((name) && STREQ ("_sigcode", name))
-
-/* Offset to saved PC in sigcontext, from <signal.h>. */
-#define SIGCONTEXT_PC_OFFSET 16
-
-#endif /* ifndef TM_SYMMETRY_H */
+// OBSOLETE /* Target machine definitions for GDB on a Sequent Symmetry under dynix 3.0,
+// OBSOLETE with Weitek 1167 and i387 support.
+// OBSOLETE
+// OBSOLETE Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 2003 Free
+// OBSOLETE Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE Symmetry version by Jay Vosburgh (fubar@sequent.com).
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #ifndef TM_SYMMETRY_H
+// OBSOLETE #define TM_SYMMETRY_H 1
+// OBSOLETE
+// OBSOLETE #include "regcache.h"
+// OBSOLETE #include "doublest.h"
+// OBSOLETE
+// OBSOLETE /* I don't know if this will work for cross-debugging, even if you do get
+// OBSOLETE a copy of the right include file. */
+// OBSOLETE #include <machine/reg.h>
+// OBSOLETE
+// OBSOLETE #include "i386/tm-i386.h"
+// OBSOLETE
+// OBSOLETE /* Amount PC must be decremented by after a breakpoint. This is often the
+// OBSOLETE number of bytes in BREAKPOINT but not always (such as now). */
+// OBSOLETE
+// OBSOLETE #undef DECR_PC_AFTER_BREAK
+// OBSOLETE #define DECR_PC_AFTER_BREAK 0
+// OBSOLETE
+// OBSOLETE /* Number of machine registers */
+// OBSOLETE
+// OBSOLETE #undef NUM_REGS
+// OBSOLETE #define NUM_REGS 49
+// OBSOLETE
+// OBSOLETE /* Initializer for an array of names of registers.
+// OBSOLETE There should be NUM_REGS strings in this initializer. */
+// OBSOLETE
+// OBSOLETE /* Initializer for an array of names of registers. There should be at least
+// OBSOLETE NUM_REGS strings in this initializer. Any excess ones are simply ignored.
+// OBSOLETE Symmetry registers are in this weird order to match the register numbers
+// OBSOLETE in the symbol table entries. If you change the order, things will probably
+// OBSOLETE break mysteriously for no apparent reason. Also note that the st(0)...
+// OBSOLETE st(7) 387 registers are represented as st0...st7. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_NAME
+// OBSOLETE #define REGISTER_NAMES { "eax", "edx", "ecx", "st0", "st1", \
+// OBSOLETE "ebx", "esi", "edi", "st2", "st3", \
+// OBSOLETE "st4", "st5", "st6", "st7", "esp", \
+// OBSOLETE "ebp", "eip", "eflags","fp1", "fp2", \
+// OBSOLETE "fp3", "fp4", "fp5", "fp6", "fp7", \
+// OBSOLETE "fp8", "fp9", "fp10", "fp11", "fp12", \
+// OBSOLETE "fp13", "fp14", "fp15", "fp16", "fp17", \
+// OBSOLETE "fp18", "fp19", "fp20", "fp21", "fp22", \
+// OBSOLETE "fp23", "fp24", "fp25", "fp26", "fp27", \
+// OBSOLETE "fp28", "fp29", "fp30", "fp31" }
+// OBSOLETE
+// OBSOLETE /* Register numbers of various important registers.
+// OBSOLETE Note that some of these values are "real" register numbers,
+// OBSOLETE and correspond to the general registers of the machine,
+// OBSOLETE and some are "phony" register numbers which are too large
+// OBSOLETE to be actual register numbers as far as the user is concerned
+// OBSOLETE but do serve to get the desired values when passed to read_register. */
+// OBSOLETE
+// OBSOLETE #define EAX_REGNUM 0
+// OBSOLETE #define EDX_REGNUM 1
+// OBSOLETE #define ECX_REGNUM 2
+// OBSOLETE #define ST0_REGNUM 3
+// OBSOLETE #define ST1_REGNUM 4
+// OBSOLETE #define EBX_REGNUM 5
+// OBSOLETE #define ESI_REGNUM 6
+// OBSOLETE #define EDI_REGNUM 7
+// OBSOLETE #define ST2_REGNUM 8
+// OBSOLETE #define ST3_REGNUM 9
+// OBSOLETE
+// OBSOLETE #define ST4_REGNUM 10
+// OBSOLETE #define ST5_REGNUM 11
+// OBSOLETE #define ST6_REGNUM 12
+// OBSOLETE #define ST7_REGNUM 13
+// OBSOLETE
+// OBSOLETE #define FP1_REGNUM 18 /* first 1167 register */
+// OBSOLETE /* Get %fp2 - %fp31 by addition, since they are contiguous */
+// OBSOLETE
+// OBSOLETE #undef SP_REGNUM
+// OBSOLETE #define SP_REGNUM 14 /* (usp) Contains address of top of stack */
+// OBSOLETE #define ESP_REGNUM 14
+// OBSOLETE #undef FP_REGNUM
+// OBSOLETE #define FP_REGNUM 15 /* (ebp) Contains address of executing stack frame */
+// OBSOLETE #define EBP_REGNUM 15
+// OBSOLETE #undef PC_REGNUM
+// OBSOLETE #define PC_REGNUM 16 /* (eip) Contains program counter */
+// OBSOLETE #define EIP_REGNUM 16
+// OBSOLETE #undef PS_REGNUM
+// OBSOLETE #define PS_REGNUM 17 /* (ps) Contains processor status */
+// OBSOLETE #define EFLAGS_REGNUM 17
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Following macro translates i386 opcode register numbers to Symmetry
+// OBSOLETE * register numbers. This is used by i386_frame_find_saved_regs.
+// OBSOLETE *
+// OBSOLETE * %eax %ecx %edx %ebx %esp %ebp %esi %edi
+// OBSOLETE * i386 0 1 2 3 4 5 6 7
+// OBSOLETE * Symmetry 0 2 1 5 14 15 6 7
+// OBSOLETE *
+// OBSOLETE */
+// OBSOLETE #define I386_REGNO_TO_SYMMETRY(n) \
+// OBSOLETE ((n)==0?0 :(n)==1?2 :(n)==2?1 :(n)==3?5 :(n)==4?14 :(n)==5?15 :(n))
+// OBSOLETE
+// OBSOLETE /* The magic numbers below are offsets into u_ar0 in the user struct.
+// OBSOLETE * They live in <machine/reg.h>. Gdb calls this macro with blockend
+// OBSOLETE * holding u.u_ar0 - KERNEL_U_ADDR. Only the registers listed are
+// OBSOLETE * saved in the u area (along with a few others that aren't useful
+// OBSOLETE * here. See <machine/reg.h>).
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE #define REGISTER_U_ADDR(addr, blockend, regno) \
+// OBSOLETE { struct user foo; /* needed for finding fpu regs */ \
+// OBSOLETE switch (regno) { \
+// OBSOLETE case 0: \
+// OBSOLETE addr = blockend + EAX * sizeof(int); break; \
+// OBSOLETE case 1: \
+// OBSOLETE addr = blockend + EDX * sizeof(int); break; \
+// OBSOLETE case 2: \
+// OBSOLETE addr = blockend + ECX * sizeof(int); break; \
+// OBSOLETE case 3: /* st(0) */ \
+// OBSOLETE addr = ((int)&foo.u_fpusave.fpu_stack[0][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 4: /* st(1) */ \
+// OBSOLETE addr = ((int) &foo.u_fpusave.fpu_stack[1][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 5: \
+// OBSOLETE addr = blockend + EBX * sizeof(int); break; \
+// OBSOLETE case 6: \
+// OBSOLETE addr = blockend + ESI * sizeof(int); break; \
+// OBSOLETE case 7: \
+// OBSOLETE addr = blockend + EDI * sizeof(int); break; \
+// OBSOLETE case 8: /* st(2) */ \
+// OBSOLETE addr = ((int) &foo.u_fpusave.fpu_stack[2][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 9: /* st(3) */ \
+// OBSOLETE addr = ((int) &foo.u_fpusave.fpu_stack[3][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 10: /* st(4) */ \
+// OBSOLETE addr = ((int) &foo.u_fpusave.fpu_stack[4][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 11: /* st(5) */ \
+// OBSOLETE addr = ((int) &foo.u_fpusave.fpu_stack[5][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 12: /* st(6) */ \
+// OBSOLETE addr = ((int) &foo.u_fpusave.fpu_stack[6][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 13: /* st(7) */ \
+// OBSOLETE addr = ((int) &foo.u_fpusave.fpu_stack[7][0] - (int)&foo); \
+// OBSOLETE break; \
+// OBSOLETE case 14: \
+// OBSOLETE addr = blockend + ESP * sizeof(int); break; \
+// OBSOLETE case 15: \
+// OBSOLETE addr = blockend + EBP * sizeof(int); break; \
+// OBSOLETE case 16: \
+// OBSOLETE addr = blockend + EIP * sizeof(int); break; \
+// OBSOLETE case 17: \
+// OBSOLETE addr = blockend + FLAGS * sizeof(int); break; \
+// OBSOLETE case 18: /* fp1 */ \
+// OBSOLETE case 19: /* fp2 */ \
+// OBSOLETE case 20: /* fp3 */ \
+// OBSOLETE case 21: /* fp4 */ \
+// OBSOLETE case 22: /* fp5 */ \
+// OBSOLETE case 23: /* fp6 */ \
+// OBSOLETE case 24: /* fp7 */ \
+// OBSOLETE case 25: /* fp8 */ \
+// OBSOLETE case 26: /* fp9 */ \
+// OBSOLETE case 27: /* fp10 */ \
+// OBSOLETE case 28: /* fp11 */ \
+// OBSOLETE case 29: /* fp12 */ \
+// OBSOLETE case 30: /* fp13 */ \
+// OBSOLETE case 31: /* fp14 */ \
+// OBSOLETE case 32: /* fp15 */ \
+// OBSOLETE case 33: /* fp16 */ \
+// OBSOLETE case 34: /* fp17 */ \
+// OBSOLETE case 35: /* fp18 */ \
+// OBSOLETE case 36: /* fp19 */ \
+// OBSOLETE case 37: /* fp20 */ \
+// OBSOLETE case 38: /* fp21 */ \
+// OBSOLETE case 39: /* fp22 */ \
+// OBSOLETE case 40: /* fp23 */ \
+// OBSOLETE case 41: /* fp24 */ \
+// OBSOLETE case 42: /* fp25 */ \
+// OBSOLETE case 43: /* fp26 */ \
+// OBSOLETE case 44: /* fp27 */ \
+// OBSOLETE case 45: /* fp28 */ \
+// OBSOLETE case 46: /* fp29 */ \
+// OBSOLETE case 47: /* fp30 */ \
+// OBSOLETE case 48: /* fp31 */ \
+// OBSOLETE addr = ((int) &foo.u_fpasave.fpa_regs[(regno)-18] - (int)&foo); \
+// OBSOLETE } \
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Total amount of space needed to store our copies of the machine's
+// OBSOLETE register state, the array `registers'. 10 i*86 registers, 8 i387
+// OBSOLETE registers, and 31 Weitek 1167 registers */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_BYTES
+// OBSOLETE #define REGISTER_BYTES ((10 * 4) + (8 * 10) + (31 * 4))
+// OBSOLETE
+// OBSOLETE /* Nonzero if register N requires conversion
+// OBSOLETE from raw format to virtual format. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_CONVERTIBLE
+// OBSOLETE #define REGISTER_CONVERTIBLE(N) \
+// OBSOLETE (((N) < 3) ? 0 : \
+// OBSOLETE ((N) < 5) ? 1 : \
+// OBSOLETE ((N) < 8) ? 0 : \
+// OBSOLETE ((N) < 14) ? 1 : \
+// OBSOLETE 0)
+// OBSOLETE
+// OBSOLETE #include "floatformat.h"
+// OBSOLETE
+// OBSOLETE /* Convert data from raw format for register REGNUM in buffer FROM
+// OBSOLETE to virtual format with type TYPE in buffer TO. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_CONVERT_TO_VIRTUAL
+// OBSOLETE #define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \
+// OBSOLETE { \
+// OBSOLETE DOUBLEST val; \
+// OBSOLETE floatformat_to_doublest (&floatformat_i387_ext, (FROM), &val); \
+// OBSOLETE deprecated_store_floating ((TO), TYPE_LENGTH (TYPE), val); \
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Convert data from virtual format with type TYPE in buffer FROM
+// OBSOLETE to raw format for register REGNUM in buffer TO. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_CONVERT_TO_RAW
+// OBSOLETE #define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \
+// OBSOLETE { \
+// OBSOLETE DOUBLEST val = deprecated_extract_floating ((FROM), TYPE_LENGTH (TYPE)); \
+// OBSOLETE floatformat_from_doublest (&floatformat_i387_ext, &val, (TO)); \
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Return the GDB type object for the "standard" data type
+// OBSOLETE of data in register N. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_VIRTUAL_TYPE
+// OBSOLETE #define REGISTER_VIRTUAL_TYPE(N) \
+// OBSOLETE ((N < 3) ? builtin_type_int : \
+// OBSOLETE (N < 5) ? builtin_type_double : \
+// OBSOLETE (N < 8) ? builtin_type_int : \
+// OBSOLETE (N < 14) ? builtin_type_double : \
+// OBSOLETE builtin_type_int)
+// OBSOLETE
+// OBSOLETE /* Store the address of the place in which to copy the structure the
+// OBSOLETE subroutine will return. This is called from call_function.
+// OBSOLETE Native cc passes the address in eax, gcc (up to version 2.5.8)
+// OBSOLETE passes it on the stack. gcc should be fixed in future versions to
+// OBSOLETE adopt native cc conventions. */
+// OBSOLETE
+// OBSOLETE #undef DEPRECATED_PUSH_ARGUMENTS
+// OBSOLETE #undef STORE_STRUCT_RETURN
+// OBSOLETE #define STORE_STRUCT_RETURN(ADDR, SP) write_register(0, (ADDR))
+// OBSOLETE
+// OBSOLETE /* Extract from an array REGBUF containing the (raw) register state
+// OBSOLETE a function return value of type TYPE, and copy that, in virtual format,
+// OBSOLETE into VALBUF. */
+// OBSOLETE
+// OBSOLETE #undef DEPRECATED_EXTRACT_RETURN_VALUE
+// OBSOLETE #define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
+// OBSOLETE symmetry_extract_return_value(TYPE, REGBUF, VALBUF)
+// OBSOLETE
+// OBSOLETE /* The following redefines make backtracing through sigtramp work.
+// OBSOLETE They manufacture a fake sigtramp frame and obtain the saved pc in sigtramp
+// OBSOLETE from the sigcontext structure which is pushed by the kernel on the
+// OBSOLETE user stack, along with a pointer to it. */
+// OBSOLETE
+// OBSOLETE #define IN_SIGTRAMP(pc, name) ((name) && STREQ ("_sigcode", name))
+// OBSOLETE
+// OBSOLETE /* Offset to saved PC in sigcontext, from <signal.h>. */
+// OBSOLETE #define SIGCONTEXT_PC_OFFSET 16
+// OBSOLETE
+// OBSOLETE #endif /* ifndef TM_SYMMETRY_H */
-/* Definitions to make GDB run on a Sequent Symmetry under ptx, with
- Weitek 1167 and i387 support.
- Copyright 1986, 1987, 1989, 1992, 1993, 1994, 1995
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* Symmetry version by Jay Vosburgh (fubar@sequent.com) */
-
-#ifdef _SEQUENT_PTX4_
-#include "config/xm-sysv4.h"
-#endif /* _SEQUENT_PTX4_ */
-
-/* This machine doesn't have the siginterrupt call. */
-#define NO_SIGINTERRUPT
-
-#define HAVE_WAIT_STRUCT
-
-#undef HAVE_TERMIO
-#define HAVE_TERMIOS
-#define USG
-
-#define USE_O_NOCTTY
+// OBSOLETE /* Definitions to make GDB run on a Sequent Symmetry under ptx, with
+// OBSOLETE Weitek 1167 and i387 support.
+// OBSOLETE Copyright 1986, 1987, 1989, 1992, 1993, 1994, 1995
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /* Symmetry version by Jay Vosburgh (fubar@sequent.com) */
+// OBSOLETE
+// OBSOLETE #ifdef _SEQUENT_PTX4_
+// OBSOLETE #include "config/xm-sysv4.h"
+// OBSOLETE #endif /* _SEQUENT_PTX4_ */
+// OBSOLETE
+// OBSOLETE /* This machine doesn't have the siginterrupt call. */
+// OBSOLETE #define NO_SIGINTERRUPT
+// OBSOLETE
+// OBSOLETE #define HAVE_WAIT_STRUCT
+// OBSOLETE
+// OBSOLETE #undef HAVE_TERMIO
+// OBSOLETE #define HAVE_TERMIOS
+// OBSOLETE #define USG
+// OBSOLETE
+// OBSOLETE #define USE_O_NOCTTY
-/* Definitions to make GDB run on a Sequent Symmetry under ptx, with
- Weitek 1167 and i387 support.
- Copyright 1986, 1987, 1989, 1992, 1993, 1994
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* Symmetry version by Jay Vosburgh (fubar@sequent.com) */
-
-#include "config/xm-sysv4.h"
-
-#include "i386/xm-ptx.h"
+// OBSOLETE /* Definitions to make GDB run on a Sequent Symmetry under ptx, with
+// OBSOLETE Weitek 1167 and i387 support.
+// OBSOLETE Copyright 1986, 1987, 1989, 1992, 1993, 1994
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /* Symmetry version by Jay Vosburgh (fubar@sequent.com) */
+// OBSOLETE
+// OBSOLETE #include "config/xm-sysv4.h"
+// OBSOLETE
+// OBSOLETE #include "i386/xm-ptx.h"
-/* Definitions to make GDB run on a Sequent Symmetry under
- dynix 3.1, with Weitek 1167 and i387 support.
- Copyright 1986, 1987, 1989, 1992, 1993, 1994
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* Symmetry version by Jay Vosburgh (fubar@sequent.com) */
-
-/* This machine doesn't have the siginterrupt call. */
-#define NO_SIGINTERRUPT
-
-#define HAVE_WAIT_STRUCT
+// OBSOLETE /* Definitions to make GDB run on a Sequent Symmetry under
+// OBSOLETE dynix 3.1, with Weitek 1167 and i387 support.
+// OBSOLETE Copyright 1986, 1987, 1989, 1992, 1993, 1994
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /* Symmetry version by Jay Vosburgh (fubar@sequent.com) */
+// OBSOLETE
+// OBSOLETE /* This machine doesn't have the siginterrupt call. */
+// OBSOLETE #define NO_SIGINTERRUPT
+// OBSOLETE
+// OBSOLETE #define HAVE_WAIT_STRUCT
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct frame_info;
+
#include "regcache.h"
/* Define BPT_VECTOR if it is different than the default.
-# Host: Little endian MIPS machine such as pmax
-# running Mach 3.0 operating system
-
-NATDEPFILES= mipsm3-nat.o m3-nat.o core-aout.o
-XM_FILE= xm-mipsm3.h
-NAT_FILE= ../nm-m3.h
+# OBSOLETE # Host: Little endian MIPS machine such as pmax
+# OBSOLETE # running Mach 3.0 operating system
+# OBSOLETE
+# OBSOLETE NATDEPFILES= mipsm3-nat.o m3-nat.o core-aout.o
+# OBSOLETE XM_FILE= xm-mipsm3.h
+# OBSOLETE NAT_FILE= ../nm-m3.h
-# Target: Little-endian MIPS machine such as pmax
-# running Mach 3.0 operating system
-TDEPFILES= mips-tdep.o
-TM_FILE= tm-mipsm3.h
+# OBSOLETE # Target: Little-endian MIPS machine such as pmax
+# OBSOLETE # running Mach 3.0 operating system
+# OBSOLETE TDEPFILES= mips-tdep.o
+# OBSOLETE TM_FILE= tm-mipsm3.h
-/* Definitions to make GDB run on a mips box under Mach 3.0
- Copyright 1992, 1993, 1998 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* Mach specific definitions for little endian mips (e.g. pmax)
- * running Mach 3.0
- *
- * Author: Jukka Virtanen <jtv@hut.fi>
- */
-
-/* Include common definitions for Mach3 systems */
-#include "config/nm-m3.h"
-
-/* Define offsets to access CPROC stack when it does not have
- * a kernel thread.
- */
-
-/* From mk/user/threads/mips/csw.s */
-#define SAVED_FP (12*4)
-#define SAVED_PC (13*4)
-#define SAVED_BYTES (14*4)
-
-/* Using these, define our offsets to items strored in
- * cproc_switch in csw.s
- */
-#define MACHINE_CPROC_SP_OFFSET SAVED_BYTES
-#define MACHINE_CPROC_PC_OFFSET SAVED_PC
-#define MACHINE_CPROC_FP_OFFSET SAVED_FP
-
-/* Thread flavors used in setting the Trace state.
-
- * In <mach/machine/thread_status.h>
- */
-#define TRACE_FLAVOR MIPS_EXC_STATE
-#define TRACE_FLAVOR_SIZE MIPS_EXC_STATE_COUNT
-#define TRACE_SET(x,state) ((struct mips_exc_state *)state)->cause = EXC_SST;
-#define TRACE_CLEAR(x,state) 0
-
-/* Mach supports attach/detach */
-#define ATTACH_DETACH 1
-
-#include "mips/tm-mips.h"
-
-/* Address of end of user stack space.
- * for MACH, see <machine/vmparam.h>
- */
-#undef STACK_END_ADDR
-#define STACK_END_ADDR USRSTACK
-
-/* Output registers in tabular format */
-#define TABULAR_REGISTER_OUTPUT
+// OBSOLETE /* Definitions to make GDB run on a mips box under Mach 3.0
+// OBSOLETE Copyright 1992, 1993, 1998 Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /* Mach specific definitions for little endian mips (e.g. pmax)
+// OBSOLETE * running Mach 3.0
+// OBSOLETE *
+// OBSOLETE * Author: Jukka Virtanen <jtv@hut.fi>
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE /* Include common definitions for Mach3 systems */
+// OBSOLETE #include "config/nm-m3.h"
+// OBSOLETE
+// OBSOLETE /* Define offsets to access CPROC stack when it does not have
+// OBSOLETE * a kernel thread.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE /* From mk/user/threads/mips/csw.s */
+// OBSOLETE #define SAVED_FP (12*4)
+// OBSOLETE #define SAVED_PC (13*4)
+// OBSOLETE #define SAVED_BYTES (14*4)
+// OBSOLETE
+// OBSOLETE /* Using these, define our offsets to items strored in
+// OBSOLETE * cproc_switch in csw.s
+// OBSOLETE */
+// OBSOLETE #define MACHINE_CPROC_SP_OFFSET SAVED_BYTES
+// OBSOLETE #define MACHINE_CPROC_PC_OFFSET SAVED_PC
+// OBSOLETE #define MACHINE_CPROC_FP_OFFSET SAVED_FP
+// OBSOLETE
+// OBSOLETE /* Thread flavors used in setting the Trace state.
+// OBSOLETE
+// OBSOLETE * In <mach/machine/thread_status.h>
+// OBSOLETE */
+// OBSOLETE #define TRACE_FLAVOR MIPS_EXC_STATE
+// OBSOLETE #define TRACE_FLAVOR_SIZE MIPS_EXC_STATE_COUNT
+// OBSOLETE #define TRACE_SET(x,state) ((struct mips_exc_state *)state)->cause = EXC_SST;
+// OBSOLETE #define TRACE_CLEAR(x,state) 0
+// OBSOLETE
+// OBSOLETE /* Mach supports attach/detach */
+// OBSOLETE #define ATTACH_DETACH 1
+// OBSOLETE
+// OBSOLETE #include "mips/tm-mips.h"
+// OBSOLETE
+// OBSOLETE /* Address of end of user stack space.
+// OBSOLETE * for MACH, see <machine/vmparam.h>
+// OBSOLETE */
+// OBSOLETE #undef STACK_END_ADDR
+// OBSOLETE #define STACK_END_ADDR USRSTACK
+// OBSOLETE
+// OBSOLETE /* Output registers in tabular format */
+// OBSOLETE #define TABULAR_REGISTER_OUTPUT
-/* Definitions to make GDB run on a mips box under 4.3bsd.
- Copyright 1986, 1987, 1989, 1993 Free Software Foundation, Inc.
- Contributed by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
- and by Alessandro Forin(af@cs.cmu.edu) at CMU
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#define KERNEL_U_ADDR 0 /* Not needed. */
-
-/* Only used for core files on DECstations. */
-
-#define REGISTER_U_ADDR(addr, blockend, regno) \
- if (regno < 38) addr = (NBPG*UPAGES) + (regno - 38)*sizeof(int);\
- else addr = 0; /* ..somewhere in the pcb */
+// OBSOLETE /* Definitions to make GDB run on a mips box under 4.3bsd.
+// OBSOLETE Copyright 1986, 1987, 1989, 1993 Free Software Foundation, Inc.
+// OBSOLETE Contributed by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
+// OBSOLETE and by Alessandro Forin(af@cs.cmu.edu) at CMU
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #define KERNEL_U_ADDR 0 /* Not needed. */
+// OBSOLETE
+// OBSOLETE /* Only used for core files on DECstations. */
+// OBSOLETE
+// OBSOLETE #define REGISTER_U_ADDR(addr, blockend, regno) \
+// OBSOLETE if (regno < 38) addr = (NBPG*UPAGES) + (regno - 38)*sizeof(int);\
+// OBSOLETE else addr = 0; /* ..somewhere in the pcb */
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct target_ops;
+
/* GNU/Linux is SVR4-ish but its /proc file system isn't. */
#undef USE_PROC_FS
#ifndef NM_LYNX_H
#define NM_LYNX_H
+struct target_waitstatus;
+
#include <sys/conf.h>
#include <sys/kernel.h>
/* sys/kernel.h should define this, but doesn't always, sigh. */
-/* Mach 3.0 common definitions and global vars.
-
- Copyright 1992, 1993, 1994, 1996 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#ifndef NM_M3_H
-#define NM_M3_H
-
-#include <mach.h>
-#include "regcache.h"
-
-/* Mach3 doesn't declare errno in <errno.h>. */
-extern int errno;
-
-/* Task port of our debugged inferior. */
-
-extern task_t inferior_task;
-
-/* Thread port of the current thread in the inferior. */
-
-extern thread_t current_thread;
-
-/* If nonzero, we must suspend/abort && resume threads
- * when setting or getting the state.
- */
-extern int must_suspend_thread;
-
-#define PREPARE_TO_PROCEED(select_it) mach3_prepare_to_proceed(select_it)
-
-/* Try to get the privileged host port for authentication to machid
-
- * If you can get this, you may debug anything on this host.
- *
- * If you can't, gdb gives it's own task port as the
- * authentication port
- */
-#define mach_privileged_host_port() task_by_pid(-1)
-
-/*
- * This is the MIG ID number of the emulator/server bsd_execve() RPC call.
- *
- * It SHOULD never change, but if it does, gdb `run'
- * command won't work until you fix this define.
- *
- */
-#define MIG_EXEC_SYSCALL_ID 101000
-
-/* If our_message_port gets a msg with this ID,
- * GDB suspends it's inferior and enters command level.
- * (Useful at least if ^C does not work)
- */
-#define GDB_MESSAGE_ID_STOP 0x41151
-
-/* wait3 WNOHANG is defined in <sys/wait.h> but
- * for some reason gdb does not want to include
- * that file.
- *
- * If your system defines WNOHANG differently, this has to be changed.
- */
-#define WNOHANG 1
-
-/* Before storing, we need to read all the registers. */
-
-#define CHILD_PREPARE_TO_STORE() deprecated_read_register_bytes (0, NULL, REGISTER_BYTES)
-
-/* Check if the inferior exists */
-#define MACH_ERROR_NO_INFERIOR \
- do if (!MACH_PORT_VALID (inferior_task)) \
- error ("Inferior task does not exist."); while(0)
-
-/* Error handler for mach calls */
-#define CHK(str,ret) \
- do if (ret != KERN_SUCCESS) \
- error ("Gdb %s [%d] %s : %s\n",__FILE__,__LINE__,str, \
- mach_error_string(ret)); while(0)
-
-/* This is from POE9 emulator/emul_stack.h
- */
-/*
- * Top of emulator stack holds link and reply port.
- */
-struct emul_stack_top
- {
- struct emul_stack_top *link;
- mach_port_t reply_port;
- };
-
-#define EMULATOR_STACK_SIZE (4096*4)
-
-#define THREAD_ALLOWED_TO_BREAK(mid) mach_thread_for_breakpoint (mid)
-
-#define THREAD_PARSE_ID(arg) mach_thread_parse_id (arg)
-
-#define THREAD_OUTPUT_ID(mid) mach_thread_output_id (mid)
-
-#define ATTACH_TO_THREAD attach_to_thread
-
-/* Don't do wait_for_inferior on attach. */
-#define ATTACH_NO_WAIT
-
-/* Do Mach 3 dependent operations when ^C or a STOP is requested */
-#define DO_QUIT() mach3_quit ()
-
-#if 0
-/* This is bogus. It is NOT OK to quit out of target_wait. */
-/* If in mach_msg() and ^C is typed set immediate_quit */
-#define REQUEST_QUIT() mach3_request_quit ()
-#endif
-
-#endif /* NM_M3_H */
+// OBSOLETE /* Mach 3.0 common definitions and global vars.
+// OBSOLETE
+// OBSOLETE Copyright 1992, 1993, 1994, 1996 Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #ifndef NM_M3_H
+// OBSOLETE #define NM_M3_H
+// OBSOLETE
+// OBSOLETE #include <mach.h>
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE /* Mach3 doesn't declare errno in <errno.h>. */
+// OBSOLETE extern int errno;
+// OBSOLETE
+// OBSOLETE /* Task port of our debugged inferior. */
+// OBSOLETE
+// OBSOLETE extern task_t inferior_task;
+// OBSOLETE
+// OBSOLETE /* Thread port of the current thread in the inferior. */
+// OBSOLETE
+// OBSOLETE extern thread_t current_thread;
+// OBSOLETE
+// OBSOLETE /* If nonzero, we must suspend/abort && resume threads
+// OBSOLETE * when setting or getting the state.
+// OBSOLETE */
+// OBSOLETE extern int must_suspend_thread;
+// OBSOLETE
+// OBSOLETE #define PREPARE_TO_PROCEED(select_it) mach3_prepare_to_proceed(select_it)
+// OBSOLETE
+// OBSOLETE /* Try to get the privileged host port for authentication to machid
+// OBSOLETE
+// OBSOLETE * If you can get this, you may debug anything on this host.
+// OBSOLETE *
+// OBSOLETE * If you can't, gdb gives it's own task port as the
+// OBSOLETE * authentication port
+// OBSOLETE */
+// OBSOLETE #define mach_privileged_host_port() task_by_pid(-1)
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * This is the MIG ID number of the emulator/server bsd_execve() RPC call.
+// OBSOLETE *
+// OBSOLETE * It SHOULD never change, but if it does, gdb `run'
+// OBSOLETE * command won't work until you fix this define.
+// OBSOLETE *
+// OBSOLETE */
+// OBSOLETE #define MIG_EXEC_SYSCALL_ID 101000
+// OBSOLETE
+// OBSOLETE /* If our_message_port gets a msg with this ID,
+// OBSOLETE * GDB suspends it's inferior and enters command level.
+// OBSOLETE * (Useful at least if ^C does not work)
+// OBSOLETE */
+// OBSOLETE #define GDB_MESSAGE_ID_STOP 0x41151
+// OBSOLETE
+// OBSOLETE /* wait3 WNOHANG is defined in <sys/wait.h> but
+// OBSOLETE * for some reason gdb does not want to include
+// OBSOLETE * that file.
+// OBSOLETE *
+// OBSOLETE * If your system defines WNOHANG differently, this has to be changed.
+// OBSOLETE */
+// OBSOLETE #define WNOHANG 1
+// OBSOLETE
+// OBSOLETE /* Before storing, we need to read all the registers. */
+// OBSOLETE
+// OBSOLETE #define CHILD_PREPARE_TO_STORE() deprecated_read_register_bytes (0, NULL, REGISTER_BYTES)
+// OBSOLETE
+// OBSOLETE /* Check if the inferior exists */
+// OBSOLETE #define MACH_ERROR_NO_INFERIOR \
+// OBSOLETE do if (!MACH_PORT_VALID (inferior_task)) \
+// OBSOLETE error ("Inferior task does not exist."); while(0)
+// OBSOLETE
+// OBSOLETE /* Error handler for mach calls */
+// OBSOLETE #define CHK(str,ret) \
+// OBSOLETE do if (ret != KERN_SUCCESS) \
+// OBSOLETE error ("Gdb %s [%d] %s : %s\n",__FILE__,__LINE__,str, \
+// OBSOLETE mach_error_string(ret)); while(0)
+// OBSOLETE
+// OBSOLETE /* This is from POE9 emulator/emul_stack.h
+// OBSOLETE */
+// OBSOLETE /*
+// OBSOLETE * Top of emulator stack holds link and reply port.
+// OBSOLETE */
+// OBSOLETE struct emul_stack_top
+// OBSOLETE {
+// OBSOLETE struct emul_stack_top *link;
+// OBSOLETE mach_port_t reply_port;
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE #define EMULATOR_STACK_SIZE (4096*4)
+// OBSOLETE
+// OBSOLETE #define THREAD_ALLOWED_TO_BREAK(mid) mach_thread_for_breakpoint (mid)
+// OBSOLETE
+// OBSOLETE #define THREAD_PARSE_ID(arg) mach_thread_parse_id (arg)
+// OBSOLETE
+// OBSOLETE #define THREAD_OUTPUT_ID(mid) mach_thread_output_id (mid)
+// OBSOLETE
+// OBSOLETE #define ATTACH_TO_THREAD attach_to_thread
+// OBSOLETE
+// OBSOLETE /* Don't do wait_for_inferior on attach. */
+// OBSOLETE #define ATTACH_NO_WAIT
+// OBSOLETE
+// OBSOLETE /* Do Mach 3 dependent operations when ^C or a STOP is requested */
+// OBSOLETE #define DO_QUIT() mach3_quit ()
+// OBSOLETE
+// OBSOLETE #if 0
+// OBSOLETE /* This is bogus. It is NOT OK to quit out of target_wait. */
+// OBSOLETE /* If in mach_msg() and ^C is typed set immediate_quit */
+// OBSOLETE #define REQUEST_QUIT() mach3_request_quit ()
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE #endif /* NM_M3_H */
#endif
#if !GDB_MULTI_ARCH
-#undef SAVED_PC_AFTER_CALL
-#define SAVED_PC_AFTER_CALL(frame) hppa_saved_pc_after_call (frame)
+#undef DEPRECATED_SAVED_PC_AFTER_CALL
+#define DEPRECATED_SAVED_PC_AFTER_CALL(frame) hppa_saved_pc_after_call (frame)
extern CORE_ADDR hppa_saved_pc_after_call (struct frame_info *);
#endif
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct frame_info;
+
/* The solib hooks are not really designed to have a list of hook
and handler routines. So until we clean up those interfaces you
either get SOM shared libraries or HP's unusual PA64 ELF shared
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct frame_info;
+
#define GDB_MULTI_ARCH 1
/* Minimum possible text address in AIX */
/* Define other aspects of the stack frame. */
#define DEPRECATED_INIT_FRAME_PC_FIRST(fromleaf, prev) \
- (fromleaf ? SAVED_PC_AFTER_CALL (prev->next) : \
+ (fromleaf ? DEPRECATED_SAVED_PC_AFTER_CALL (prev->next) : \
prev->next ? DEPRECATED_FRAME_SAVED_PC (prev->next) : read_pc ())
/* NOTE: cagney/2002-12-08: Add local declaration of
init_frame_pc_noop() because it isn't possible to include
-# Target: SPARC embedded Sparclet monitor
-TDEPFILES= sparc-tdep.o monitor.o sparclet-rom.o dsrec.o
-TM_FILE= tm-sparclet.h
+# OBSOLETE # Target: SPARC embedded Sparclet monitor
+# OBSOLETE TDEPFILES= sparc-tdep.o monitor.o sparclet-rom.o dsrec.o
+# OBSOLETE TM_FILE= tm-sparclet.h
-# Target: Fujitsu SPARClite processor
-TDEPFILES= sparc-tdep.o sparcl-tdep.o
-TM_FILE= tm-sparclite.h
-SIM_OBS = remote-sim.o
-SIM = ../sim/erc32/libsim.a
+# OBSOLETE # Target: Fujitsu SPARClite processor
+# OBSOLETE TDEPFILES= sparc-tdep.o sparcl-tdep.o
+# OBSOLETE TM_FILE= tm-sparclite.h
+# OBSOLETE SIM_OBS = remote-sim.o
+# OBSOLETE SIM = ../sim/erc32/libsim.a
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct type;
+
#define GDB_MULTI_ARCH GDB_MULTI_ARCH_PARTIAL
#ifndef GDB_TARGET_IS_SPARC64
the new frame is not set up until the new function executes
some instructions. */
-#define SAVED_PC_AFTER_CALL(FRAME) PC_ADJUST (read_register (RP_REGNUM))
+#define DEPRECATED_SAVED_PC_AFTER_CALL(FRAME) PC_ADJUST (read_register (RP_REGNUM))
/* Stack grows downward. */
extern CORE_ADDR init_frame_pc_noop (int fromleaf, struct frame_info *prev);
#define DEPRECATED_INIT_FRAME_PC(FROMLEAF, PREV) (init_frame_pc_noop (FROMLEAF, PREV))
#define DEPRECATED_INIT_FRAME_PC_FIRST(FROMLEAF, PREV) \
- ((FROMLEAF) ? SAVED_PC_AFTER_CALL ((PREV)->next) : \
+ ((FROMLEAF) ? DEPRECATED_SAVED_PC_AFTER_CALL ((PREV)->next) : \
(PREV)->next ? DEPRECATED_FRAME_SAVED_PC ((PREV)->next) : read_pc ())
/* Define other aspects of the stack frame. */
-/* Target machine definitions for GDB for an embedded SPARC.
- Copyright 1996, 1997, 2000 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#include "regcache.h"
-
-#define TARGET_SPARCLET 1 /* Still needed for non-multi-arch case */
-
-#include "sparc/tm-sparc.h"
-
-/* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
- at this time, because we have not figured out how to detect the
- sparclet target from the bfd structure. */
-
-/* Sparclet regs, for debugging purposes. */
-
-enum {
- CCSR_REGNUM = 72,
- CCPR_REGNUM = 73,
- CCCRCR_REGNUM = 74,
- CCOR_REGNUM = 75,
- CCOBR_REGNUM = 76,
- CCIBR_REGNUM = 77,
- CCIR_REGNUM = 78
-};
-
-/* Select the sparclet disassembler. Slightly different instruction set from
- the V8 sparc. */
-
-#undef TM_PRINT_INSN_MACH
-#define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclet
-
-/* overrides of tm-sparc.h */
-
-#undef TARGET_BYTE_ORDER
-
-/* Sequence of bytes for breakpoint instruction (ta 1). */
-#undef BREAKPOINT
-#define BIG_BREAKPOINT {0x91, 0xd0, 0x20, 0x01}
-#define LITTLE_BREAKPOINT {0x01, 0x20, 0xd0, 0x91}
-
-#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
-/*
- * The following defines must go away for MULTI_ARCH.
- */
-
-#undef NUM_REGS /* formerly "72" */
-/* WIN FP CPU CCP ASR AWR APSR */
-#define NUM_REGS (32 + 32 + 8 + 8 + 8/*+ 32 + 1*/)
-
-#undef REGISTER_BYTES /* formerly "(32*4 + 32*4 + 8*4)" */
-#define REGISTER_BYTES (32*4 + 32*4 + 8*4 + 8*4 + 8*4/* + 32*4 + 1*4*/)
-
-/* Initializer for an array of names of registers.
- There should be NUM_REGS strings in this initializer. */
-/* Sparclet has no fp! */
-/* Compiler maps types for floats by number, so can't
- change the numbers here. */
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
- "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", \
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
- "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", \
- \
- "", "", "", "", "", "", "", "", /* no FPU regs */ \
- "", "", "", "", "", "", "", "", \
- "", "", "", "", "", "", "", "", \
- "", "", "", "", "", "", "", "", \
- /* no CPSR, FPSR */ \
- "y", "psr", "wim", "tbr", "pc", "npc", "", "", \
- \
- "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", \
- \
- /* ASR15 ASR19 (don't display them) */ \
- "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22", \
-/* \
- "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7", \
- "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", \
- "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", \
- "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", \
- "apsr", \
- */ \
-}
-
-/* Remove FP dependant code which was defined in tm-sparc.h */
-#undef FP0_REGNUM /* Floating point register 0 */
-#undef FPS_REGNUM /* Floating point status register */
-#undef CPS_REGNUM /* Coprocessor status register */
-
-/* sparclet register numbers */
-#define CCSR_REGNUM 72
-
-#undef DEPRECATED_EXTRACT_RETURN_VALUE
-#define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
- { \
- memcpy ((VALBUF), \
- (char *)(REGBUF) + REGISTER_RAW_SIZE (O0_REGNUM) * 8 + \
- (TYPE_LENGTH(TYPE) >= REGISTER_RAW_SIZE (O0_REGNUM) \
- ? 0 : REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH(TYPE)), \
- TYPE_LENGTH(TYPE)); \
- }
-#undef DEPRECATED_STORE_RETURN_VALUE
-#define DEPRECATED_STORE_RETURN_VALUE(TYPE,VALBUF) \
- { \
- /* Other values are returned in register %o0. */ \
- deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), (VALBUF), \
- TYPE_LENGTH (TYPE)); \
- }
-
-#endif /* GDB_MULTI_ARCH */
-
-extern void sparclet_do_registers_info (int regnum, int all);
-#undef DEPRECATED_DO_REGISTERS_INFO
-#define DEPRECATED_DO_REGISTERS_INFO(REGNUM,ALL) sparclet_do_registers_info (REGNUM, ALL)
-
-
-/* Offsets into jmp_buf. Not defined by Sun, but at least documented in a
- comment in <machine/setjmp.h>! */
-
-#define JB_ELEMENT_SIZE 4 /* Size of each element in jmp_buf */
-
-#define JB_ONSSTACK 0
-#define JB_SIGMASK 1
-#define JB_SP 2
-#define JB_PC 3
-#define JB_NPC 4
-#define JB_PSR 5
-#define JB_G1 6
-#define JB_O0 7
-#define JB_WBCNT 8
-
-/* Figure out where the longjmp will land. We expect that we have just entered
- longjmp and haven't yet setup the stack frame, so the args are still in the
- output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
- extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
- This routine returns true on success */
-
-extern int get_longjmp_target (CORE_ADDR *);
-
-#define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)
+// OBSOLETE /* Target machine definitions for GDB for an embedded SPARC.
+// OBSOLETE Copyright 1996, 1997, 2000 Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE #define TARGET_SPARCLET 1 /* Still needed for non-multi-arch case */
+// OBSOLETE
+// OBSOLETE #include "sparc/tm-sparc.h"
+// OBSOLETE
+// OBSOLETE /* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
+// OBSOLETE at this time, because we have not figured out how to detect the
+// OBSOLETE sparclet target from the bfd structure. */
+// OBSOLETE
+// OBSOLETE /* Sparclet regs, for debugging purposes. */
+// OBSOLETE
+// OBSOLETE enum {
+// OBSOLETE CCSR_REGNUM = 72,
+// OBSOLETE CCPR_REGNUM = 73,
+// OBSOLETE CCCRCR_REGNUM = 74,
+// OBSOLETE CCOR_REGNUM = 75,
+// OBSOLETE CCOBR_REGNUM = 76,
+// OBSOLETE CCIBR_REGNUM = 77,
+// OBSOLETE CCIR_REGNUM = 78
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE /* Select the sparclet disassembler. Slightly different instruction set from
+// OBSOLETE the V8 sparc. */
+// OBSOLETE
+// OBSOLETE #undef TM_PRINT_INSN_MACH
+// OBSOLETE #define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclet
+// OBSOLETE
+// OBSOLETE /* overrides of tm-sparc.h */
+// OBSOLETE
+// OBSOLETE #undef TARGET_BYTE_ORDER
+// OBSOLETE
+// OBSOLETE /* Sequence of bytes for breakpoint instruction (ta 1). */
+// OBSOLETE #undef BREAKPOINT
+// OBSOLETE #define BIG_BREAKPOINT {0x91, 0xd0, 0x20, 0x01}
+// OBSOLETE #define LITTLE_BREAKPOINT {0x01, 0x20, 0xd0, 0x91}
+// OBSOLETE
+// OBSOLETE #if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+// OBSOLETE /*
+// OBSOLETE * The following defines must go away for MULTI_ARCH.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE #undef NUM_REGS /* formerly "72" */
+// OBSOLETE /* WIN FP CPU CCP ASR AWR APSR */
+// OBSOLETE #define NUM_REGS (32 + 32 + 8 + 8 + 8/*+ 32 + 1*/)
+// OBSOLETE
+// OBSOLETE #undef REGISTER_BYTES /* formerly "(32*4 + 32*4 + 8*4)" */
+// OBSOLETE #define REGISTER_BYTES (32*4 + 32*4 + 8*4 + 8*4 + 8*4/* + 32*4 + 1*4*/)
+// OBSOLETE
+// OBSOLETE /* Initializer for an array of names of registers.
+// OBSOLETE There should be NUM_REGS strings in this initializer. */
+// OBSOLETE /* Sparclet has no fp! */
+// OBSOLETE /* Compiler maps types for floats by number, so can't
+// OBSOLETE change the numbers here. */
+// OBSOLETE
+// OBSOLETE #undef REGISTER_NAMES
+// OBSOLETE #define REGISTER_NAMES \
+// OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
+// OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", \
+// OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
+// OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", \
+// OBSOLETE \
+// OBSOLETE "", "", "", "", "", "", "", "", /* no FPU regs */ \
+// OBSOLETE "", "", "", "", "", "", "", "", \
+// OBSOLETE "", "", "", "", "", "", "", "", \
+// OBSOLETE "", "", "", "", "", "", "", "", \
+// OBSOLETE /* no CPSR, FPSR */ \
+// OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "", "", \
+// OBSOLETE \
+// OBSOLETE "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", \
+// OBSOLETE \
+// OBSOLETE /* ASR15 ASR19 (don't display them) */ \
+// OBSOLETE "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22", \
+// OBSOLETE /* \
+// OBSOLETE "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7", \
+// OBSOLETE "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", \
+// OBSOLETE "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", \
+// OBSOLETE "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", \
+// OBSOLETE "apsr", \
+// OBSOLETE */ \
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Remove FP dependant code which was defined in tm-sparc.h */
+// OBSOLETE #undef FP0_REGNUM /* Floating point register 0 */
+// OBSOLETE #undef FPS_REGNUM /* Floating point status register */
+// OBSOLETE #undef CPS_REGNUM /* Coprocessor status register */
+// OBSOLETE
+// OBSOLETE /* sparclet register numbers */
+// OBSOLETE #define CCSR_REGNUM 72
+// OBSOLETE
+// OBSOLETE #undef DEPRECATED_EXTRACT_RETURN_VALUE
+// OBSOLETE #define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
+// OBSOLETE { \
+// OBSOLETE memcpy ((VALBUF), \
+// OBSOLETE (char *)(REGBUF) + REGISTER_RAW_SIZE (O0_REGNUM) * 8 + \
+// OBSOLETE (TYPE_LENGTH(TYPE) >= REGISTER_RAW_SIZE (O0_REGNUM) \
+// OBSOLETE ? 0 : REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH(TYPE)), \
+// OBSOLETE TYPE_LENGTH(TYPE)); \
+// OBSOLETE }
+// OBSOLETE #undef DEPRECATED_STORE_RETURN_VALUE
+// OBSOLETE #define DEPRECATED_STORE_RETURN_VALUE(TYPE,VALBUF) \
+// OBSOLETE { \
+// OBSOLETE /* Other values are returned in register %o0. */ \
+// OBSOLETE deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), (VALBUF), \
+// OBSOLETE TYPE_LENGTH (TYPE)); \
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #endif /* GDB_MULTI_ARCH */
+// OBSOLETE
+// OBSOLETE extern void sparclet_do_registers_info (int regnum, int all);
+// OBSOLETE #undef DEPRECATED_DO_REGISTERS_INFO
+// OBSOLETE #define DEPRECATED_DO_REGISTERS_INFO(REGNUM,ALL) sparclet_do_registers_info (REGNUM, ALL)
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE /* Offsets into jmp_buf. Not defined by Sun, but at least documented in a
+// OBSOLETE comment in <machine/setjmp.h>! */
+// OBSOLETE
+// OBSOLETE #define JB_ELEMENT_SIZE 4 /* Size of each element in jmp_buf */
+// OBSOLETE
+// OBSOLETE #define JB_ONSSTACK 0
+// OBSOLETE #define JB_SIGMASK 1
+// OBSOLETE #define JB_SP 2
+// OBSOLETE #define JB_PC 3
+// OBSOLETE #define JB_NPC 4
+// OBSOLETE #define JB_PSR 5
+// OBSOLETE #define JB_G1 6
+// OBSOLETE #define JB_O0 7
+// OBSOLETE #define JB_WBCNT 8
+// OBSOLETE
+// OBSOLETE /* Figure out where the longjmp will land. We expect that we have just entered
+// OBSOLETE longjmp and haven't yet setup the stack frame, so the args are still in the
+// OBSOLETE output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
+// OBSOLETE extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
+// OBSOLETE This routine returns true on success */
+// OBSOLETE
+// OBSOLETE extern int get_longjmp_target (CORE_ADDR *);
+// OBSOLETE
+// OBSOLETE #define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)
-/* Macro definitions for GDB for a Fujitsu SPARClite.
- Copyright 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#include "regcache.h"
-
-#define TARGET_SPARCLITE 1 /* Still needed for non-multi-arch case */
-
-#include "sparc/tm-sparc.h"
-
-/* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
- at this time, because we have not figured out how to detect the
- sparclet target from the bfd structure. */
-
-/* Sparclite regs, for debugging purposes */
-
-enum {
- DIA1_REGNUM = 72, /* debug instr address register 1 */
- DIA2_REGNUM = 73, /* debug instr address register 2 */
- DDA1_REGNUM = 74, /* debug data address register 1 */
- DDA2_REGNUM = 75, /* debug data address register 2 */
- DDV1_REGNUM = 76, /* debug data value register 1 */
- DDV2_REGNUM = 77, /* debug data value register 2 */
- DCR_REGNUM = 78, /* debug control register */
- DSR_REGNUM = 79 /* debug status regsiter */
-};
-
-/* overrides of tm-sparc.h */
-
-#undef TARGET_BYTE_ORDER
-
-/* Select the sparclite disassembler. Slightly different instruction set from
- the V8 sparc. */
-
-#undef TM_PRINT_INSN_MACH
-#define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclite
-
-/* Amount PC must be decremented by after a hardware instruction breakpoint.
- This is often the number of bytes in BREAKPOINT
- but not always. */
-
-#define DECR_PC_AFTER_HW_BREAK 4
-
-#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
-/*
- * The following defines must go away for MULTI_ARCH.
- */
-
-#undef NUM_REGS
-#define NUM_REGS 80
-
-#undef REGISTER_BYTES
-#define REGISTER_BYTES (32*4+32*4+8*4+8*4)
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
- "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", \
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
- "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", \
- \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
- "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
- "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
- \
- "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", \
- "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" }
-
-#define DIA1_REGNUM 72 /* debug instr address register 1 */
-#define DIA2_REGNUM 73 /* debug instr address register 2 */
-#define DDA1_REGNUM 74 /* debug data address register 1 */
-#define DDA2_REGNUM 75 /* debug data address register 2 */
-#define DDV1_REGNUM 76 /* debug data value register 1 */
-#define DDV2_REGNUM 77 /* debug data value register 2 */
-#define DCR_REGNUM 78 /* debug control register */
-#define DSR_REGNUM 79 /* debug status regsiter */
-
-#endif /* GDB_MULTI_ARCH */
-
-#define TARGET_HW_BREAK_LIMIT 2
-#define TARGET_HW_WATCH_LIMIT 2
-
-/* Enable watchpoint macro's */
-
-#define TARGET_HAS_HARDWARE_WATCHPOINTS
-
-#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
- sparclite_check_watch_resources (type, cnt, ot)
-
-/* When a hardware watchpoint fires off the PC will be left at the
- instruction which caused the watchpoint. It will be necessary for
- GDB to step over the watchpoint. ***
-
- #define STOPPED_BY_WATCHPOINT(W) \
- ((W).kind == TARGET_WAITKIND_STOPPED \
- && (W).value.sig == TARGET_SIGNAL_TRAP \
- && ((int) read_register (IPSW_REGNUM) & 0x00100000))
- */
-
-/* Use these macros for watchpoint insertion/deletion. */
-#define target_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type)
-#define target_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type)
-#define target_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len)
-#define target_remove_hw_breakpoint(addr, len) sparclite_remove_hw_breakpoint (addr, len)
-#define target_stopped_data_address() sparclite_stopped_data_address()
+// OBSOLETE /* Macro definitions for GDB for a Fujitsu SPARClite.
+// OBSOLETE Copyright 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE #define TARGET_SPARCLITE 1 /* Still needed for non-multi-arch case */
+// OBSOLETE
+// OBSOLETE #include "sparc/tm-sparc.h"
+// OBSOLETE
+// OBSOLETE /* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
+// OBSOLETE at this time, because we have not figured out how to detect the
+// OBSOLETE sparclet target from the bfd structure. */
+// OBSOLETE
+// OBSOLETE /* Sparclite regs, for debugging purposes */
+// OBSOLETE
+// OBSOLETE enum {
+// OBSOLETE DIA1_REGNUM = 72, /* debug instr address register 1 */
+// OBSOLETE DIA2_REGNUM = 73, /* debug instr address register 2 */
+// OBSOLETE DDA1_REGNUM = 74, /* debug data address register 1 */
+// OBSOLETE DDA2_REGNUM = 75, /* debug data address register 2 */
+// OBSOLETE DDV1_REGNUM = 76, /* debug data value register 1 */
+// OBSOLETE DDV2_REGNUM = 77, /* debug data value register 2 */
+// OBSOLETE DCR_REGNUM = 78, /* debug control register */
+// OBSOLETE DSR_REGNUM = 79 /* debug status regsiter */
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE /* overrides of tm-sparc.h */
+// OBSOLETE
+// OBSOLETE #undef TARGET_BYTE_ORDER
+// OBSOLETE
+// OBSOLETE /* Select the sparclite disassembler. Slightly different instruction set from
+// OBSOLETE the V8 sparc. */
+// OBSOLETE
+// OBSOLETE #undef TM_PRINT_INSN_MACH
+// OBSOLETE #define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclite
+// OBSOLETE
+// OBSOLETE /* Amount PC must be decremented by after a hardware instruction breakpoint.
+// OBSOLETE This is often the number of bytes in BREAKPOINT
+// OBSOLETE but not always. */
+// OBSOLETE
+// OBSOLETE #define DECR_PC_AFTER_HW_BREAK 4
+// OBSOLETE
+// OBSOLETE #if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+// OBSOLETE /*
+// OBSOLETE * The following defines must go away for MULTI_ARCH.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE #undef NUM_REGS
+// OBSOLETE #define NUM_REGS 80
+// OBSOLETE
+// OBSOLETE #undef REGISTER_BYTES
+// OBSOLETE #define REGISTER_BYTES (32*4+32*4+8*4+8*4)
+// OBSOLETE
+// OBSOLETE #undef REGISTER_NAMES
+// OBSOLETE #define REGISTER_NAMES \
+// OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
+// OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", \
+// OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
+// OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", \
+// OBSOLETE \
+// OBSOLETE "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
+// OBSOLETE "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
+// OBSOLETE "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
+// OBSOLETE "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
+// OBSOLETE \
+// OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", \
+// OBSOLETE "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" }
+// OBSOLETE
+// OBSOLETE #define DIA1_REGNUM 72 /* debug instr address register 1 */
+// OBSOLETE #define DIA2_REGNUM 73 /* debug instr address register 2 */
+// OBSOLETE #define DDA1_REGNUM 74 /* debug data address register 1 */
+// OBSOLETE #define DDA2_REGNUM 75 /* debug data address register 2 */
+// OBSOLETE #define DDV1_REGNUM 76 /* debug data value register 1 */
+// OBSOLETE #define DDV2_REGNUM 77 /* debug data value register 2 */
+// OBSOLETE #define DCR_REGNUM 78 /* debug control register */
+// OBSOLETE #define DSR_REGNUM 79 /* debug status regsiter */
+// OBSOLETE
+// OBSOLETE #endif /* GDB_MULTI_ARCH */
+// OBSOLETE
+// OBSOLETE #define TARGET_HW_BREAK_LIMIT 2
+// OBSOLETE #define TARGET_HW_WATCH_LIMIT 2
+// OBSOLETE
+// OBSOLETE /* Enable watchpoint macro's */
+// OBSOLETE
+// OBSOLETE #define TARGET_HAS_HARDWARE_WATCHPOINTS
+// OBSOLETE
+// OBSOLETE #define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
+// OBSOLETE sparclite_check_watch_resources (type, cnt, ot)
+// OBSOLETE
+// OBSOLETE /* When a hardware watchpoint fires off the PC will be left at the
+// OBSOLETE instruction which caused the watchpoint. It will be necessary for
+// OBSOLETE GDB to step over the watchpoint. ***
+// OBSOLETE
+// OBSOLETE #define STOPPED_BY_WATCHPOINT(W) \
+// OBSOLETE ((W).kind == TARGET_WAITKIND_STOPPED \
+// OBSOLETE && (W).value.sig == TARGET_SIGNAL_TRAP \
+// OBSOLETE && ((int) read_register (IPSW_REGNUM) & 0x00100000))
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE /* Use these macros for watchpoint insertion/deletion. */
+// OBSOLETE #define target_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type)
+// OBSOLETE #define target_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type)
+// OBSOLETE #define target_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len)
+// OBSOLETE #define target_remove_hw_breakpoint(addr, len) sparclite_remove_hw_breakpoint (addr, len)
+// OBSOLETE #define target_stopped_data_address() sparclite_stopped_data_address()
# OBSOLETE hppa*-*-osf*) gdb_host=hppaosf ;;
i[3456]86-ncr-*) gdb_host=ncr3000 ;;
-i[3456]86-sequent-bsd*) gdb_host=symmetry ;; # dynix
-i[3456]86-sequent-sysv4*) gdb_host=ptx4 ;;
-i[3456]86-sequent-sysv*) gdb_host=ptx ;;
+# OBSOLETE i[3456]86-sequent-bsd*) gdb_host=symmetry ;; # dynix
+# OBSOLETE i[3456]86-sequent-sysv4*) gdb_host=ptx4 ;;
+# OBSOLETE i[3456]86-sequent-sysv*) gdb_host=ptx ;;
i[3456]86-*-bsd*) gdb_host=i386bsd ;;
i[3456]86-*-dgux*) gdb_host=i386v4 ;;
i[3456]86-*-freebsd*) gdb_host=fbsd ;;
m68*-sun-sunos4*) gdb_host=sun3os4 ;;
m68*-sun-*) gdb_host=sun3os4 ;;
-mips-dec-mach3*) gdb_host=mipsm3 ;;
+# OBSOLETE mips-dec-mach3*) gdb_host=mipsm3 ;;
mips-dec-*) gdb_host=decstation ;;
mips-little-*) gdb_host=littlemips ;;
mips-sgi-irix3*) gdb_host=irix3 ;;
# OBSOLETE hppa*-*-osf*) gdb_target=hppaosf ;;
hppa*-*-*) gdb_target=hppa ;;
-i[3456]86-sequent-bsd*) gdb_target=symmetry ;;
-i[3456]86-sequent-sysv4*) gdb_target=ptx4 ;;
-i[3456]86-sequent-sysv*) gdb_target=ptx ;;
+# OBSOLETE i[3456]86-sequent-bsd*) gdb_target=symmetry ;;
+# OBSOLETE i[3456]86-sequent-sysv4*) gdb_target=ptx4 ;;
+# OBSOLETE i[3456]86-sequent-sysv*) gdb_target=ptx ;;
i[3456]86-ncr-*) gdb_target=ncr3000 ;;
i[3456]86-*-bsd*) gdb_target=i386bsd ;;
i[3456]86-*-netbsd*) gdb_target=nbsd ;;
build_gdbserver=yes
;;
mips*-*-netbsd*) gdb_target=nbsd ;;
-mips*-*-mach3*) gdb_target=mipsm3 ;;
+# OBSOLETE mips*-*-mach3*) gdb_target=mipsm3 ;;
mips*-*-sysv4*) gdb_target=mipsv4 ;;
mips*-*-sysv*) gdb_target=bigmips ;;
mips*-*-riscos*) gdb_target=bigmips ;;
sparc-*-sunos5*) gdb_target=sun4sol2 ;;
sparc-*-vxworks*) gdb_target=vxsparc ;;
sparc-*-*) gdb_target=sun4os4 ;;
-sparclet-*-*) gdb_target=sparclet;;
-sparclite-*-*) gdb_target=sparclite ;;
-sparc86x-*-*) gdb_target=sparclite ;;
+# OBSOLETE sparclet-*-*) gdb_target=sparclet;;
+# OBSOLETE sparclite-*-*) gdb_target=sparclite ;;
+# OBSOLETE sparc86x-*-*) gdb_target=sparclite ;;
# It's not clear what the right solution for "v8plus" systems is yet.
# For now, stick with sparc-sun-solaris2 since that's what config.guess
# should return. Work is still needed to get gdb to print the 64 bit
/* Machine independent GDB support for core files on systems using "regsets".
- Copyright 1993, 1994, 1995, 1996, 1998, 1999, 2000
+
+ Copyright 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2003
Free Software Foundation, Inc.
This file is part of GDB.
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-
-/* N O T E S
-
- This file is used by most systems that implement /proc. For these systems,
- the general registers are laid out the same way in both the core file and
- the gregset_p structure. The current exception to this is Irix-4.*, where
- the gregset_p structure is split up into two pieces in the core file.
-
- The general register and floating point register sets are manipulated by
- separate ioctl's. This file makes the assumption that if FP0_REGNUM is
- defined, then support for the floating point register set is desired,
- regardless of whether or not the actual target has floating point hardware.
-
- */
+/* This file is used by most systems that use ELF for their core
+ dumps. This includes most systems that have SVR4-ish variant of
+ /proc. For these systems, the registers are laid out the same way
+ in core files as in the gregset_t and fpregset_t structures that
+ are used in the interaction with /proc (Irix 4 is an exception and
+ therefore doesn't use this file). Quite a few systems without a
+ SVR4-ish /proc define these structures too, and can make use of
+ this code too. */
#include "defs.h"
+#include "command.h"
+#include "gdbcore.h"
+#include "inferior.h"
+#include "target.h"
+#include <fcntl.h>
+#include <errno.h>
+#include "gdb_string.h"
#include <time.h>
#ifdef HAVE_SYS_PROCFS_H
#include <sys/procfs.h>
#endif
-#include <fcntl.h>
-#include <errno.h>
-#include "gdb_string.h"
-#include "inferior.h"
-#include "target.h"
-#include "command.h"
-#include "gdbcore.h"
-
-/* Prototypes for supply_gregset etc. */
+/* Prototypes for supply_gregset etc. */
#include "gregset.h"
-static void fetch_core_registers (char *, unsigned, int, CORE_ADDR);
-
-void _initialize_core_regset (void);
-
-/*
-
- GLOBAL FUNCTION
+/* Provide registers to GDB from a core file.
- fetch_core_registers -- fetch current registers from core file
+ CORE_REG_SECT points to an array of bytes, which are the contents
+ of a `note' from a core file which BFD thinks might contain
+ register contents. CORE_REG_SIZE is its size.
- SYNOPSIS
+ WHICH says which register set corelow suspects this is:
+ 0 --- the general-purpose register set, in gregset_t format
+ 2 --- the floating-point register set, in fpregset_t format
- void fetch_core_registers (char *core_reg_sect,
- unsigned core_reg_size,
- int which, CORE_ADDR reg_addr)
-
- DESCRIPTION
-
- Read the values of either the general register set (WHICH equals 0)
- or the floating point register set (WHICH equals 2) from the core
- file data (pointed to by CORE_REG_SECT), and update gdb's idea of
- their current values. The CORE_REG_SIZE parameter is compared to
- the size of the gregset or fpgregset structures (as appropriate) to
- validate the size of the structure from the core file. The
- REG_ADDR parameter is ignored.
-
- */
+ REG_ADDR is ignored. */
static void
fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, int which,
gdb_gregset_t gregset;
gdb_fpregset_t fpregset;
- if (which == 0)
+ switch (which)
{
+ case 0:
if (core_reg_size != sizeof (gregset))
- {
- warning ("wrong size gregset struct in core file");
- }
+ warning ("Wrong size gregset in core file.");
else
{
- memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
+ memcpy (&gregset, core_reg_sect, sizeof (gregset));
supply_gregset (&gregset);
}
- }
- else if (which == 2)
- {
+ break;
+
+ case 2:
if (core_reg_size != sizeof (fpregset))
- {
- warning ("wrong size fpregset struct in core file");
- }
+ warning ("Wrong size fpregset in core file.");
else
{
- memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
+ memcpy (&fpregset, core_reg_sect, sizeof (fpregset));
if (FP0_REGNUM >= 0)
supply_fpregset (&fpregset);
}
+ break;
+
+ default:
+ /* We've covered all the kinds of registers we know about here,
+ so this must be something we wouldn't know what to do with
+ anyway. Just ignore it. */
+ break;
}
}
\f
-/* Register that we are able to handle ELF file formats using standard
- procfs "regset" structures. */
+/* Register that we are able to handle ELF core file formats using
+ standard procfs "regset" structures. */
static struct core_fns regset_core_fns =
{
NULL /* next */
};
+/* Provide a prototype to silence -Wmissing-prototypes. */
+extern void _initialize_core_regset (void);
+
void
_initialize_core_regset (void)
{
#ifndef CP_ABI_H_
#define CP_ABI_H_ 1
+struct fn_field;
+struct type;
struct value;
/* The functions here that attempt to determine what sort of thing a
--- /dev/null
+/* Helper routines for C++ support in GDB.
+ Copyright 2003 Free Software Foundation, Inc.
+
+ Contributed by David Carlton.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#include "defs.h"
+#include "cp-support.h"
+#include "gdb_obstack.h"
+#include "symtab.h"
+#include "symfile.h"
+#include "gdb_assert.h"
+#include "block.h"
+
+/* When set, the file that we're processing seems to have debugging
+ info for C++ namespaces, so cp-namespace.c shouldn't try to guess
+ namespace info itself. */
+
+unsigned char processing_has_namespace_info;
+
+/* If processing_has_namespace_info is nonzero, this string should
+ contain the name of the current namespace. The string is
+ temporary; copy it if you need it. */
+
+const char *processing_current_namespace;
+
+/* List of using directives that are active in the current file. */
+
+static struct using_direct *using_list;
+
+static struct using_direct *cp_add_using (const char *name,
+ unsigned int inner_len,
+ unsigned int outer_len,
+ struct using_direct *next);
+
+static struct using_direct *cp_copy_usings (struct using_direct *using,
+ struct obstack *obstack);
+
+/* Set up support for dealing with C++ namespace info in the current
+ symtab. */
+
+void cp_initialize_namespace ()
+{
+ processing_has_namespace_info = 0;
+ using_list = NULL;
+}
+
+/* Add all the using directives we've gathered to the current symtab.
+ STATIC_BLOCK should be the symtab's static block; OBSTACK is used
+ for allocation. */
+
+void
+cp_finalize_namespace (struct block *static_block,
+ struct obstack *obstack)
+{
+ if (using_list != NULL)
+ {
+ block_set_using (static_block,
+ cp_copy_usings (using_list, obstack),
+ obstack);
+ using_list = NULL;
+ }
+}
+
+/* Check to see if SYMBOL refers to an object contained within an
+ anonymous namespace; if so, add an appropriate using directive. */
+
+/* Optimize away strlen ("(anonymous namespace)"). */
+
+#define ANONYMOUS_NAMESPACE_LEN 21
+
+void
+cp_scan_for_anonymous_namespaces (const struct symbol *symbol)
+{
+ if (!processing_has_namespace_info
+ && SYMBOL_CPLUS_DEMANGLED_NAME (symbol) != NULL)
+ {
+ const char *name = SYMBOL_CPLUS_DEMANGLED_NAME (symbol);
+ unsigned int previous_component;
+ unsigned int next_component;
+ const char *len;
+
+ /* Start with a quick-and-dirty check for mention of "(anonymous
+ namespace)". */
+
+ if (!cp_is_anonymous (name))
+ return;
+
+ previous_component = 0;
+ next_component = cp_find_first_component (name + previous_component);
+
+ while (name[next_component] == ':')
+ {
+ if ((next_component - previous_component) == ANONYMOUS_NAMESPACE_LEN
+ && strncmp (name + previous_component,
+ "(anonymous namespace)",
+ ANONYMOUS_NAMESPACE_LEN) == 0)
+ {
+ /* We've found a component of the name that's an
+ anonymous namespace. So add symbols in it to the
+ namespace given by the previous component if there is
+ one, or to the global namespace if there isn't. */
+ cp_add_using_directive (name,
+ previous_component == 0
+ ? 0 : previous_component - 2,
+ next_component);
+ }
+ /* The "+ 2" is for the "::". */
+ previous_component = next_component + 2;
+ next_component = (previous_component
+ + cp_find_first_component (name
+ + previous_component));
+ }
+ }
+}
+
+/* Add a using directive to using_list. NAME is the start of a string
+ that should contain the namespaces we want to add as initial
+ substrings, OUTER_LENGTH is the end of the outer namespace, and
+ INNER_LENGTH is the end of the inner namespace. If the using
+ directive in question has already been added, don't add it
+ twice. */
+
+void
+cp_add_using_directive (const char *name, unsigned int outer_length,
+ unsigned int inner_length)
+{
+ struct using_direct *current;
+ struct using_direct *new;
+
+ /* Has it already been added? */
+
+ for (current = using_list; current != NULL; current = current->next)
+ {
+ if ((strncmp (current->inner, name, inner_length) == 0)
+ && (strlen (current->inner) == inner_length)
+ && (strlen (current->outer) == outer_length))
+ return;
+ }
+
+ using_list = cp_add_using (name, inner_length, outer_length,
+ using_list);
+}
+
+/* Record the namespace that the function defined by SYMBOL was
+ defined in, if necessary. BLOCK is the associated block; use
+ OBSTACK for allocation. */
+
+void
+cp_set_block_scope (const struct symbol *symbol,
+ struct block *block,
+ struct obstack *obstack)
+{
+ /* Make sure that the name was originally mangled: if not, there
+ certainly isn't any namespace information to worry about! */
+
+ if (SYMBOL_CPLUS_DEMANGLED_NAME (symbol) != NULL)
+ {
+ if (processing_has_namespace_info)
+ {
+ block_set_scope
+ (block, obsavestring (processing_current_namespace,
+ strlen (processing_current_namespace),
+ obstack),
+ obstack);
+ }
+ else
+ {
+ /* Try to figure out the appropriate namespace from the
+ demangled name. */
+
+ /* FIXME: carlton/2003-04-15: If the function in question is
+ a method of a class, the name will actually include the
+ name of the class as well. This should be harmless, but
+ is a little unfortunate. */
+
+ const char *name = SYMBOL_CPLUS_DEMANGLED_NAME (symbol);
+ unsigned int prefix_len = cp_entire_prefix_len (name);
+
+ block_set_scope (block,
+ obsavestring (name, prefix_len, obstack),
+ obstack);
+ }
+ }
+}
+
+/* Test whether or not NAMESPACE looks like it mentions an anonymous
+ namespace; return nonzero if so. */
+
+int
+cp_is_anonymous (const char *namespace)
+{
+ return (strstr (namespace, "(anonymous namespace)")
+ != NULL);
+}
+
+/* Create a new struct using direct whose inner namespace is the
+ initial substring of NAME of leng INNER_LEN and whose outer
+ namespace is the initial substring of NAME of length OUTER_LENGTH.
+ Set its next member in the linked list to NEXT; allocate all memory
+ using xmalloc. It copies the strings, so NAME can be a temporary
+ string. */
+
+static struct using_direct *
+cp_add_using (const char *name,
+ unsigned int inner_len,
+ unsigned int outer_len,
+ struct using_direct *next)
+{
+ struct using_direct *retval;
+
+ gdb_assert (outer_len < inner_len);
+
+ retval = xmalloc (sizeof (struct using_direct));
+ retval->inner = savestring (name, inner_len);
+ retval->outer = savestring (name, outer_len);
+ retval->next = next;
+
+ return retval;
+}
+
+/* Make a copy of the using directives in the list pointed to by
+ USING, using OBSTACK to allocate memory. Free all memory pointed
+ to by USING via xfree. */
+
+static struct using_direct *
+cp_copy_usings (struct using_direct *using,
+ struct obstack *obstack)
+{
+ if (using == NULL)
+ {
+ return NULL;
+ }
+ else
+ {
+ struct using_direct *retval
+ = obstack_alloc (obstack, sizeof (struct using_direct));
+ retval->inner = obsavestring (using->inner, strlen (using->inner),
+ obstack);
+ retval->outer = obsavestring (using->outer, strlen (using->outer),
+ obstack);
+ retval->next = cp_copy_usings (using->next, obstack);
+
+ xfree (using->inner);
+ xfree (using->outer);
+ xfree (using);
+
+ return retval;
+ }
+}
/* Helper routines for C++ support in GDB.
- Copyright 2002 Free Software Foundation, Inc.
+ Copyright 2002, 2003 Free Software Foundation, Inc.
Contributed by MontaVista Software.
Boston, MA 02111-1307, USA. */
#include "defs.h"
+#include <ctype.h>
#include "cp-support.h"
#include "gdb_string.h"
#include "demangle.h"
+#include "gdb_assert.h"
+#include "gdbcmd.h"
+
+/* The list of "maint cplus" commands. */
+
+static struct cmd_list_element *maint_cplus_cmd_list = NULL;
+
+/* The actual commands. */
+
+static void maint_cplus_command (char *arg, int from_tty);
+static void first_component_command (char *arg, int from_tty);
+
+/* Here are some random pieces of trivia to keep in mind while trying
+ to take apart demangled names:
+
+ - Names can contain function arguments or templates, so the process
+ has to be, to some extent recursive: maybe keep track of your
+ depth based on encountering <> and ().
+
+ - Parentheses don't just have to happen at the end of a name: they
+ can occur even if the name in question isn't a function, because
+ a template argument might be a type that's a function.
+
+ - Conversely, even if you're trying to deal with a function, its
+ demangled name might not end with ')': it could be a const or
+ volatile class method, in which case it ends with "const" or
+ "volatile".
+
+ - Parentheses are also used in anonymous namespaces: a variable
+ 'foo' in an anonymous namespace gets demangled as "(anonymous
+ namespace)::foo".
+
+ - And operator names can contain parentheses or angle brackets.
+ Fortunately, I _think_ that operator names can only occur in a
+ fairly restrictive set of locations (in particular, they have be
+ at depth 0, don't they?). */
+
+/* NOTE: carlton/2003-02-21: Daniel Jacobowitz came up with an example
+ where operator names don't occur at depth 0. Sigh. (It involved a
+ template argument that was a pointer: I hadn't realized that was
+ possible.) Handling such edge cases does not seem like a
+ high-priority problem to me. */
+
+/* FIXME: carlton/2003-03-13: We have several functions here with
+ overlapping functionality; can we combine them? Also, do they
+ handle all the above considerations correctly? */
/* Find the last component of the demangled C++ name NAME. NAME
must be a method name including arguments, in order to correctly
xfree (demangled_name);
return ret;
}
+
+/* This returns the length of first component of NAME, which should be
+ the demangled name of a C++ variable/function/method/etc.
+ Specifically, it returns the index of the first colon forming the
+ boundary of the first component: so, given 'A::foo' or 'A::B::foo'
+ it returns the 1, and given 'foo', it returns 0. */
+
+/* Well, that's what it should do when called externally, but to make
+ the recursion easier, it also stops if it reaches an unexpected ')'
+ or '>'. */
+
+/* NOTE: carlton/2003-03-13: This function is currently only intended
+ for internal use: it's probably not entirely safe when called on
+ user-generated input, because some of the 'index += 2' lines might
+ go past the end of malformed input. */
+
+/* Let's optimize away calls to strlen("operator"). */
+
+#define LENGTH_OF_OPERATOR 8
+
+unsigned int
+cp_find_first_component (const char *name)
+{
+ /* Names like 'operator<<' screw up the recursion, so let's
+ special-case them. I _hope_ they can only occur at the start of
+ a component. */
+
+ unsigned int index = 0;
+
+ if (strncmp (name, "operator", LENGTH_OF_OPERATOR) == 0)
+ {
+ index += LENGTH_OF_OPERATOR;
+ while (isspace(name[index]))
+ ++index;
+ switch (name[index])
+ {
+ case '<':
+ if (name[index + 1] == '<')
+ index += 2;
+ else
+ index += 1;
+ break;
+ case '>':
+ case '-':
+ if (name[index + 1] == '>')
+ index += 2;
+ else
+ index += 1;
+ break;
+ case '(':
+ index += 2;
+ break;
+ default:
+ index += 1;
+ break;
+ }
+ }
+
+ for (;; ++index)
+ {
+ switch (name[index])
+ {
+ case '<':
+ /* Template; eat it up. The calls to cp_first_component
+ should only return (I hope!) when they reach the '>'
+ terminating the component or a '::' between two
+ components. (Hence the '+ 2'.) */
+ index += 1;
+ for (index += cp_find_first_component (name + index);
+ name[index] != '>';
+ index += cp_find_first_component (name + index))
+ {
+ gdb_assert (name[index] == ':');
+ index += 2;
+ }
+ break;
+ case '(':
+ /* Similar comment as to '<'. */
+ index += 1;
+ for (index += cp_find_first_component (name + index);
+ name[index] != ')';
+ index += cp_find_first_component (name + index))
+ {
+ gdb_assert (name[index] == ':');
+ index += 2;
+ }
+ break;
+ case '>':
+ case ')':
+ case '\0':
+ case ':':
+ return index;
+ default:
+ break;
+ }
+ }
+}
+
+/* If NAME is the fully-qualified name of a C++
+ function/variable/method/etc., this returns the length of its
+ entire prefix: all of the namespaces and classes that make up its
+ name. Given 'A::foo', it returns 1, given 'A::B::foo', it returns
+ 4, given 'foo', it returns 0. */
+
+unsigned int
+cp_entire_prefix_len (const char *name)
+{
+ unsigned int current_len = cp_find_first_component (name);
+ unsigned int previous_len = 0;
+
+ while (name[current_len] != '\0')
+ {
+ gdb_assert (name[current_len] == ':');
+ previous_len = current_len;
+ /* Skip the '::'. */
+ current_len += 2;
+ current_len += cp_find_first_component (name + current_len);
+ }
+
+ return previous_len;
+}
+
+/* Don't allow just "maintenance cplus". */
+
+static void
+maint_cplus_command (char *arg, int from_tty)
+{
+ printf_unfiltered ("\"maintenance cplus\" must be followed by the name of a command.\n");
+ help_list (maint_cplus_cmd_list, "maintenance cplus ", -1, gdb_stdout);
+}
+
+/* This is a front end for cp_find_first_component, for unit testing.
+ Be careful when using it: see the NOTE above
+ cp_find_first_component. */
+
+static void
+first_component_command (char *arg, int from_tty)
+{
+ int len = cp_find_first_component (arg);
+ char *prefix = alloca (len + 1);
+
+ memcpy (prefix, arg, len);
+ prefix[len] = '\0';
+
+ printf_unfiltered ("%s\n", prefix);
+}
+
+void
+_initialize_cp_support (void)
+{
+ add_prefix_cmd ("cplus", class_maintenance, maint_cplus_command,
+ "C++ maintenance commands.", &maint_cplus_cmd_list,
+ "maintenance cplus ", 0, &maintenancelist);
+ add_alias_cmd ("cp", "cplus", class_maintenance, 1, &maintenancelist);
+
+ add_cmd ("first_component", class_maintenance, first_component_command,
+ "Print the first class/namespace component of NAME.",
+ &maint_cplus_cmd_list);
+
+}
/* Helper routines for C++ support in GDB.
- Copyright 2002 Free Software Foundation, Inc.
+ Copyright 2002, 2003 Free Software Foundation, Inc.
Contributed by MontaVista Software.
+ Namespace support contributed by David Carlton.
This file is part of GDB.
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+#ifndef CP_SUPPORT_H
+#define CP_SUPPORT_H
+
+/* Opaque declarations. */
+
+struct obstack;
+struct block;
+struct symbol;
+
+/* This struct is designed to store data from using directives. It
+ says that names from namespace INNER should be visible within
+ namespace OUTER. OUTER should always be a strict initial substring
+ of INNER. These form a linked list; NEXT is the next element of
+ the list. */
+
+struct using_direct
+{
+ char *inner;
+ char *outer;
+ struct using_direct *next;
+};
+
+
+/* Functions from cp-support.c. */
+
extern char *class_name_from_physname (const char *physname);
extern char *method_name_from_physname (const char *physname);
+
+extern unsigned int cp_find_first_component (const char *name);
+
+extern unsigned int cp_entire_prefix_len (const char *name);
+
+
+/* Functions/variables from cp-namespace.c. */
+
+extern unsigned char processing_has_namespace_info;
+
+extern const char *processing_current_namespace;
+
+extern int cp_is_anonymous (const char *namespace);
+
+extern void cp_add_using_directive (const char *name,
+ unsigned int outer_length,
+ unsigned int inner_length);
+
+extern void cp_initialize_namespace ();
+
+extern void cp_finalize_namespace (struct block *static_block,
+ struct obstack *obstack);
+
+extern void cp_set_block_scope (const struct symbol *symbol,
+ struct block *block,
+ struct obstack *obstack);
+
+extern void cp_scan_for_anonymous_namespaces (const struct symbol *symbol);
+
+#endif /* CP_SUPPORT_H */
fprintf_filtered (stream, "<unknown>");
return;
}
- addr = unpack_pointer (lookup_pointer_type (builtin_type_void), valaddr);
+ addr = unpack_pointer (type, valaddr);
if (METHOD_PTR_IS_VIRTUAL (addr))
{
offset = METHOD_PTR_TO_VOFFSET (addr);
set_gdbarch_deprecated_frame_chain (gdbarch, cris_frame_chain);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, cris_frame_saved_pc);
- set_gdbarch_saved_pc_after_call (gdbarch, cris_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, cris_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
return (addr | DMEM_START);
}
-/* Immediately after a function call, return the saved pc. We can't
- use frame->return_pc beause that is determined by reading R13 off
- the stack and that may not be written yet. */
-
-static CORE_ADDR
-d10v_saved_pc_after_call (struct frame_info *frame)
-{
- return ((read_register (LR_REGNUM) << 2)
- | IMEM_START);
-}
-
static int
check_prologue (unsigned short op)
{
info->uses_frame = 0;
for (pc = frame_func_unwind (next_frame);
- pc < frame_pc_unwind (next_frame);
+ pc > 0 && pc < frame_pc_unwind (next_frame);
pc += 4)
{
op = (unsigned long) read_memory_integer (pc, 4);
struct d10v_unwind_cache *info
= d10v_frame_unwind_cache (next_frame, this_prologue_cache);
CORE_ADDR base;
- CORE_ADDR pc;
+ CORE_ADDR func;
+ struct frame_id id;
- /* The PC is easy. */
- pc = frame_pc_unwind (next_frame);
+ /* The FUNC is easy. */
+ func = frame_func_unwind (next_frame);
/* This is meant to halt the backtrace at "_start". Make sure we
don't halt it at a generic dummy frame. */
- if (pc == IMEM_START || pc <= IMEM_START || inside_entry_file (pc))
+ if (func <= IMEM_START || inside_entry_file (func))
return;
/* Hopefully the prologue analysis either correctly determined the
if (base == STACK_START || base == 0)
return;
+ id = frame_id_build (base, func);
+
/* Check that we're not going round in circles with the same frame
ID (but avoid applying the test to sentinel frames which do go
round in circles). Can't use frame_id_eq() as that doesn't yet
compare the frame's PC value. */
if (frame_relative_level (next_frame) >= 0
&& get_frame_type (next_frame) != DUMMY_FRAME
- && get_frame_pc (next_frame) == pc
- && get_frame_base (next_frame) == base)
+ && frame_id_eq (get_frame_id (next_frame), id))
return;
- (*this_id) = frame_id_build (base, pc);
+ (*this_id) = id;
}
static void
set_gdbarch_frame_args_skip (gdbarch, 0);
set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
- set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
set_gdbarch_stack_align (gdbarch, d10v_stack_align);
extern void fputstrn_unfiltered (const char *str, int n, int quotr, struct ui_file * stream);
/* Display the host ADDR on STREAM formatted as ``0x%x''. */
-extern void gdb_print_host_address (void *addr, struct ui_file *stream);
+extern void gdb_print_host_address (const void *addr, struct ui_file *stream);
/* Convert a CORE_ADDR into a HEX string. paddr() is like %08lx.
paddr_nz() is like %lx. paddr_u() is like %lu. paddr_width() is
/* parts of the symbolic representation of the address */
int unmapped;
- char *filename = NULL;
- char *name = NULL;
int offset;
int line;
struct cleanup *ui_out_chain;
for (pc = low; pc < high;)
{
+ char *filename = NULL;
+ char *name = NULL;
+
QUIT;
if (how_many >= 0)
{
if (strcmp (target_shortname, "child") == 0
|| strcmp (target_shortname, "procfs") == 0
|| strcmp (target_shortname, "vxprocess") == 0
- || strstr (target_shortname, "-threads") != NULL)
+ || strcmp (target_shortname, "core") == 0
+ || strstr (target_shortname, "-thread") != NULL)
gdb_disassemble_from_exec = 0; /* It's a child process, read inferior mem */
else
gdb_disassemble_from_exec = 1; /* It's remote, read the exec file */
#ifndef DISASM_H
#define DISASM_H
+struct ui_out;
+
extern void gdb_disassembly (struct ui_out *uiout,
char *file_string,
int line_num,
+2003-04-09 Jim Blandy <jimb@redhat.com>
+
+ * gdb.texinfo (Symbols): Document 'maint list symtabs' and 'maint
+ list psymtabs'.
+
+2003-04-08 Andrew Cagney <cagney@redhat.com>
+
+ * gdbint.texinfo (Target Architecture Definition): Delete
+ references to EXTRA_FRAME_INFO.
+
+2003-04-08 Andrew Cagney <cagney@redhat.com>
+
+ * gdbint.texinfo (Target Architecture Definition): Delete
+ PRINT_TYPELESS_INTEGER.
+
2003-04-02 J. Brobecker <brobecker@gnat.com>
* observer.texi (GDB Observers): Adjust the documentation for the
required for each object file from which @value{GDBN} has read some symbols.
@xref{Files, ,Commands to specify files}, for a discussion of how
@value{GDBN} reads symbols (in the description of @code{symbol-file}).
+
+@kindex maint list symtabs
+@kindex maint list psymtabs
+@cindex listing @value{GDBN}'s internal symbol tables
+@cindex symbol tables, listing @value{GDBN}'s internal
+@cindex full symbol tables, listing @value{GDBN}'s internal
+@cindex partial symbol tables, listing @value{GDBN}'s internal
+@item maint list symtabs @r{[} @var{regexp} @r{]}
+@itemx maint list psymtabs @r{[} @var{regexp} @r{]}
+
+List the @code{struct symtab} or @code{struct partial_symtab}
+structures whose names match @var{regexp}. If @var{regexp} is not
+given, list them all. The output includes expressions which you can
+copy into a @value{GDBN} debugging this one to examine a particular
+structure in more detail. For example:
+
+@smallexample
+(@value{GDBP}) maint list psymtabs dwarf2read
+@{ objfile /home/gnu/build/gdb/gdb
+ ((struct objfile *) 0x82e69d0)
+ @{ psymtab /home/gnu/src/gdb/dwarf2read.c
+ ((struct partial_symtab *) 0x8474b10)
+ readin no
+ fullname (null)
+ text addresses 0x814d3c8 -- 0x8158074
+ globals (* (struct partial_symbol **) 0x8507a08 @@ 9)
+ statics (* (struct partial_symbol **) 0x40e95b78 @@ 2882)
+ dependencies (none)
+ @}
+@}
+(@value{GDBP}) maint list symtabs
+(@value{GDBP})
+@end smallexample
+@noindent
+We see that there is one partial symbol table whose filename contains
+the string @samp{dwarf2read}, belonging to the @samp{gdb} executable;
+and we see that @value{GDBN} has not read in any symtabs yet at all.
+If we set a breakpoint on a function, that will cause @value{GDBN} to
+read the symtab for the compilation unit containing that function:
+
+@smallexample
+(@value{GDBP}) break dwarf2_psymtab_to_symtab
+Breakpoint 1 at 0x814e5da: file /home/gnu/src/gdb/dwarf2read.c,
+line 1574.
+(@value{GDBP}) maint list symtabs
+@{ objfile /home/gnu/build/gdb/gdb
+ ((struct objfile *) 0x82e69d0)
+ @{ symtab /home/gnu/src/gdb/dwarf2read.c
+ ((struct symtab *) 0x86c1f38)
+ dirname (null)
+ fullname (null)
+ blockvector ((struct blockvector *) 0x86c1bd0) (primary)
+ debugformat DWARF 2
+ @}
+@}
+(@value{GDBP})
+@end smallexample
@end table
+
@node Altering
@chapter Altering Execution
@code{DEPRECATED_FRAME_INIT_SAVED_REGS} using
@code{frame_saved_regs_zalloc}.
-@code{FRAME_FIND_SAVED_REGS} and @code{EXTRA_FRAME_INFO} are deprecated.
+@code{FRAME_FIND_SAVED_REGS} is deprecated.
@item FRAME_NUM_ARGS (@var{fi})
@findex FRAME_NUM_ARGS
If non-zero, round arguments to a boundary of this many bits before
pushing them on the stack.
-@item PRINT_TYPELESS_INTEGER
-@findex PRINT_TYPELESS_INTEGER
-This is an obscure substitute for @code{print_longest} that seems to
-have been defined for the Convex target.
-
@item PROCESS_LINENUMBER_HOOK
@findex PROCESS_LINENUMBER_HOOK
A hook defined for XCOFF reading.
Some mechanisms do not work with multi-arch. They include:
@table @code
-@item EXTRA_FRAME_INFO
-Delete.
@item FRAME_FIND_SAVED_REGS
Replaced with @code{DEPRECATED_FRAME_INIT_SAVED_REGS}
@end table
/* Floating point routines for GDB, the GNU debugger.
- Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
- 1997, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
+
+ Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995,
+ 1996, 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation,
+ Inc.
This file is part of GDB.
/* Extract a floating-point number of length LEN from a target-order
byte-stream at ADDR. Returns the value as type DOUBLEST. */
-DOUBLEST
-extract_floating (const void *addr, int len)
+static DOUBLEST
+extract_floating_by_length (const void *addr, int len)
{
const struct floatformat *fmt = floatformat_from_length (len);
DOUBLEST val;
return val;
}
+DOUBLEST
+deprecated_extract_floating (const void *addr, int len)
+{
+ return extract_floating_by_length (addr, len);
+}
+
/* Store VAL as a floating-point number of length LEN to a
target-order byte-stream at ADDR. */
-void
-store_floating (void *addr, int len, DOUBLEST val)
+static void
+store_floating_by_length (void *addr, int len, DOUBLEST val)
{
const struct floatformat *fmt = floatformat_from_length (len);
floatformat_from_doublest (fmt, &val, addr);
}
+void
+deprecated_store_floating (void *addr, int len, DOUBLEST val)
+{
+ store_floating_by_length (addr, len, val);
+}
+
/* Extract a floating-point number of type TYPE from a target-order
byte-stream at ADDR. Returns the value as type DOUBLEST. */
gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
if (TYPE_FLOATFORMAT (type) == NULL)
- return extract_floating (addr, TYPE_LENGTH (type));
+ /* Not all code remembers to set the FLOATFORMAT (language
+ specific code? stabs?) so handle that here as a special case. */
+ return extract_floating_by_length (addr, TYPE_LENGTH (type));
floatformat_to_doublest (TYPE_FLOATFORMAT (type), addr, &retval);
return retval;
memset (addr, 0, TYPE_LENGTH (type));
if (TYPE_FLOATFORMAT (type) == NULL)
- store_floating (addr, TYPE_LENGTH (type), val);
+ /* Not all code remembers to set the FLOATFORMAT (language
+ specific code? stabs?) so handle that here as a special case. */
+ store_floating_by_length (addr, TYPE_LENGTH (type), val);
else
floatformat_from_doublest (TYPE_FLOATFORMAT (type), &val, addr);
}
/* Floating point definitions for GDB.
- Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
- 1997, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
+
+ Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995,
+ 1996, 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation,
+ Inc.
This file is part of GDB.
#ifndef DOUBLEST_H
#define DOUBLEST_H
+struct type;
+
/* Setup definitions for host and target floating point formats. We need to
consider the format for `float', `double', and `long double' for both target
and host. We need to do this so that we know what kind of conversions need
extern int floatformat_is_nan (const struct floatformat *, char *);
extern char *floatformat_mantissa (const struct floatformat *, char *);
-/* These two functions are deprecated in favour of
- extract_typed_floating and store_typed_floating. See comments in
- 'doublest.c' for details. */
+/* These functions have been replaced by extract_typed_floating and
+ store_typed_floating.
+
+ Most calls are passing in TYPE_LENGTH (TYPE) so can be changed to
+ just pass the TYPE. The remainder pass in the length of a
+ register, those calls should instead pass in the floating point
+ type that corresponds to that length. */
-extern DOUBLEST extract_floating (const void *addr, int len);
-extern void store_floating (void *addr, int len, DOUBLEST val);
+extern DOUBLEST deprecated_extract_floating (const void *addr, int len);
+extern void deprecated_store_floating (void *addr, int len, DOUBLEST val);
/* Given TYPE, return its floatformat. TYPE_FLOATFORMAT() may return
NULL. type_floatformat() detects that and returns a floatformat
(*this_id) = null_frame_id;
return;
}
- (*this_prologue_cache) = find_dummy_frame ((*this_id).pc, (*this_id).base);
+ (*this_prologue_cache) = find_dummy_frame ((*this_id).code_addr,
+ (*this_id).stack_addr);
}
static struct frame_unwind dummy_frame_unwind =
#ifndef DWARF2CFI_H
#define DWARF2CFI_H
+struct frame_info;
+
struct context_reg
{
union
BUF_END. The address is returned, and *BYTES_READ is set to the
number of bytes read from BUF. */
-static CORE_ADDR
-read_address (unsigned char *buf, unsigned char *buf_end, int *bytes_read)
+CORE_ADDR
+dwarf2_read_address (unsigned char *buf, unsigned char *buf_end, int *bytes_read)
{
CORE_ADDR result;
if (buf_end - buf < TARGET_ADDR_BIT / TARGET_CHAR_BIT)
- error ("read_address: Corrupted DWARF expression.");
+ error ("dwarf2_read_address: Corrupted DWARF expression.");
*bytes_read = TARGET_ADDR_BIT / TARGET_CHAR_BIT;
result = extract_address (buf, TARGET_ADDR_BIT / TARGET_CHAR_BIT);
while (op_ptr < op_end)
{
enum dwarf_location_atom op = *op_ptr++;
- CORE_ADDR result, memaddr;
+ CORE_ADDR result;
ULONGEST uoffset, reg;
LONGEST offset;
int bytes_read;
- enum lval_type expr_lval;
ctx->in_reg = 0;
break;
case DW_OP_addr:
- result = read_address (op_ptr, op_end, &bytes_read);
+ result = dwarf2_read_address (op_ptr, op_end, &bytes_read);
op_ptr += bytes_read;
break;
error ("DWARF-2 expression error: DW_OP_reg operations must be "
"used alone.");
- /* FIXME drow/2003-02-21: This call to read_reg could be pushed
- into the evaluator's caller by changing the semantics for in_reg.
- Then we wouldn't need to return an lval_type and a memaddr. */
- result = (ctx->read_reg) (ctx->baton, op - DW_OP_reg0, &expr_lval,
- &memaddr);
-
- if (expr_lval == lval_register)
- {
- ctx->regnum = op - DW_OP_reg0;
- ctx->in_reg = 1;
- }
- else
- result = memaddr;
+ result = op - DW_OP_reg0;
+ ctx->in_reg = 1;
break;
error ("DWARF-2 expression error: DW_OP_reg operations must be "
"used alone.");
- result = (ctx->read_reg) (ctx->baton, reg, &expr_lval, &memaddr);
-
- if (expr_lval == lval_register)
- {
- ctx->regnum = reg;
- ctx->in_reg = 1;
- }
- else
- result = memaddr;
-
+ result = reg;
+ ctx->in_reg = 1;
break;
case DW_OP_breg0:
case DW_OP_breg31:
{
op_ptr = read_sleb128 (op_ptr, op_end, &offset);
- result = (ctx->read_reg) (ctx->baton, op - DW_OP_breg0,
- &expr_lval, &memaddr);
+ result = (ctx->read_reg) (ctx->baton, op - DW_OP_breg0);
result += offset;
}
break;
{
op_ptr = read_uleb128 (op_ptr, op_end, ®);
op_ptr = read_sleb128 (op_ptr, op_end, &offset);
- result = (ctx->read_reg) (ctx->baton, reg, &expr_lval, &memaddr);
+ result = (ctx->read_reg) (ctx->baton, reg);
result += offset;
}
break;
(ctx->get_frame_base) (ctx->baton, &datastart, &datalen);
dwarf_expr_eval (ctx, datastart, datalen);
result = dwarf_expr_fetch (ctx, 0);
- if (! ctx->in_reg)
+ if (ctx->in_reg)
+ result = (ctx->read_reg) (ctx->baton, result);
+ else
{
char *buf = alloca (TARGET_ADDR_BIT / TARGET_CHAR_BIT);
int bytes_read;
(ctx->read_mem) (ctx->baton, buf, result,
TARGET_ADDR_BIT / TARGET_CHAR_BIT);
- result = read_address (buf,
- buf + TARGET_ADDR_BIT / TARGET_CHAR_BIT,
- &bytes_read);
+ result = dwarf2_read_address (buf,
+ buf + (TARGET_ADDR_BIT
+ / TARGET_CHAR_BIT),
+ &bytes_read);
}
result = result + offset;
ctx->stack_len = before_stack_len;
(ctx->read_mem) (ctx->baton, buf, result,
TARGET_ADDR_BIT / TARGET_CHAR_BIT);
- result = read_address (buf,
- buf + TARGET_ADDR_BIT / TARGET_CHAR_BIT,
- &bytes_read);
+ result = dwarf2_read_address (buf,
+ buf + (TARGET_ADDR_BIT
+ / TARGET_CHAR_BIT),
+ &bytes_read);
}
break;
int bytes_read;
(ctx->read_mem) (ctx->baton, buf, result, *op_ptr++);
- result = read_address (buf,
- buf + TARGET_ADDR_BIT / TARGET_CHAR_BIT,
- &bytes_read);
+ result = dwarf2_read_address (buf,
+ buf + (TARGET_ADDR_BIT
+ / TARGET_CHAR_BIT),
+ &bytes_read);
}
break;
to all of the callback functions. */
void *baton;
- /* Return the value of register number REGNUM. LVALP will be set
- to the kind of lval this register is (generally lval_register
- for the current frame's registers or lval_memory for a register
- saved to the stack). For lval_memory ADDRP will be set to the
- saved location of the register. */
- CORE_ADDR (*read_reg) (void *baton, int regnum, enum lval_type *lvalp,
- CORE_ADDR *addrp);
+ /* Return the value of register number REGNUM. */
+ CORE_ADDR (*read_reg) (void *baton, int regnum);
/* Read LENGTH bytes at ADDR into BUF. */
void (*read_mem) (void *baton, char *buf, CORE_ADDR addr,
int recursion_depth, max_recursion_depth;
/* Non-zero if the result is in a register. The register number
- will be in REGNUM, and the result will be the contents of the
- register. */
+ will be on the expression stack. */
int in_reg;
-
- /* If the result is in a register, the register number. */
- int regnum;
};
struct dwarf_expr_context *new_dwarf_expr_context ();
ULONGEST * r);
unsigned char *read_sleb128 (unsigned char *buf, unsigned char *buf_end,
LONGEST * r);
+CORE_ADDR dwarf2_read_address (unsigned char *buf, unsigned char *buf_end,
+ int *bytes_read);
#endif
#define DWARF2_REG_TO_REGNUM(REG) (REG)
#endif
+/* A helper function for dealing with location lists. Given a
+ symbol baton (BATON) and a pc value (PC), find the appropriate
+ location expression, set *LOCEXPR_LENGTH, and return a pointer
+ to the beginning of the expression. Returns NULL on failure.
+
+ For now, only return the first matching location expression; there
+ can be more than one in the list. */
+
+static char *
+find_location_expression (struct dwarf2_loclist_baton *baton,
+ int *locexpr_length, CORE_ADDR pc)
+{
+ CORE_ADDR base_address = baton->base_address;
+ CORE_ADDR low, high;
+ char *loc_ptr, *buf_end;
+ unsigned int addr_size = TARGET_ADDR_BIT / TARGET_CHAR_BIT, length;
+ CORE_ADDR base_mask = ~(~(CORE_ADDR)1 << (addr_size * 8 - 1));
+
+ loc_ptr = baton->data;
+ buf_end = baton->data + baton->size;
+
+ while (1)
+ {
+ low = dwarf2_read_address (loc_ptr, buf_end, &length);
+ loc_ptr += length;
+ high = dwarf2_read_address (loc_ptr, buf_end, &length);
+ loc_ptr += length;
+
+ /* An end-of-list entry. */
+ if (low == 0 && high == 0)
+ return NULL;
+
+ /* A base-address-selection entry. */
+ if ((low & base_mask) == base_mask)
+ {
+ base_address = high;
+ continue;
+ }
+
+ /* Otherwise, a location expression entry. */
+ low += base_address;
+ high += base_address;
+
+ length = extract_unsigned_integer (loc_ptr, 2);
+ loc_ptr += 2;
+
+ if (pc >= low && pc < high)
+ {
+ *locexpr_length = length;
+ return loc_ptr;
+ }
+
+ loc_ptr += length;
+ }
+}
+
/* This is the baton used when performing dwarf2 expression
evaluation. */
struct dwarf_expr_baton
type will be returned in LVALP, and for lval_memory the register
save address will be returned in ADDRP. */
static CORE_ADDR
-dwarf_expr_read_reg (void *baton, int dwarf_regnum, enum lval_type *lvalp,
- CORE_ADDR *addrp)
+dwarf_expr_read_reg (void *baton, int dwarf_regnum)
{
struct dwarf_expr_baton *debaton = (struct dwarf_expr_baton *) baton;
- CORE_ADDR result;
+ CORE_ADDR result, save_addr;
+ enum lval_type lval_type;
char *buf;
int optimized, regnum, realnum, regsize;
regsize = register_size (current_gdbarch, regnum);
buf = (char *) alloca (regsize);
- frame_register (debaton->frame, regnum, &optimized, lvalp, addrp, &realnum,
- buf);
+ frame_register (debaton->frame, regnum, &optimized, &lval_type, &save_addr,
+ &realnum, buf);
result = extract_address (buf, regsize);
return result;
get_frame_base_address(), and then implement a dwarf2 specific
this_base method. */
struct symbol *framefunc;
- struct dwarf2_locexpr_baton *symbaton;
struct dwarf_expr_baton *debaton = (struct dwarf_expr_baton *) baton;
+
framefunc = get_frame_function (debaton->frame);
- symbaton = SYMBOL_LOCATION_BATON (framefunc);
- *start = symbaton->data;
- *length = symbaton->size;
+
+ if (SYMBOL_LOCATION_FUNCS (framefunc) == &dwarf2_loclist_funcs)
+ {
+ struct dwarf2_loclist_baton *symbaton;
+ symbaton = SYMBOL_LOCATION_BATON (framefunc);
+ *start = find_location_expression (symbaton, length,
+ get_frame_pc (debaton->frame));
+ }
+ else
+ {
+ struct dwarf2_locexpr_baton *symbaton;
+ symbaton = SYMBOL_LOCATION_BATON (framefunc);
+ *length = symbaton->size;
+ *start = symbaton->data;
+ }
+
+ if (*start == NULL)
+ error ("Could not find the frame base for \"%s\".",
+ SYMBOL_NATURAL_NAME (framefunc));
}
/* Using the objfile specified in BATON, find the address for the
struct dwarf_expr_baton baton;
struct dwarf_expr_context *ctx;
+ if (size == 0)
+ {
+ retval = allocate_value (SYMBOL_TYPE (var));
+ VALUE_LVAL (retval) = not_lval;
+ VALUE_OPTIMIZED_OUT (retval) = 1;
+ }
+
baton.frame = frame;
baton.objfile = objfile;
ctx->get_tls_address = dwarf_expr_tls_address;
dwarf_expr_eval (ctx, data, size);
-
- retval = allocate_value (SYMBOL_TYPE (var));
- VALUE_BFD_SECTION (retval) = SYMBOL_BFD_SECTION (var);
+ result = dwarf_expr_fetch (ctx, 0);
if (ctx->in_reg)
- {
- store_unsigned_integer (VALUE_CONTENTS_RAW (retval),
- TYPE_LENGTH (SYMBOL_TYPE (var)),
- dwarf_expr_fetch (ctx, 0));
- VALUE_LVAL (retval) = lval_register;
- VALUE_REGNO (retval) = ctx->regnum;
- }
+ retval = value_from_register (SYMBOL_TYPE (var), result, frame);
else
{
- result = dwarf_expr_fetch (ctx, 0);
+ retval = allocate_value (SYMBOL_TYPE (var));
+ VALUE_BFD_SECTION (retval) = SYMBOL_BFD_SECTION (var);
+
VALUE_LVAL (retval) = lval_memory;
VALUE_LAZY (retval) = 1;
VALUE_ADDRESS (retval) = result;
/* Reads from registers do require a frame. */
static CORE_ADDR
-needs_frame_read_reg (void *baton, int regnum, enum lval_type *lvalp,
- CORE_ADDR *addrp)
+needs_frame_read_reg (void *baton, int regnum)
{
struct needs_frame_baton *nf_baton = baton;
nf_baton->needs_frame = 1;
return baton.needs_frame;
}
+static void
+dwarf2_tracepoint_var_ref (struct symbol * symbol, struct agent_expr * ax,
+ struct axs_value * value, unsigned char *data,
+ int size)
+{
+ if (size == 0)
+ error ("Symbol \"%s\" has been optimized out.",
+ SYMBOL_PRINT_NAME (symbol));
+ if (size == 1
+ && data[0] >= DW_OP_reg0
+ && data[0] <= DW_OP_reg31)
+ {
+ value->kind = axs_lvalue_register;
+ value->u.reg = data[0] - DW_OP_reg0;
+ }
+ else if (data[0] == DW_OP_regx)
+ {
+ ULONGEST reg;
+ read_uleb128 (data + 1, data + size, ®);
+ value->kind = axs_lvalue_register;
+ value->u.reg = reg;
+ }
+ else if (data[0] == DW_OP_fbreg)
+ {
+ /* And this is worse than just minimal; we should honor the frame base
+ as above. */
+ int frame_reg;
+ LONGEST frame_offset;
+ unsigned char *buf_end;
+
+ buf_end = read_sleb128 (data + 1, data + size, &frame_offset);
+ if (buf_end != data + size)
+ error ("Unexpected opcode after DW_OP_fbreg for symbol \"%s\".",
+ SYMBOL_PRINT_NAME (symbol));
+
+ TARGET_VIRTUAL_FRAME_POINTER (ax->scope, &frame_reg, &frame_offset);
+ ax_reg (ax, frame_reg);
+ ax_const_l (ax, frame_offset);
+ ax_simple (ax, aop_add);
+ ax_const_l (ax, frame_offset);
+ ax_simple (ax, aop_add);
+ value->kind = axs_lvalue_memory;
+ }
+ else
+ error ("Unsupported DWARF opcode in the location of \"%s\".",
+ SYMBOL_PRINT_NAME (symbol));
+}
\f
/* Return the value of SYMBOL in FRAME using the DWARF-2 expression
evaluator to calculate the location. */
publicly available stub with tracepoint support for me to test
against. When there is one this function should be revisited. */
-void
+static void
locexpr_tracepoint_var_ref (struct symbol * symbol, struct agent_expr * ax,
struct axs_value * value)
{
struct dwarf2_locexpr_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol);
- if (dlbaton->size == 0)
- error ("Symbol \"%s\" has been optimized out.",
- SYMBOL_PRINT_NAME (symbol));
-
- if (dlbaton->size == 1
- && dlbaton->data[0] >= DW_OP_reg0
- && dlbaton->data[0] <= DW_OP_reg31)
- {
- value->kind = axs_lvalue_register;
- value->u.reg = dlbaton->data[0] - DW_OP_reg0;
- }
- else if (dlbaton->data[0] == DW_OP_regx)
- {
- ULONGEST reg;
- read_uleb128 (dlbaton->data + 1, dlbaton->data + dlbaton->size,
- ®);
- value->kind = axs_lvalue_register;
- value->u.reg = reg;
- }
- else if (dlbaton->data[0] == DW_OP_fbreg)
- {
- /* And this is worse than just minimal; we should honor the frame base
- as above. */
- int frame_reg;
- LONGEST frame_offset;
- unsigned char *buf_end;
-
- buf_end = read_sleb128 (dlbaton->data + 1, dlbaton->data + dlbaton->size,
- &frame_offset);
- if (buf_end != dlbaton->data + dlbaton->size)
- error ("Unexpected opcode after DW_OP_fbreg for symbol \"%s\".",
- SYMBOL_PRINT_NAME (symbol));
-
- TARGET_VIRTUAL_FRAME_POINTER (ax->scope, &frame_reg, &frame_offset);
- ax_reg (ax, frame_reg);
- ax_const_l (ax, frame_offset);
- ax_simple (ax, aop_add);
-
- ax_const_l (ax, frame_offset);
- ax_simple (ax, aop_add);
- value->kind = axs_lvalue_memory;
- }
- else
- error ("Unsupported DWARF opcode in the location of \"%s\".",
- SYMBOL_PRINT_NAME (symbol));
+ dwarf2_tracepoint_var_ref (symbol, ax, value, dlbaton->data, dlbaton->size);
}
/* The set of location functions used with the DWARF-2 expression
locexpr_describe_location,
locexpr_tracepoint_var_ref
};
+
+
+/* Wrapper functions for location lists. These generally find
+ the appropriate location expression and call something above. */
+
+/* Return the value of SYMBOL in FRAME using the DWARF-2 expression
+ evaluator to calculate the location. */
+static struct value *
+loclist_read_variable (struct symbol *symbol, struct frame_info *frame)
+{
+ struct dwarf2_loclist_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol);
+ struct value *val;
+ unsigned char *data;
+ int size;
+
+ data = find_location_expression (dlbaton, &size,
+ frame ? get_frame_pc (frame) : 0);
+ if (data == NULL)
+ error ("Variable \"%s\" is not available.", SYMBOL_NATURAL_NAME (symbol));
+
+ val = dwarf2_evaluate_loc_desc (symbol, frame, data, size, dlbaton->objfile);
+
+ return val;
+}
+
+/* Return non-zero iff we need a frame to evaluate SYMBOL. */
+static int
+loclist_read_needs_frame (struct symbol *symbol)
+{
+ /* If there's a location list, then assume we need to have a frame
+ to choose the appropriate location expression. With tracking of
+ global variables this is not necessarily true, but such tracking
+ is disabled in GCC at the moment until we figure out how to
+ represent it. */
+
+ return 1;
+}
+
+/* Print a natural-language description of SYMBOL to STREAM. */
+static int
+loclist_describe_location (struct symbol *symbol, struct ui_file *stream)
+{
+ /* FIXME: Could print the entire list of locations. */
+ fprintf_filtered (stream, "a variable with multiple locations");
+ return 1;
+}
+
+/* Describe the location of SYMBOL as an agent value in VALUE, generating
+ any necessary bytecode in AX. */
+static void
+loclist_tracepoint_var_ref (struct symbol * symbol, struct agent_expr * ax,
+ struct axs_value * value)
+{
+ struct dwarf2_loclist_baton *dlbaton = SYMBOL_LOCATION_BATON (symbol);
+ unsigned char *data;
+ int size;
+
+ data = find_location_expression (dlbaton, &size, ax->scope);
+ if (data == NULL)
+ error ("Variable \"%s\" is not available.", SYMBOL_NATURAL_NAME (symbol));
+
+ dwarf2_tracepoint_var_ref (symbol, ax, value, data, size);
+}
+
+/* The set of location functions used with the DWARF-2 expression
+ evaluator and location lists. */
+struct location_funcs dwarf2_loclist_funcs = {
+ loclist_read_variable,
+ loclist_read_needs_frame,
+ loclist_describe_location,
+ loclist_tracepoint_var_ref
+};
/* This header is private to the DWARF-2 reader. It is shared between
dwarf2read.c and dwarf2loc.c. */
-/* The symbol location baton type used by the DWARF-2 reader (i.e.
- SYMBOL_LOCATION_BATON for a LOC_COMPUTED symbol). */
+/* The symbol location baton types used by the DWARF-2 reader (i.e.
+ SYMBOL_LOCATION_BATON for a LOC_COMPUTED symbol). "struct
+ dwarf2_locexpr_baton" is for a symbol with a single location
+ expression; "struct dwarf2_loclist_baton" is for a symbol with a
+ location list. */
struct dwarf2_locexpr_baton
{
+ /* Pointer to the start of the location expression. */
unsigned char *data;
+
+ /* Length of the location expression. */
unsigned short size;
+
+ /* The objfile containing the symbol whose location we're computing. */
+ struct objfile *objfile;
+};
+
+struct dwarf2_loclist_baton
+{
+ /* The initial base address for the location list, based on the compilation
+ unit. */
+ CORE_ADDR base_address;
+
+ /* Pointer to the start of the location list. */
+ unsigned char *data;
+
+ /* Length of the location list. */
+ unsigned short size;
+
+ /* The objfile containing the symbol whose location we're computing. */
struct objfile *objfile;
};
extern struct location_funcs dwarf2_locexpr_funcs;
+extern struct location_funcs dwarf2_loclist_funcs;
#endif
#include "bcache.h"
#include "dwarf2expr.h"
#include "dwarf2loc.h"
+#include "cp-support.h"
#include <fcntl.h>
#include "gdb_string.h"
struct abbrev_info *dwarf2_abbrevs[ABBREV_HASH_SIZE];
- /* Pointer to the DIE associated with the compilation unit. */
+ /* Base address of this compilation unit. */
- struct die_info *die;
+ CORE_ADDR base_address;
+
+ /* Non-zero if base_address has been set. */
+
+ int base_known;
};
/* The line number information for a compilation unit (found in the
static char *dwarf_str_buffer;
static char *dwarf_macinfo_buffer;
static char *dwarf_ranges_buffer;
+static char *dwarf_loc_buffer;
/* A zeroed version of a partial die for initialization purposes. */
static struct partial_die_info zeroed_partial_die;
unsigned int dwarf_ranges_size;
+ /* Pointer to start of dwarf locations buffer for the objfile. */
+
+ char *dwarf_loc_buffer;
+
+ /* Size of dwarf locations buffer for the objfile. */
+
+ unsigned int dwarf_loc_size;
};
#define PST_PRIVATE(p) ((struct dwarf2_pinfo *)(p)->read_symtab_private)
#define DWARF_MACINFO_SIZE(p) (PST_PRIVATE(p)->dwarf_macinfo_size)
#define DWARF_RANGES_BUFFER(p) (PST_PRIVATE(p)->dwarf_ranges_buffer)
#define DWARF_RANGES_SIZE(p) (PST_PRIVATE(p)->dwarf_ranges_size)
+#define DWARF_LOC_BUFFER(p) (PST_PRIVATE(p)->dwarf_loc_buffer)
+#define DWARF_LOC_SIZE(p) (PST_PRIVATE(p)->dwarf_loc_size)
/* Maintain an array of referenced fundamental types for the current
compilation unit being read. For DWARF version 1, we have to construct
static char *dwarf2_linkage_name (struct die_info *);
+static char *dwarf2_name (struct die_info *die);
+
+static struct die_info *dwarf2_extension (struct die_info *die);
+
static char *dwarf_tag_name (unsigned int);
static char *dwarf_attr_name (unsigned int);
dwarf_frame_offset = 0;
dwarf_eh_frame_offset = 0;
dwarf_ranges_offset = 0;
+ dwarf_loc_offset = 0;
bfd_map_over_sections (abfd, dwarf2_locate_sections, NULL);
if (dwarf_info_offset && dwarf_abbrev_offset)
else
dwarf_ranges_buffer = NULL;
+ if (dwarf_loc_offset)
+ dwarf_loc_buffer = dwarf2_read_section (objfile,
+ dwarf_loc_offset,
+ dwarf_loc_size,
+ dwarf_loc_section);
+ else
+ dwarf_loc_buffer = NULL;
+
if (mainline
|| (objfile->global_psymbols.size == 0
&& objfile->static_psymbols.size == 0))
DWARF_MACINFO_SIZE (pst) = dwarf_macinfo_size;
DWARF_RANGES_BUFFER (pst) = dwarf_ranges_buffer;
DWARF_RANGES_SIZE (pst) = dwarf_ranges_size;
+ DWARF_LOC_BUFFER (pst) = dwarf_loc_buffer;
+ DWARF_LOC_SIZE (pst) = dwarf_loc_size;
baseaddr = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
/* Store the function that reads in the rest of the symbol table */
char *info_ptr;
struct symtab *symtab;
struct cleanup *back_to;
+ struct attribute *attr;
/* Set local variables from the partial symbol table info. */
offset = DWARF_INFO_OFFSET (pst);
dwarf_macinfo_size = DWARF_MACINFO_SIZE (pst);
dwarf_ranges_buffer = DWARF_RANGES_BUFFER (pst);
dwarf_ranges_size = DWARF_RANGES_SIZE (pst);
+ dwarf_loc_buffer = DWARF_LOC_BUFFER (pst);
+ dwarf_loc_size = DWARF_LOC_SIZE (pst);
baseaddr = ANOFFSET (pst->section_offsets, SECT_OFF_TEXT (objfile));
cu_header_offset = offset;
info_ptr = dwarf_info_buffer + offset;
make_cleanup_free_die_list (dies);
+ /* Find the base address of the compilation unit for range lists and
+ location lists. It will normally be specified by DW_AT_low_pc.
+ In DWARF-3 draft 4, the base address could be overridden by
+ DW_AT_entry_pc. It's been removed, but GCC still uses this for
+ compilation units with discontinuous ranges. */
+
+ cu_header.base_known = 0;
+ cu_header.base_address = 0;
+
+ attr = dwarf_attr (dies, DW_AT_entry_pc);
+ if (attr)
+ {
+ cu_header.base_address = DW_ADDR (attr);
+ cu_header.base_known = 1;
+ }
+ else
+ {
+ attr = dwarf_attr (dies, DW_AT_low_pc);
+ if (attr)
+ {
+ cu_header.base_address = DW_ADDR (attr);
+ cu_header.base_known = 1;
+ }
+ }
+
/* Do line number decoding in read_file_scope () */
- cu_header.die = dies;
process_die (dies, objfile, &cu_header);
if (!dwarf2_get_pc_bounds (dies, &lowpc, &highpc, objfile, &cu_header))
case DW_TAG_common_inclusion:
break;
case DW_TAG_namespace:
+ if (!processing_has_namespace_info)
+ {
+ processing_has_namespace_info = 1;
+ processing_current_namespace = "";
+ }
read_namespace (die, objfile, cu_header);
break;
case DW_TAG_imported_declaration:
shouldn't in the C++ case, but conceivably could in the
Fortran case, so we'll have to replace this gdb_assert if
Fortran compilers start generating that info. */
+ if (!processing_has_namespace_info)
+ {
+ processing_has_namespace_info = 1;
+ processing_current_namespace = "";
+ }
gdb_assert (!die->has_children);
break;
default:
.debug_renges section. */
unsigned int offset = DW_UNSND (attr);
/* Base address selection entry. */
- CORE_ADDR base = 0;
- int found_base = 0;
+ CORE_ADDR base;
+ int found_base;
int dummy;
unsigned int i;
char *buffer;
CORE_ADDR marker;
int low_set;
- /* The applicable base address is determined by (1) the closest
- preceding base address selection entry in the range list or
- (2) the DW_AT_low_pc of the compilation unit. */
-
- /* ??? Was in dwarf3 draft4, and has since been removed.
- GCC still uses it though. */
- attr = dwarf_attr (cu_header->die, DW_AT_entry_pc);
- if (attr)
- {
- base = DW_ADDR (attr);
- found_base = 1;
- }
-
- if (!found_base)
- {
- attr = dwarf_attr (cu_header->die, DW_AT_low_pc);
- if (attr)
- {
- base = DW_ADDR (attr);
- found_base = 1;
- }
- }
-
+ found_base = cu_header->base_known;
+ base = cu_header->base_address;
buffer = dwarf_ranges_buffer + offset;
-
/* Read in the largest possible address. */
marker = read_address (obfd, buffer, cu_header, &dummy);
if ((marker & mask) == mask)
/* Read a C++ namespace. */
-/* FIXME: carlton/2002-10-16: For now, we don't actually do anything
- useful with the namespace data: we just process its children. */
-
static void
read_namespace (struct die_info *die, struct objfile *objfile,
const struct comp_unit_head *cu_header)
{
+ const char *previous_namespace = processing_current_namespace;
+ const char *name = NULL;
+ int is_anonymous;
+ struct die_info *current_die;
+
+ /* Loop through the extensions until we find a name. */
+
+ for (current_die = die;
+ current_die != NULL;
+ current_die = dwarf2_extension (die))
+ {
+ name = dwarf2_name (current_die);
+ if (name != NULL)
+ break;
+ }
+
+ /* Is it an anonymous namespace? */
+
+ is_anonymous = (name == NULL);
+ if (is_anonymous)
+ name = "(anonymous namespace)";
+
+ /* Now build the name of the current namespace. */
+
+ if (previous_namespace[0] == '\0')
+ {
+ processing_current_namespace = name;
+ }
+ else
+ {
+ /* We need temp_name around because processing_current_namespace
+ is a const char *. */
+ char *temp_name = alloca (strlen (previous_namespace)
+ + 2 + strlen(name) + 1);
+ strcpy (temp_name, previous_namespace);
+ strcat (temp_name, "::");
+ strcat (temp_name, name);
+
+ processing_current_namespace = temp_name;
+ }
+
+ /* If it's an anonymous namespace that we're seeing for the first
+ time, add a using directive. */
+
+ if (is_anonymous && dwarf_attr (die, DW_AT_extension) == NULL)
+ cp_add_using_directive (processing_current_namespace,
+ strlen (previous_namespace),
+ strlen (processing_current_namespace));
+
if (die->has_children)
{
struct die_info *child_die = die->next;
child_die = sibling_die (child_die);
}
}
+
+ processing_current_namespace = previous_namespace;
}
/* Extract all information from a DW_TAG_pointer_type DIE and add to
return NULL;
}
+/* Get name of a die, return NULL if not found. */
+
+static char *
+dwarf2_name (struct die_info *die)
+{
+ struct attribute *attr;
+
+ attr = dwarf_attr (die, DW_AT_name);
+ if (attr && DW_STRING (attr))
+ return DW_STRING (attr);
+ return NULL;
+}
+
+/* Return the die that this die in an extension of, or NULL if there
+ is none. */
+
+static struct die_info *
+dwarf2_extension (struct die_info *die)
+{
+ struct attribute *attr;
+ struct die_info *extension_die;
+ unsigned int ref;
+
+ attr = dwarf_attr (die, DW_AT_extension);
+ if (attr == NULL)
+ return NULL;
+
+ ref = dwarf2_get_ref_die_offset (attr);
+ extension_die = follow_die_ref (ref);
+ if (!extension_die)
+ {
+ error ("Dwarf Error: Cannot find referent at offset %d.", ref);
+ }
+
+ return extension_die;
+}
+
/* Convert a DIE tag into its string name. */
static char *
const struct comp_unit_head *cu_header,
struct objfile *objfile)
{
- struct dwarf2_locexpr_baton *baton;
-
- /* When support for location lists is added, this will go away. */
- if (!attr_form_is_block (attr))
+ if (attr->form == DW_FORM_data4 || attr->form == DW_FORM_data8)
{
- dwarf2_complex_location_expr_complaint ();
- return;
- }
+ struct dwarf2_loclist_baton *baton;
- baton = obstack_alloc (&objfile->symbol_obstack,
- sizeof (struct dwarf2_locexpr_baton));
- baton->objfile = objfile;
+ baton = obstack_alloc (&objfile->symbol_obstack,
+ sizeof (struct dwarf2_loclist_baton));
+ baton->objfile = objfile;
- /* Note that we're just copying the block's data pointer here, not
- the actual data. We're still pointing into the dwarf_info_buffer
- for SYM's objfile; right now we never release that buffer, but
- when we do clean up properly this may need to change. */
- baton->size = DW_BLOCK (attr)->size;
- baton->data = DW_BLOCK (attr)->data;
+ /* We don't know how long the location list is, but make sure we
+ don't run off the edge of the section. */
+ baton->size = dwarf_loc_size - DW_UNSND (attr);
+ baton->data = dwarf_loc_buffer + DW_UNSND (attr);
+ baton->base_address = cu_header->base_address;
+ if (cu_header->base_known == 0)
+ complaint (&symfile_complaints,
+ "Location list used without specifying the CU base address.");
- SYMBOL_LOCATION_FUNCS (sym) = &dwarf2_locexpr_funcs;
- SYMBOL_LOCATION_BATON (sym) = baton;
+ SYMBOL_LOCATION_FUNCS (sym) = &dwarf2_loclist_funcs;
+ SYMBOL_LOCATION_BATON (sym) = baton;
+ }
+ else
+ {
+ struct dwarf2_locexpr_baton *baton;
+
+ baton = obstack_alloc (&objfile->symbol_obstack,
+ sizeof (struct dwarf2_locexpr_baton));
+ baton->objfile = objfile;
+
+ if (attr_form_is_block (attr))
+ {
+ /* Note that we're just copying the block's data pointer
+ here, not the actual data. We're still pointing into the
+ dwarf_info_buffer for SYM's objfile; right now we never
+ release that buffer, but when we do clean up properly
+ this may need to change. */
+ baton->size = DW_BLOCK (attr)->size;
+ baton->data = DW_BLOCK (attr)->data;
+ }
+ else
+ {
+ dwarf2_invalid_attrib_class_complaint ("location description",
+ SYMBOL_NATURAL_NAME (sym));
+ baton->size = 0;
+ baton->data = NULL;
+ }
+
+ SYMBOL_LOCATION_FUNCS (sym) = &dwarf2_locexpr_funcs;
+ SYMBOL_LOCATION_BATON (sym) = baton;
+ }
}
#ifndef EVENT_TOP_H
#define EVENT_TOP_H
+struct cmd_list_element;
+
/* Stack for prompts. Each prompt is composed as a prefix, a prompt
and a suffix. The prompt to be displayed at any given time is the
one on top of the stack. A stack is necessary because of cases in
#else
while (1)
{
- stop_soon_quietly = 1; /* Make wait_for_inferior be quiet */
+ /* Make wait_for_inferior be quiet */
+ stop_soon = STOP_QUIETLY;
wait_for_inferior ();
if (stop_signal != TARGET_SIGNAL_TRAP)
{
}
}
#endif /* STARTUP_INFERIOR */
- stop_soon_quietly = 0;
+ stop_soon = NO_STOP_QUIETLY;
}
#include "command.h"
#include "gdbcmd.h"
+/* We keep a cache of stack frames, each of which is a "struct
+ frame_info". The innermost one gets allocated (in
+ wait_for_inferior) each time the inferior stops; current_frame
+ points to it. Additional frames get allocated (in get_prev_frame)
+ as needed, and are chained through the next and prev fields. Any
+ time that the frame cache becomes invalid (most notably when we
+ execute something, but also if we change how we interpret the
+ frames (e.g. "set heuristic-fence-post" in mips-tdep.c, or anything
+ which reads new symbols)), we should call reinit_frame_cache. */
+
+struct frame_info
+{
+ /* Level of this frame. The inner-most (youngest) frame is at level
+ 0. As you move towards the outer-most (oldest) frame, the level
+ increases. This is a cached value. It could just as easily be
+ computed by counting back from the selected frame to the inner
+ most frame. */
+ /* NOTE: cagney/2002-04-05: Perhaphs a level of ``-1'' should be
+ reserved to indicate a bogus frame - one that has been created
+ just to keep GDB happy (GDB always needs a frame). For the
+ moment leave this as speculation. */
+ int level;
+
+ /* The frame's type. */
+ /* FIXME: cagney/2003-04-02: Should instead be returning
+ ->unwind->type. Unfortunatly, legacy code is still explicitly
+ setting the type using the method deprecated_set_frame_type.
+ Eliminate that method and this field can be eliminated. */
+ enum frame_type type;
+
+ /* For each register, address of where it was saved on entry to the
+ frame, or zero if it was not saved on entry to this frame. This
+ includes special registers such as pc and fp saved in special
+ ways in the stack frame. The SP_REGNUM is even more special, the
+ address here is the sp for the previous frame, not the address
+ where the sp was saved. */
+ /* Allocated by frame_saved_regs_zalloc () which is called /
+ initialized by DEPRECATED_FRAME_INIT_SAVED_REGS(). */
+ CORE_ADDR *saved_regs; /*NUM_REGS + NUM_PSEUDO_REGS*/
+
+ /* Anything extra for this structure that may have been defined in
+ the machine dependent files. */
+ /* Allocated by frame_extra_info_zalloc () which is called /
+ initialized by DEPRECATED_INIT_EXTRA_FRAME_INFO */
+ struct frame_extra_info *extra_info;
+
+ /* If dwarf2 unwind frame informations is used, this structure holds
+ all related unwind data. */
+ struct context *context;
+
+ /* The frame's low-level unwinder and corresponding cache. The
+ low-level unwinder is responsible for unwinding register values
+ for the previous frame. The low-level unwind methods are
+ selected based on the presence, or otherwize, of register unwind
+ information such as CFI. */
+ void *prologue_cache;
+ const struct frame_unwind *unwind;
+
+ /* Cached copy of the previous frame's resume address. */
+ struct {
+ int p;
+ CORE_ADDR value;
+ } prev_pc;
+
+ /* Cached copy of the previous frame's function address. */
+ struct
+ {
+ CORE_ADDR addr;
+ int p;
+ } prev_func;
+
+ /* This frame's ID. */
+ struct
+ {
+ int p;
+ struct frame_id value;
+ } this_id;
+
+ /* The frame's high-level base methods, and corresponding cache.
+ The high level base methods are selected based on the frame's
+ debug info. */
+ const struct frame_base *base;
+ void *base_cache;
+
+ /* Pointers to the next (down, inner, younger) and previous (up,
+ outer, older) frame_info's in the frame cache. */
+ struct frame_info *next; /* down, inner, younger */
+ int prev_p;
+ struct frame_info *prev; /* up, outer, older */
+};
+
/* Flag to control debugging. */
static int frame_debug;
static int backtrace_below_main;
+static void
+fprint_frame_id (struct ui_file *file, struct frame_id id)
+{
+ fprintf_unfiltered (file, "{stack=0x%s,code=0x%s}",
+ paddr_nz (id.stack_addr),
+ paddr_nz (id.code_addr));
+}
+
+static void
+fprint_frame_type (struct ui_file *file, enum frame_type type)
+{
+ switch (type)
+ {
+ case UNKNOWN_FRAME:
+ fprintf_unfiltered (file, "UNKNOWN_FRAME");
+ return;
+ case NORMAL_FRAME:
+ fprintf_unfiltered (file, "NORMAL_FRAME");
+ return;
+ case DUMMY_FRAME:
+ fprintf_unfiltered (file, "DUMMY_FRAME");
+ return;
+ case SIGTRAMP_FRAME:
+ fprintf_unfiltered (file, "SIGTRAMP_FRAME");
+ return;
+ default:
+ fprintf_unfiltered (file, "<unknown type>");
+ return;
+ };
+}
+
+static void
+fprint_frame (struct ui_file *file, struct frame_info *fi)
+{
+ if (fi == NULL)
+ {
+ fprintf_unfiltered (file, "<NULL frame>");
+ return;
+ }
+ fprintf_unfiltered (file, "{");
+ fprintf_unfiltered (file, "level=%d", fi->level);
+ fprintf_unfiltered (file, ",");
+ fprintf_unfiltered (file, "type=");
+ fprint_frame_type (file, fi->type);
+ fprintf_unfiltered (file, ",");
+ fprintf_unfiltered (file, "unwind=");
+ if (fi->unwind != NULL)
+ gdb_print_host_address (fi->unwind, file);
+ else
+ fprintf_unfiltered (file, "<unknown>");
+ fprintf_unfiltered (file, ",");
+ fprintf_unfiltered (file, "pc=");
+ if (fi->next != NULL && fi->next->prev_pc.p)
+ fprintf_unfiltered (file, "0x%s", paddr_nz (fi->next->prev_pc.value));
+ else
+ fprintf_unfiltered (file, "<unknown>");
+ fprintf_unfiltered (file, ",");
+ fprintf_unfiltered (file, "id=");
+ if (fi->this_id.p)
+ fprint_frame_id (file, fi->this_id.value);
+ else
+ fprintf_unfiltered (file, "<unknown>");
+ fprintf_unfiltered (file, ",");
+ fprintf_unfiltered (file, "func=");
+ if (fi->next != NULL && fi->next->prev_func.p)
+ fprintf_unfiltered (file, "0x%s", paddr_nz (fi->next->prev_func.addr));
+ else
+ fprintf_unfiltered (file, "<unknown>");
+ fprintf_unfiltered (file, "}");
+}
+
/* Return a frame uniq ID that can be used to, later, re-find the
frame. */
{
return null_frame_id;
}
- if (!fi->id_p)
+ if (!fi->this_id.p)
{
gdb_assert (!legacy_frame_p (current_gdbarch));
+ if (frame_debug)
+ fprintf_unfiltered (gdb_stdlog, "{ get_frame_id (fi=%d) ",
+ fi->level);
+ /* Find the unwinder. */
+ if (fi->unwind == NULL)
+ {
+ fi->unwind = frame_unwind_find_by_pc (current_gdbarch,
+ get_frame_pc (fi));
+ /* FIXME: cagney/2003-04-02: Rather than storing the frame's
+ type in the frame, the unwinder's type should be returned
+ directly. Unfortunatly, legacy code, called by
+ legacy_get_prev_frame, explicitly set the frames type
+ using the method deprecated_set_frame_type(). */
+ gdb_assert (fi->unwind->type != UNKNOWN_FRAME);
+ fi->type = fi->unwind->type;
+ }
/* Find THIS frame's ID. */
- fi->unwind->this_id (fi->next, &fi->prologue_cache, &fi->id);
- fi->id_p = 1;
- /* FIXME: cagney/2002-12-18: Instead of this hack, should only
- store the frame ID in PREV_FRAME. */
- fi->frame = fi->id.base;
+ fi->unwind->this_id (fi->next, &fi->prologue_cache, &fi->this_id.value);
+ fi->this_id.p = 1;
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame_id (gdb_stdlog, fi->this_id.value);
+ fprintf_unfiltered (gdb_stdlog, " }\n");
+ }
}
- return frame_id_build (fi->frame, get_frame_pc (fi));
+ return fi->this_id.value;
}
const struct frame_id null_frame_id; /* All zeros. */
struct frame_id
-frame_id_build (CORE_ADDR base, CORE_ADDR func_or_pc)
+frame_id_build (CORE_ADDR stack_addr, CORE_ADDR code_addr)
{
struct frame_id id;
- id.base = base;
- id.pc = func_or_pc;
+ id.stack_addr = stack_addr;
+ id.code_addr = code_addr;
return id;
}
int
frame_id_p (struct frame_id l)
{
- /* The .func can be NULL but the .base cannot. */
- return (l.base != 0);
+ int p;
+ /* The .code can be NULL but the .stack cannot. */
+ p = (l.stack_addr != 0);
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "{ frame_id_p (l=");
+ fprint_frame_id (gdb_stdlog, l);
+ fprintf_unfiltered (gdb_stdlog, ") -> %d }\n", p);
+ }
+ return p;
}
int
frame_id_eq (struct frame_id l, struct frame_id r)
{
- /* If .base is different, the frames are different. */
- if (l.base != r.base)
- return 0;
- /* Add a test to check that the frame ID's are for the same function
- here. */
- return 1;
+ int eq;
+ if (l.stack_addr == 0 || r.stack_addr == 0)
+ /* Like a NaN, if either ID is invalid, the result is false. */
+ eq = 0;
+ else if (l.stack_addr != r.stack_addr)
+ /* If .stack addresses are different, the frames are different. */
+ eq = 0;
+ else if (l.code_addr == 0 || r.code_addr == 0)
+ /* A zero code addr is a wild card, always succeed. */
+ eq = 1;
+ else if (l.code_addr == r.code_addr)
+ /* The .stack and .code are identical, the ID's are identical. */
+ eq = 1;
+ else
+ /* FIXME: cagney/2003-04-06: This should be zero. Can't yet do
+ this because most frame ID's are not being initialized
+ correctly. */
+ eq = 1;
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "{ frame_id_eq (l=");
+ fprint_frame_id (gdb_stdlog, l);
+ fprintf_unfiltered (gdb_stdlog, ",r=");
+ fprint_frame_id (gdb_stdlog, r);
+ fprintf_unfiltered (gdb_stdlog, ") -> %d }\n", eq);
+ }
+ return eq;
}
int
frame_id_inner (struct frame_id l, struct frame_id r)
{
- /* Only return non-zero when strictly inner than. Note that, per
- comment in "frame.h", there is some fuzz here. Frameless
- functions are not strictly inner than (same .base but different
- .func). */
- return INNER_THAN (l.base, r.base);
+ int inner;
+ if (l.stack_addr == 0 || r.stack_addr == 0)
+ /* Like NaN, any operation involving an invalid ID always fails. */
+ inner = 0;
+ else
+ /* Only return non-zero when strictly inner than. Note that, per
+ comment in "frame.h", there is some fuzz here. Frameless
+ functions are not strictly inner than (same .stack but
+ different .code). */
+ inner = INNER_THAN (l.stack_addr, r.stack_addr);
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "{ frame_id_inner (l=");
+ fprint_frame_id (gdb_stdlog, l);
+ fprintf_unfiltered (gdb_stdlog, ",r=");
+ fprint_frame_id (gdb_stdlog, r);
+ fprintf_unfiltered (gdb_stdlog, ") -> %d }\n", inner);
+ }
+ return inner;
}
struct frame_info *
CORE_ADDR
frame_pc_unwind (struct frame_info *this_frame)
{
- if (!this_frame->pc_unwind_cache_p)
+ if (!this_frame->prev_pc.p)
{
CORE_ADDR pc;
if (gdbarch_unwind_pc_p (current_gdbarch))
}
else
internal_error (__FILE__, __LINE__, "No gdbarch_unwind_pc method");
- this_frame->pc_unwind_cache = pc;
- this_frame->pc_unwind_cache_p = 1;
+ this_frame->prev_pc.value = pc;
+ this_frame->prev_pc.p = 1;
+ if (frame_debug)
+ fprintf_unfiltered (gdb_stdlog,
+ "{ frame_pc_unwind (this_frame=%d) -> 0x%s }\n",
+ this_frame->level,
+ paddr_nz (this_frame->prev_pc.value));
}
- return this_frame->pc_unwind_cache;
+ return this_frame->prev_pc.value;
}
CORE_ADDR
{
fi->prev_func.p = 1;
fi->prev_func.addr = get_pc_function_start (frame_pc_unwind (fi));
+ if (frame_debug)
+ fprintf_unfiltered (gdb_stdlog,
+ "{ frame_func_unwind (fi=%d) -> 0x%s }\n",
+ fi->level, paddr_nz (fi->prev_func.addr));
}
return fi->prev_func.addr;
}
{
struct frame_unwind_cache *cache;
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog,
+ "{ frame_register_unwind (frame=%d,regnum=\"%s\",...) ",
+ frame->level, frame_map_regnum_to_name (regnum));
+ }
+
/* Require all but BUFFERP to be valid. A NULL BUFFERP indicates
that the value proper does not need to be fetched. */
gdb_assert (optimizedp != NULL);
detected the problem before calling here. */
gdb_assert (frame != NULL);
+ /* Find the unwinder. */
+ if (frame->unwind == NULL)
+ {
+ frame->unwind = frame_unwind_find_by_pc (current_gdbarch,
+ get_frame_pc (frame));
+ /* FIXME: cagney/2003-04-02: Rather than storing the frame's
+ type in the frame, the unwinder's type should be returned
+ directly. Unfortunatly, legacy code, called by
+ legacy_get_prev_frame, explicitly set the frames type using
+ the method deprecated_set_frame_type(). */
+ gdb_assert (frame->unwind->type != UNKNOWN_FRAME);
+ frame->type = frame->unwind->type;
+ }
+
/* Ask this frame to unwind its register. See comment in
"frame-unwind.h" for why NEXT frame and this unwind cace are
passed in. */
frame->unwind->prev_register (frame->next, &frame->prologue_cache, regnum,
optimizedp, lvalp, addrp, realnump, bufferp);
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "->");
+ fprintf_unfiltered (gdb_stdlog, " *optimizedp=%d", (*optimizedp));
+ fprintf_unfiltered (gdb_stdlog, " *lvalp=%d", (int) (*lvalp));
+ fprintf_unfiltered (gdb_stdlog, " *addrp=0x%s", paddr_nz ((*addrp)));
+ fprintf_unfiltered (gdb_stdlog, " *bufferp=");
+ if (bufferp == NULL)
+ fprintf_unfiltered (gdb_stdlog, "<NULL>");
+ else
+ {
+ int i;
+ const char *buf = bufferp;
+ fprintf_unfiltered (gdb_stdlog, "[");
+ for (i = 0; i < register_size (current_gdbarch, regnum); i++)
+ fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
+ fprintf_unfiltered (gdb_stdlog, "]");
+ }
+ fprintf_unfiltered (gdb_stdlog, " }\n");
+ }
}
void
/* Link this frame back to itself. The frame is self referential
(the unwound PC is the same as the pc), so make it so. */
frame->next = frame;
- /* Always unwind the PC as part of creating this frame. This
- ensures that the frame's PC points at something valid. */
- /* FIXME: cagney/2003-01-10: Problem here. Unwinding a sentinel
- frame's PC may require information such as the frame's thread's
- stop reason. Is it possible to get to that? */
- /* FIXME: cagney/2003-04-04: Once ->pc is eliminated, this
- assignment can go away. */
- frame->pc = frame_pc_unwind (frame);
/* Make the sentinel frame's ID valid, but invalid. That way all
comparisons with it should fail. */
- frame->id_p = 1;
- frame->id = null_frame_id;
+ frame->this_id.p = 1;
+ frame->this_id.value = null_frame_id;
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "{ create_sentinel_frame (...) -> ");
+ fprint_frame (gdb_stdlog, frame);
+ fprintf_unfiltered (gdb_stdlog, " }\n");
+ }
return frame;
}
void **this_prologue_cache,
struct frame_id *id)
{
- int fromleaf;
- CORE_ADDR base;
- CORE_ADDR pc;
-
- if (frame_relative_level (next_frame) < 0)
- {
- /* FIXME: cagney/2003-03-14: We've got the extra special case of
- unwinding a sentinel frame, the PC of which is pointing at a
- stack dummy. Fake up the dummy frame's ID using the same
- sequence as is found a traditional unwinder. */
- (*id) = frame_id_build (read_fp (), read_pc ());
- return;
- }
-
- /* Start out by assuming it's NULL. */
- (*id) = null_frame_id;
-
- if (frame_relative_level (next_frame) <= 0)
- /* FIXME: 2002-11-09: Frameless functions can occure anywhere in
- the frame chain, not just the inner most frame! The generic,
- per-architecture, frame code should handle this and the below
- should simply be removed. */
- fromleaf = FRAMELESS_FUNCTION_INVOCATION (next_frame);
- else
- fromleaf = 0;
-
- if (fromleaf)
- /* A frameless inner-most frame. The `FP' (which isn't an
- architecture frame-pointer register!) of the caller is the same
- as the callee. */
- /* FIXME: 2002-11-09: There isn't any reason to special case this
- edge condition. Instead the per-architecture code should hande
- it locally. */
- base = get_frame_base (next_frame);
- else
- {
- /* Two macros defined in tm.h specify the machine-dependent
- actions to be performed here.
-
- First, get the frame's chain-pointer.
-
- If that is zero, the frame is the outermost frame or a leaf
- called by the outermost frame. This means that if start
- calls main without a frame, we'll return 0 (which is fine
- anyway).
-
- Nope; there's a problem. This also returns when the current
- routine is a leaf of main. This is unacceptable. We move
- this to after the ffi test; I'd rather have backtraces from
- start go curfluy than have an abort called from main not show
- main. */
- gdb_assert (DEPRECATED_FRAME_CHAIN_P ());
- base = DEPRECATED_FRAME_CHAIN (next_frame);
-
- if (!frame_chain_valid (base, next_frame))
- return;
- }
- if (base == 0)
- return;
-
- /* FIXME: cagney/2002-06-08: This should probably return the frame's
- function and not the PC (a.k.a. resume address). */
- pc = frame_pc_unwind (next_frame);
- (*id) = frame_id_build (base, pc);
+ /* legacy_get_prev_frame() always sets ->this_id.p, hence this is
+ never needed. */
+ internal_error (__FILE__, __LINE__, "legacy_saved_regs_this_id() called");
}
const struct frame_unwind legacy_saved_regs_unwinder = {
{
struct frame_info *fi;
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog,
+ "{ create_new_frame (addr=0x%s, pc=0x%s) ",
+ paddr_nz (addr), paddr_nz (pc));
+ }
+
fi = frame_obstack_zalloc (sizeof (struct frame_info));
fi->next = create_sentinel_frame (current_regcache);
/* Select/initialize both the unwind function and the frame's type
based on the PC. */
- fi->unwind = frame_unwind_find_by_pc (current_gdbarch, fi->pc);
+ fi->unwind = frame_unwind_find_by_pc (current_gdbarch, pc);
if (fi->unwind->type != UNKNOWN_FRAME)
fi->type = fi->unwind->type;
else
fi->type = frame_type_from_pc (pc);
+ fi->this_id.p = 1;
deprecated_update_frame_base_hack (fi, addr);
deprecated_update_frame_pc_hack (fi, pc);
if (DEPRECATED_INIT_EXTRA_FRAME_INFO_P ())
DEPRECATED_INIT_EXTRA_FRAME_INFO (0, fi);
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, fi);
+ fprintf_unfiltered (gdb_stdlog, " }\n");
+ }
+
return fi;
}
current_frame = NULL; /* Invalidate cache */
select_frame (NULL);
annotate_frames_invalid ();
+ if (frame_debug)
+ fprintf_unfiltered (gdb_stdlog, "{ flush_cached_frames () }\n");
}
/* Flush the frame cache, and start a new one if necessary. */
struct frame_info *prev;
int fromleaf;
+ /* Don't frame_debug print legacy_get_prev_frame() here, just
+ confuses the output. */
+
/* Allocate the new frame.
There is no reason to worry about memory leaks, should the
prev->type = UNKNOWN_FRAME;
/* A legacy frame's ID is always computed here. Mark it as valid. */
- prev->id_p = 1;
+ prev->this_id.p = 1;
/* Handle sentinel frame unwind as a special case. */
if (this_frame->level < 0)
/* The allocated PREV_FRAME will be reclaimed when the frame
obstack is next purged. */
if (frame_debug)
- fprintf_unfiltered (gdb_stdlog,
- "Outermost frame - unwound PC zero\n");
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog,
+ " // unwound legacy PC zero }\n");
+ }
return NULL;
}
/* Set the unwind functions based on that identified PC. Ditto
for the "type" but strongly prefer the unwinder's frame type. */
- prev->unwind = frame_unwind_find_by_pc (current_gdbarch, prev->pc);
+ prev->unwind = frame_unwind_find_by_pc (current_gdbarch,
+ get_frame_pc (prev));
if (prev->unwind->type == UNKNOWN_FRAME)
- prev->type = frame_type_from_pc (prev->pc);
+ prev->type = frame_type_from_pc (get_frame_pc (prev));
else
prev->type = prev->unwind->type;
dummy ID from the next frame. Note that this method uses
frame_register_unwind to obtain the register values
needed to determine the dummy frame's ID. */
- prev->id = gdbarch_unwind_dummy_id (current_gdbarch, this_frame);
+ prev->this_id.value = gdbarch_unwind_dummy_id (current_gdbarch,
+ this_frame);
}
else
{
using the same sequence as is found a traditional
unwinder. Once all architectures supply the
unwind_dummy_id method, this code can go away. */
- prev->id = frame_id_build (read_fp (), read_pc ());
+ prev->this_id.value = frame_id_build (read_fp (), read_pc ());
}
/* Check that the unwound ID is valid. */
- if (!frame_id_p (prev->id))
+ if (!frame_id_p (prev->this_id.value))
{
if (frame_debug)
- fprintf_unfiltered (gdb_stdlog,
- "Outermost legacy sentinel frame - unwound frame ID invalid\n");
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog,
+ " // unwound legacy ID invalid }\n");
+ }
return NULL;
}
after the switch to storing the frame ID, instead of the
frame base, in the frame object. */
- /* FIXME: cagney/2002-12-18: Instead of this hack, should only
- store the frame ID in PREV_FRAME. */
- /* FIXME: cagney/2003-04-04: Once ->frame is eliminated, this
- assignment can go. */
- prev->frame = prev->id.base;
-
/* Link it in. */
this_frame->prev = prev;
{
DEPRECATED_INIT_EXTRA_FRAME_INFO (0, prev);
}
+
+ if (prev->type == NORMAL_FRAME)
+ prev->this_id.value.code_addr
+ = get_pc_function_start (prev->this_id.value.code_addr);
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, prev);
+ fprintf_unfiltered (gdb_stdlog, " } // legacy innermost frame\n");
+ }
return prev;
}
gdb_assert (DEPRECATED_FRAME_CHAIN_P ());
address = DEPRECATED_FRAME_CHAIN (this_frame);
- if (!frame_chain_valid (address, this_frame))
- return 0;
+ if (!legacy_frame_chain_valid (address, this_frame))
+ {
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog,
+ " // legacy frame chain invalid }\n");
+ }
+ return NULL;
+ }
}
if (address == 0)
- return 0;
+ {
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog,
+ " // legacy frame chain NULL }\n");
+ }
+ return NULL;
+ }
/* Link in the already allocated prev frame. */
this_frame->prev = prev;
{
this_frame->prev = NULL;
obstack_free (&frame_cache_obstack, prev);
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog,
+ " // legacy this.id == prev.id }\n");
+ }
return NULL;
}
if (prev->unwind->type != UNKNOWN_FRAME)
{
prev->type = prev->unwind->type;
+ if (prev->type == NORMAL_FRAME)
+ prev->this_id.value.code_addr
+ = get_pc_function_start (prev->this_id.value.code_addr);
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, prev);
+ fprintf_unfiltered (gdb_stdlog, " } // legacy with unwound type\n");
+ }
return prev;
}
go away. */
}
+ if (prev->type == NORMAL_FRAME)
+ prev->this_id.value.code_addr
+ = get_pc_function_start (prev->this_id.value.code_addr);
+
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, prev);
+ fprintf_unfiltered (gdb_stdlog, " } // legacy with confused type\n");
+ }
+
return prev;
}
{
struct frame_info *prev_frame;
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "{ get_prev_frame (this_frame=");
+ if (this_frame != NULL)
+ fprintf_unfiltered (gdb_stdlog, "%d", this_frame->level);
+ else
+ fprintf_unfiltered (gdb_stdlog, "<NULL>");
+ fprintf_unfiltered (gdb_stdlog, ") ");
+ }
+
/* Return the inner-most frame, when the caller passes in NULL. */
/* NOTE: cagney/2002-11-09: Not sure how this would happen. The
caller should have previously obtained a valid frame using
allow unwinds past main(), that just happens. */
{
if (frame_debug)
- fprintf_unfiltered (gdb_stdlog,
- "Outermost frame - inside main func.\n");
+ fprintf_unfiltered (gdb_stdlog, "-> NULL // inside main func }\n");
return NULL;
}
/* Only try to do the unwind once. */
if (this_frame->prev_p)
- return this_frame->prev;
+ {
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, this_frame->prev);
+ fprintf_unfiltered (gdb_stdlog, " // cached \n");
+ }
+ return this_frame->prev;
+ }
this_frame->prev_p = 1;
#if 0
&& inside_entry_file (get_frame_pc (this_frame)))
{
if (frame_debug)
- fprintf_unfiltered (gdb_stdlog,
- "Outermost frame - inside entry file\n");
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog, " // inside entry file }\n");
+ }
return NULL;
}
#endif
&& inside_entry_func (get_frame_pc (this_frame)))
{
if (frame_debug)
- fprintf_unfiltered (gdb_stdlog,
- "Outermost frame - inside entry func\n");
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog, "// inside entry func }\n");
+ }
return NULL;
}
if (legacy_frame_p (current_gdbarch))
{
prev_frame = legacy_get_prev_frame (this_frame);
- if (frame_debug && prev_frame == NULL)
- fprintf_unfiltered (gdb_stdlog,
- "Outermost frame - legacy_get_prev_frame NULL.\n");
return prev_frame;
}
if (this_frame->level >= 0 && !frame_id_p (get_frame_id (this_frame)))
{
if (frame_debug)
- fprintf_filtered (gdb_stdlog,
- "Outermost frame - this ID is NULL\n");
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog, " // this ID is NULL }\n");
+ }
return NULL;
}
because (well ignoring the PPC) a dummy frame can be located
using THIS_FRAME's frame ID. */
- /* FIXME: cagney/2003-04-04: Once ->pc is eliminated, this
- assignment can go away. */
- prev_frame->pc = frame_pc_unwind (this_frame);
- if (prev_frame->pc == 0)
+ if (frame_pc_unwind (this_frame) == 0)
{
/* The allocated PREV_FRAME will be reclaimed when the frame
obstack is next purged. */
if (frame_debug)
- fprintf_unfiltered (gdb_stdlog,
- "Outermost frame - unwound PC zero\n");
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, NULL);
+ fprintf_unfiltered (gdb_stdlog, " // unwound PC zero }\n");
+ }
return NULL;
}
- /* Set the unwind functions based on that identified PC. */
- prev_frame->unwind = frame_unwind_find_by_pc (current_gdbarch,
- prev_frame->pc);
+ /* Don't yet compute ->unwind (and hence ->type). It is computed
+ on-demand in get_frame_type, frame_register_unwind, and
+ get_frame_id. */
- /* FIXME: cagney/2003-04-02: Rather than storing the frame's type in
- the frame, the unwinder's type should be returned directly.
- Unfortunatly, legacy code, called by legacy_get_prev_frame,
- explicitly set the frames type using the method
- deprecated_set_frame_type(). */
- gdb_assert (prev_frame->unwind->type != UNKNOWN_FRAME);
- prev_frame->type = prev_frame->unwind->type;
-
- /* Can the frame's type and unwinder be computed on demand? That
- would make a frame's creation really really lite! */
-
- /* The prev's frame's ID is computed by demand in get_frame_id(). */
+ /* Don't yet compute the frame's ID. It is computed on-demand by
+ get_frame_id(). */
/* The unwound frame ID is validate at the start of this function,
as part of the logic to decide if that frame should be further
this_frame->prev = prev_frame;
prev_frame->next = this_frame;
+ if (frame_debug)
+ {
+ fprintf_unfiltered (gdb_stdlog, "-> ");
+ fprint_frame (gdb_stdlog, prev_frame);
+ fprintf_unfiltered (gdb_stdlog, " }\n");
+ }
+
return prev_frame;
}
CORE_ADDR
get_frame_pc (struct frame_info *frame)
{
- return frame->pc;
+ gdb_assert (frame->next != NULL);
+ return frame_pc_unwind (frame->next);
}
static int
CORE_ADDR
get_frame_base (struct frame_info *fi)
{
- if (!fi->id_p)
- {
- /* HACK: Force the ID code to (indirectly) initialize the
- ->frame pointer. */
- get_frame_id (fi);
- }
- return fi->frame;
+ return get_frame_id (fi).stack_addr;
}
/* High-level offsets into the frame. Used by the debug info. */
if (!DEPRECATED_USE_GENERIC_DUMMY_FRAMES
&& deprecated_frame_in_dummy (frame))
return DUMMY_FRAME;
+ if (frame->unwind == NULL)
+ {
+ /* Initialize the frame's unwinder because it is that which
+ provides the frame's type. */
+ frame->unwind = frame_unwind_find_by_pc (current_gdbarch,
+ get_frame_pc (frame));
+ /* FIXME: cagney/2003-04-02: Rather than storing the frame's
+ type in the frame, the unwinder's type should be returned
+ directly. Unfortunatly, legacy code, called by
+ legacy_get_prev_frame, explicitly set the frames type using
+ the method deprecated_set_frame_type(). */
+ gdb_assert (frame->unwind->type != UNKNOWN_FRAME);
+ frame->type = frame->unwind->type;
+ }
if (frame->type == UNKNOWN_FRAME)
return NORMAL_FRAME;
else
void
deprecated_update_frame_pc_hack (struct frame_info *frame, CORE_ADDR pc)
{
- /* See comment in "frame.h". */
- frame->pc = pc;
+ if (frame_debug)
+ fprintf_unfiltered (gdb_stdlog,
+ "{ deprecated_update_frame_pc_hack (frame=%d,pc=0x%s) }\n",
+ frame->level, paddr_nz (pc));
/* NOTE: cagney/2003-03-11: Some architectures (e.g., Arm) are
maintaining a locally allocated frame object. Since such frame's
are not in the frame chain, it isn't possible to assume that the
/* While we're at it, update this frame's cached PC value, found
in the next frame. Oh for the day when "struct frame_info"
is opaque and this hack on hack can just go away. */
- frame->next->pc_unwind_cache = pc;
- frame->next->pc_unwind_cache_p = 1;
+ frame->next->prev_pc.value = pc;
+ frame->next->prev_pc.p = 1;
}
}
void
deprecated_update_frame_base_hack (struct frame_info *frame, CORE_ADDR base)
{
+ if (frame_debug)
+ fprintf_unfiltered (gdb_stdlog,
+ "{ deprecated_update_frame_base_hack (frame=%d,base=0x%s) }\n",
+ frame->level, paddr_nz (base));
/* See comment in "frame.h". */
- frame->frame = base;
+ frame->this_id.value.stack_addr = base;
}
void
struct frame_info *
deprecated_frame_xmalloc (void)
{
- struct frame_info *frame = XMALLOC (struct frame_info);
- memset (frame, 0, sizeof (struct frame_info));
+ struct frame_info *frame = FRAME_OBSTACK_ZALLOC (struct frame_info);
+ frame->this_id.p = 1;
return frame;
}
struct frame_unwind;
struct frame_base;
struct block;
+struct gdbarch;
/* A legacy unwinder to prop up architectures using the old style
saved regs array. */
struct frame_id
{
- /* The frame's address. This should be constant through out the
- lifetime of a frame. */
+ /* The frame's stack address. This shall be constant through out
+ the lifetime of a frame. Note that this requirement applies to
+ not just the function body, but also the prologue and (in theory
+ at least) the epilogue. Since that value needs to fall either on
+ the boundary, or within the frame's address range, the frame's
+ outer-most address (the inner-most address of the previous frame)
+ is used. Watch out for all the legacy targets that still use the
+ function pointer register or stack pointer register. They are
+ wrong. */
/* NOTE: cagney/2002-11-16: The ia64 has two stacks and hence two
frame bases. This will need to be expanded to accomodate that. */
- CORE_ADDR base;
- /* The frame's current PC. While the PC within the function may
- change, the function that contains the PC does not. Should this
- instead be the frame's function? */
- CORE_ADDR pc;
+ CORE_ADDR stack_addr;
+ /* The frame's code address. This shall be constant through out the
+ lifetime of the frame. While the PC (a.k.a. resume address)
+ changes as the function is executed, this code address cannot.
+ Typically, it is set to the address of the entry point of the
+ frame's function (as returned by frame_func_unwind(). */
+ CORE_ADDR code_addr;
};
/* Methods for constructing and comparing Frame IDs.
/* For convenience. All fields are zero. */
extern const struct frame_id null_frame_id;
-/* Construct a frame ID. The second parameter isn't yet well defined.
- It might be the containing function, or the resume PC (see comment
- above in `struct frame_id')? A func/pc of zero indicates a
- wildcard (i.e., do not use func in frame ID comparisons). */
-extern struct frame_id frame_id_build (CORE_ADDR base,
- CORE_ADDR func_or_pc);
+/* Construct a frame ID. The first parameter is the frame's constant
+ stack address (typically the outer-bound), and the second the
+ frame's constant code address (typically the entry point) (or zero,
+ to indicate a wild card). */
+extern struct frame_id frame_id_build (CORE_ADDR stack_addr,
+ CORE_ADDR code_addr);
/* Returns non-zero when L is a valid frame (a valid frame has a
non-zero .base). */
/* Base attributes of a frame: */
/* The frame's `resume' address. Where the program will resume in
- this frame. */
+ this frame.
+
+ This replaced: frame->pc; */
extern CORE_ADDR get_frame_pc (struct frame_info *);
/* Following on from the `resume' address. Return the entry point
get_frame_args_address: A set of high-level debug-info dependant
addresses that fall within the frame. These addresses almost
certainly will not match the stack address part of a frame ID (as
- returned by get_frame_base). */
+ returned by get_frame_base).
+
+ This replaced: frame->frame; */
extern CORE_ADDR get_frame_base (struct frame_info *);
of the caller. */
extern void frame_pop (struct frame_info *frame);
-/* We keep a cache of stack frames, each of which is a "struct
- frame_info". The innermost one gets allocated (in
- wait_for_inferior) each time the inferior stops; current_frame
- points to it. Additional frames get allocated (in
- get_prev_frame) as needed, and are chained through the next
- and prev fields. Any time that the frame cache becomes invalid
- (most notably when we execute something, but also if we change how
- we interpret the frames (e.g. "set heuristic-fence-post" in
- mips-tdep.c, or anything which reads new symbols)), we should call
- reinit_frame_cache. */
-
-struct frame_info
- {
- /* Nominal address of the frame described. See comments at
- get_frame_base() about what this means outside the *FRAME*
- macros; in the *FRAME* macros, it can mean whatever makes most
- sense for this machine. */
- CORE_ADDR frame;
-
- /* Address at which execution is occurring in this frame.
- For the innermost frame, it's the current pc.
- For other frames, it is a pc saved in the next frame. */
- CORE_ADDR pc;
-
- /* Level of this frame. The inner-most (youngest) frame is at
- level 0. As you move towards the outer-most (oldest) frame,
- the level increases. This is a cached value. It could just as
- easily be computed by counting back from the selected frame to
- the inner most frame. */
- /* NOTE: cagney/2002-04-05: Perhaphs a level of ``-1'' should be
- reserved to indicate a bogus frame - one that has been created
- just to keep GDB happy (GDB always needs a frame). For the
- moment leave this as speculation. */
- int level;
-
- /* The frame's type. */
- /* FIXME: cagney/2003-04-02: Should instead be returning
- ->unwind->type. Unfortunatly, legacy code is still explicitly
- setting the type using the method deprecated_set_frame_type.
- Eliminate that method and this field can be eliminated. */
- enum frame_type type;
-
- /* For each register, address of where it was saved on entry to
- the frame, or zero if it was not saved on entry to this frame.
- This includes special registers such as pc and fp saved in
- special ways in the stack frame. The SP_REGNUM is even more
- special, the address here is the sp for the previous frame, not
- the address where the sp was saved. */
- /* Allocated by frame_saved_regs_zalloc () which is called /
- initialized by DEPRECATED_FRAME_INIT_SAVED_REGS(). */
- CORE_ADDR *saved_regs; /*NUM_REGS + NUM_PSEUDO_REGS*/
-
- /* Anything extra for this structure that may have been defined
- in the machine dependent files. */
- /* Allocated by frame_extra_info_zalloc () which is called /
- initialized by DEPRECATED_INIT_EXTRA_FRAME_INFO */
- struct frame_extra_info *extra_info;
-
- /* If dwarf2 unwind frame informations is used, this structure holds all
- related unwind data. */
- struct context *context;
-
- /* The frame's low-level unwinder and corresponding cache. The
- low-level unwinder is responsible for unwinding register values
- for the previous frame. The low-level unwind methods are
- selected based on the presence, or otherwize, of register
- unwind information such as CFI. */
- void *prologue_cache;
- const struct frame_unwind *unwind;
-
- /* Cached copy of the previous frame's resume address. */
- int pc_unwind_cache_p;
- CORE_ADDR pc_unwind_cache;
-
- /* Cached copy of the previous frame's function address. */
- struct
- {
- CORE_ADDR addr;
- int p;
- } prev_func;
-
- /* This frame's ID. Note that the frame's ID, base and PC contain
- redundant information. */
- int id_p;
- struct frame_id id;
-
- /* The frame's high-level base methods, and corresponding cache.
- The high level base methods are selected based on the frame's
- debug info. */
- const struct frame_base *base;
- void *base_cache;
-
- /* Pointers to the next (down, inner, younger) and previous (up,
- outer, older) frame_info's in the frame cache. */
- struct frame_info *next; /* down, inner, younger */
- int prev_p;
- struct frame_info *prev; /* up, outer, older */
- };
-
/* Values for the source flag to be used in print_frame_info_base(). */
enum print_what
{
extern void *frame_obstack_zalloc (unsigned long size);
#define FRAME_OBSTACK_ZALLOC(TYPE) ((TYPE *) frame_obstack_zalloc (sizeof (TYPE)))
-/* If DEPRECATED_FRAME_CHAIN_VALID returns zero it means that the
- given frame is the outermost one and has no caller. */
+/* If legacy_frame_chain_valid() returns zero it means that the given
+ frame is the outermost one and has no caller.
-extern int frame_chain_valid (CORE_ADDR, struct frame_info *);
+ This method has been superseeded by the per-architecture
+ frame_unwind_pc() (returns 0 to indicate an invalid return address)
+ and per-frame this_id() (returns a NULL frame ID to indicate an
+ invalid frame). */
+extern int legacy_frame_chain_valid (CORE_ADDR, struct frame_info *);
extern void generic_save_dummy_frame_tos (CORE_ADDR sp);
/* FIXME: cagney/2002-12-06: Has the PC in the current frame changed?
"infrun.c", Thanks to DECR_PC_AFTER_BREAK, can change the PC after
- the initial frame create. This puts things back in sync. */
+ the initial frame create. This puts things back in sync.
+
+ This replaced: frame->pc = ....; */
extern void deprecated_update_frame_pc_hack (struct frame_info *frame,
CORE_ADDR pc);
more exact, whas that initial guess at the frame's base as returned
by read_fp() wrong. If it was, fix it. This shouldn't be
necessary since the code should be getting the frame's base correct
- from the outset. */
+ from the outset.
+
+ This replaced: frame->frame = ....; */
extern void deprecated_update_frame_base_hack (struct frame_info *frame,
CORE_ADDR base);
set_gdbarch_frame_args_skip (gdbarch, 0);
set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation);
- set_gdbarch_saved_pc_after_call (gdbarch, frv_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, frv_saved_pc_after_call);
set_gdbarch_deprecated_frame_chain (gdbarch, frv_frame_chain);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, frv_frame_saved_pc);
#ifndef GDB_H
#define GDB_H
+struct ui_out;
+
/* Return-code (RC) from a gdb library call. (The abreviation RC is
taken from the sim/common directory.) */
--- /dev/null
+#!/bin/sh
+
+# Copyright 2003 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Please email any bugs, comments, and/or additions to this file to:
+# bug-gdb@prep.ai.mit.edu
+
+#
+# gcore.sh
+# Script to generate a core file of a running program.
+# It starts up gdb, attaches to the given PID and invokes the gcore command.
+#
+
+if [ "$#" -eq "0" ]
+then
+ echo "usage: gcore [-o filename] pid"
+ exit 2
+fi
+
+# Need to check for -o option, but set default basename to "core".
+name=core
+
+if [ "$1" = "-o" ]
+then
+ if [ "$#" -lt "3" ]
+ then
+ # Not enough arguments.
+ echo "usage: gcore [-o filename] pid"
+ exit 2
+ fi
+ name=$2
+
+ # Shift over to start of pid list
+ shift; shift
+fi
+
+# Initialise return code.
+rc=0
+
+# Loop through pids
+for pid in $*
+do
+ # Write gdb script for pid $pid.
+
+ # Avoid need for temporary files by using funky "here
+ # document" feature of sh.
+
+ /usr/bin/gdb > /dev/null << EOF
+ attach $pid
+ gcore $name.$pid
+ detach
+ quit
+EOF
+
+ if [ -r $name.$pid ] ; then
+ rc=0
+ else
+ echo gcore: failed to create $name.$pid
+ rc=1
+ break
+ fi
+
+
+done
+
+exit $rc
+
types="\
-T FILE \
--T bfd -T asection \
--T prgregset_t -T fpregset_t -T gregset_t \
+-T bfd -T asection -T pid_t \
+-T prgregset_t -T fpregset_t -T gregset_t -T sigset_t \
+-T td_thrhandle_t -T td_event_msg_t -T td_thr_events_t \
+-T td_notify_t -T td_thr_iter_f -T td_thrinfo_t \
`cat *.h | sed -n \
-e 's/^.*[^a-z0-9_]\([a-z0-9_]*_ftype\).*$/-T \1/p' \
-e 's/^.*[^a-z0-9_]\([a-z0-9_]*_func\).*$/-T \1/p' \
gdbarch_unwind_pc_ftype *unwind_pc;
gdbarch_frame_args_address_ftype *frame_args_address;
gdbarch_frame_locals_address_ftype *frame_locals_address;
- gdbarch_saved_pc_after_call_ftype *saved_pc_after_call;
+ gdbarch_deprecated_saved_pc_after_call_ftype *deprecated_saved_pc_after_call;
gdbarch_frame_num_args_ftype *frame_num_args;
gdbarch_stack_align_ftype *stack_align;
gdbarch_frame_align_ftype *frame_align;
/* Skip verify of unwind_pc, has predicate */
/* Skip verify of frame_args_address, invalid_p == 0 */
/* Skip verify of frame_locals_address, invalid_p == 0 */
- if ((GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
- && (gdbarch->saved_pc_after_call == 0))
- fprintf_unfiltered (log, "\n\tsaved_pc_after_call");
+ /* Skip verify of deprecated_saved_pc_after_call, has predicate */
if ((GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL)
&& (gdbarch->frame_num_args == 0))
fprintf_unfiltered (log, "\n\tframe_num_args");
(long) current_gdbarch->deprecated_push_return_address
/*DEPRECATED_PUSH_RETURN_ADDRESS ()*/);
#endif
+#ifdef DEPRECATED_SAVED_PC_AFTER_CALL_P
+ fprintf_unfiltered (file,
+ "gdbarch_dump: %s # %s\n",
+ "DEPRECATED_SAVED_PC_AFTER_CALL_P()",
+ XSTRING (DEPRECATED_SAVED_PC_AFTER_CALL_P ()));
+ fprintf_unfiltered (file,
+ "gdbarch_dump: DEPRECATED_SAVED_PC_AFTER_CALL_P() = %d\n",
+ DEPRECATED_SAVED_PC_AFTER_CALL_P ());
+#endif
+#ifdef DEPRECATED_SAVED_PC_AFTER_CALL
+ fprintf_unfiltered (file,
+ "gdbarch_dump: %s # %s\n",
+ "DEPRECATED_SAVED_PC_AFTER_CALL(frame)",
+ XSTRING (DEPRECATED_SAVED_PC_AFTER_CALL (frame)));
+ if (GDB_MULTI_ARCH)
+ fprintf_unfiltered (file,
+ "gdbarch_dump: DEPRECATED_SAVED_PC_AFTER_CALL = <0x%08lx>\n",
+ (long) current_gdbarch->deprecated_saved_pc_after_call
+ /*DEPRECATED_SAVED_PC_AFTER_CALL ()*/);
+#endif
#ifdef DEPRECATED_STORE_RETURN_VALUE
#if GDB_MULTI_ARCH
/* Macro might contain `[{}]' when not multi-arch */
(long) current_gdbarch->return_value_on_stack
/*RETURN_VALUE_ON_STACK ()*/);
#endif
-#ifdef SAVED_PC_AFTER_CALL
- fprintf_unfiltered (file,
- "gdbarch_dump: %s # %s\n",
- "SAVED_PC_AFTER_CALL(frame)",
- XSTRING (SAVED_PC_AFTER_CALL (frame)));
- if (GDB_MULTI_ARCH)
- fprintf_unfiltered (file,
- "gdbarch_dump: SAVED_PC_AFTER_CALL = <0x%08lx>\n",
- (long) current_gdbarch->saved_pc_after_call
- /*SAVED_PC_AFTER_CALL ()*/);
-#endif
#ifdef SAVE_DUMMY_FRAME_TOS_P
fprintf_unfiltered (file,
"gdbarch_dump: %s # %s\n",
gdbarch->frame_locals_address = frame_locals_address;
}
+int
+gdbarch_deprecated_saved_pc_after_call_p (struct gdbarch *gdbarch)
+{
+ gdb_assert (gdbarch != NULL);
+ return gdbarch->deprecated_saved_pc_after_call != 0;
+}
+
CORE_ADDR
-gdbarch_saved_pc_after_call (struct gdbarch *gdbarch, struct frame_info *frame)
+gdbarch_deprecated_saved_pc_after_call (struct gdbarch *gdbarch, struct frame_info *frame)
{
gdb_assert (gdbarch != NULL);
- if (gdbarch->saved_pc_after_call == 0)
+ if (gdbarch->deprecated_saved_pc_after_call == 0)
internal_error (__FILE__, __LINE__,
- "gdbarch: gdbarch_saved_pc_after_call invalid");
+ "gdbarch: gdbarch_deprecated_saved_pc_after_call invalid");
if (gdbarch_debug >= 2)
- fprintf_unfiltered (gdb_stdlog, "gdbarch_saved_pc_after_call called\n");
- return gdbarch->saved_pc_after_call (frame);
+ fprintf_unfiltered (gdb_stdlog, "gdbarch_deprecated_saved_pc_after_call called\n");
+ return gdbarch->deprecated_saved_pc_after_call (frame);
}
void
-set_gdbarch_saved_pc_after_call (struct gdbarch *gdbarch,
- gdbarch_saved_pc_after_call_ftype saved_pc_after_call)
+set_gdbarch_deprecated_saved_pc_after_call (struct gdbarch *gdbarch,
+ gdbarch_deprecated_saved_pc_after_call_ftype deprecated_saved_pc_after_call)
{
- gdbarch->saved_pc_after_call = saved_pc_after_call;
+ gdbarch->deprecated_saved_pc_after_call = deprecated_saved_pc_after_call;
}
int
#include "symfile.h" /* For entry_point_address(). */
#endif
+struct floatformat;
+struct ui_file;
struct frame_info;
struct value;
struct objfile;
#endif
#endif
-typedef CORE_ADDR (gdbarch_saved_pc_after_call_ftype) (struct frame_info *frame);
-extern CORE_ADDR gdbarch_saved_pc_after_call (struct gdbarch *gdbarch, struct frame_info *frame);
-extern void set_gdbarch_saved_pc_after_call (struct gdbarch *gdbarch, gdbarch_saved_pc_after_call_ftype *saved_pc_after_call);
-#if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) && defined (SAVED_PC_AFTER_CALL)
-#error "Non multi-arch definition of SAVED_PC_AFTER_CALL"
+#if defined (DEPRECATED_SAVED_PC_AFTER_CALL)
+/* Legacy for systems yet to multi-arch DEPRECATED_SAVED_PC_AFTER_CALL */
+#if !defined (DEPRECATED_SAVED_PC_AFTER_CALL_P)
+#define DEPRECATED_SAVED_PC_AFTER_CALL_P() (1)
+#endif
+#endif
+
+/* Default predicate for non- multi-arch targets. */
+#if (!GDB_MULTI_ARCH) && !defined (DEPRECATED_SAVED_PC_AFTER_CALL_P)
+#define DEPRECATED_SAVED_PC_AFTER_CALL_P() (0)
+#endif
+
+extern int gdbarch_deprecated_saved_pc_after_call_p (struct gdbarch *gdbarch);
+#if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) && defined (DEPRECATED_SAVED_PC_AFTER_CALL_P)
+#error "Non multi-arch definition of DEPRECATED_SAVED_PC_AFTER_CALL"
+#endif
+#if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) || !defined (DEPRECATED_SAVED_PC_AFTER_CALL_P)
+#define DEPRECATED_SAVED_PC_AFTER_CALL_P() (gdbarch_deprecated_saved_pc_after_call_p (current_gdbarch))
+#endif
+
+/* Default (function) for non- multi-arch platforms. */
+#if (!GDB_MULTI_ARCH) && !defined (DEPRECATED_SAVED_PC_AFTER_CALL)
+#define DEPRECATED_SAVED_PC_AFTER_CALL(frame) (internal_error (__FILE__, __LINE__, "DEPRECATED_SAVED_PC_AFTER_CALL"), 0)
+#endif
+
+typedef CORE_ADDR (gdbarch_deprecated_saved_pc_after_call_ftype) (struct frame_info *frame);
+extern CORE_ADDR gdbarch_deprecated_saved_pc_after_call (struct gdbarch *gdbarch, struct frame_info *frame);
+extern void set_gdbarch_deprecated_saved_pc_after_call (struct gdbarch *gdbarch, gdbarch_deprecated_saved_pc_after_call_ftype *deprecated_saved_pc_after_call);
+#if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) && defined (DEPRECATED_SAVED_PC_AFTER_CALL)
+#error "Non multi-arch definition of DEPRECATED_SAVED_PC_AFTER_CALL"
#endif
#if GDB_MULTI_ARCH
-#if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) || !defined (SAVED_PC_AFTER_CALL)
-#define SAVED_PC_AFTER_CALL(frame) (gdbarch_saved_pc_after_call (current_gdbarch, frame))
+#if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) || !defined (DEPRECATED_SAVED_PC_AFTER_CALL)
+#define DEPRECATED_SAVED_PC_AFTER_CALL(frame) (gdbarch_deprecated_saved_pc_after_call (current_gdbarch, frame))
#endif
#endif
M::UNWIND_PC:CORE_ADDR:unwind_pc:struct frame_info *next_frame:next_frame:
f:2:FRAME_ARGS_ADDRESS:CORE_ADDR:frame_args_address:struct frame_info *fi:fi::0:get_frame_base::0
f:2:FRAME_LOCALS_ADDRESS:CORE_ADDR:frame_locals_address:struct frame_info *fi:fi::0:get_frame_base::0
-f:2:SAVED_PC_AFTER_CALL:CORE_ADDR:saved_pc_after_call:struct frame_info *frame:frame::0:0
+F::DEPRECATED_SAVED_PC_AFTER_CALL:CORE_ADDR:deprecated_saved_pc_after_call:struct frame_info *frame:frame
f:2:FRAME_NUM_ARGS:int:frame_num_args:struct frame_info *frame:frame::0:0
#
F:2:STACK_ALIGN:CORE_ADDR:stack_align:CORE_ADDR sp:sp::0:0
#include "symfile.h" /* For entry_point_address(). */
#endif
+struct floatformat;
+struct ui_file;
struct frame_info;
struct value;
struct objfile;
extern struct cmd_list_element *maintenanceprintlist;
+/* Chain containing all defined "maintenance list" subcommands. */
+
+extern struct cmd_list_element *maintenancelistlist;
+
extern struct cmd_list_element *setprintlist;
extern struct cmd_list_element *showprintlist;
#if !defined (GDBCORE_H)
#define GDBCORE_H 1
+struct type;
+
#include "bfd.h"
/* Return the name of the executable file as a string.
#ifndef GDBTHREAD_H
#define GDBTHREAD_H
+struct breakpoint;
+struct frame_id;
+struct symtab;
+
/* For bpstat */
#include "breakpoint.h"
int num; /* Convenient handle (GDB thread id) */
/* State from wait_for_inferior */
CORE_ADDR prev_pc;
- CORE_ADDR prev_func_start;
char *prev_func_name;
struct breakpoint *step_resume_breakpoint;
struct breakpoint *through_sigtramp_breakpoint;
/* infrun context switch: save the debugger state for the given thread. */
extern void save_infrun_state (ptid_t ptid,
CORE_ADDR prev_pc,
- CORE_ADDR prev_func_start,
char *prev_func_name,
int trap_expected,
struct breakpoint *step_resume_breakpoint,
for the given thread. */
extern void load_infrun_state (ptid_t ptid,
CORE_ADDR *prev_pc,
- CORE_ADDR *prev_func_start,
char **prev_func_name,
int *trap_expected,
struct breakpoint **step_resume_breakpoint,
#define GDBTYPES_H 1
/* Forward declarations for prototypes. */
+struct field;
struct block;
/* Codes for `fundamental types'. This is a monstrosity based on the
set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, h8300_frame_init_saved_regs);
set_gdbarch_deprecated_init_extra_frame_info (gdbarch, h8300_init_extra_frame_info);
set_gdbarch_deprecated_frame_chain (gdbarch, h8300_frame_chain);
- set_gdbarch_saved_pc_after_call (gdbarch, h8300_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, h8300_saved_pc_after_call);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, h8300_frame_saved_pc);
set_gdbarch_skip_prologue (gdbarch, h8300_skip_prologue);
set_gdbarch_frame_args_address (gdbarch, h8300_frame_args_address);
/* Target-dependent code for HPUX running on PA-RISC, for GDB.
- Copyright 2002 Free Software Foundation, Inc.
+
+ Copyright 2002, 2003 Free Software Foundation, Inc.
This file is part of GDB.
void
hppa_hpux_frame_saved_pc_in_sigtramp (struct frame_info *fi, CORE_ADDR *tmp)
{
- *tmp = read_memory_integer (fi->frame + (43 * 4), 4);
+ *tmp = read_memory_integer (get_frame_base (fi) + (43 * 4), 4);
}
void
hppa_hpux_frame_base_before_sigtramp (struct frame_info *fi,
CORE_ADDR *tmp)
{
- *tmp = read_memory_integer (fi->frame + (40 * 4), 4);
+ *tmp = read_memory_integer (get_frame_base (fi) + (40 * 4), 4);
}
void
CORE_ADDR *fsr)
{
int i;
- const CORE_ADDR tmp = (fi)->frame + (10 * 4);
+ const CORE_ADDR tmp = get_frame_base (fi) + (10 * 4);
for (i = 0; i < NUM_REGS; i++)
{
{
struct unwind_table_entry *u;
- u = find_unwind_entry (frame->pc);
+ u = find_unwind_entry (get_frame_pc (frame));
if (u == 0)
return 0;
are saved in the exact same order as GDB numbers registers. How
convienent. */
if (pc_in_interrupt_handler (pc))
- return read_memory_integer (frame->frame + PC_REGNUM * 4,
+ return read_memory_integer (get_frame_base (frame) + PC_REGNUM * 4,
TARGET_PTR_BIT / 8) & ~0x3;
- if ((frame->pc >= frame->frame
- && frame->pc <= (frame->frame
- /* A call dummy is sized in words, but it is
- actually a series of instructions. Account
- for that scaling factor. */
- + ((REGISTER_SIZE / INSTRUCTION_SIZE)
- * CALL_DUMMY_LENGTH)
- /* Similarly we have to account for 64bit
- wide register saves. */
- + (32 * REGISTER_SIZE)
- /* We always consider FP regs 8 bytes long. */
- + (NUM_REGS - FP0_REGNUM) * 8
- /* Similarly we have to account for 64bit
- wide register saves. */
- + (6 * REGISTER_SIZE))))
+ if ((get_frame_pc (frame) >= get_frame_base (frame)
+ && (get_frame_pc (frame)
+ <= (get_frame_base (frame)
+ /* A call dummy is sized in words, but it is actually a
+ series of instructions. Account for that scaling
+ factor. */
+ + ((REGISTER_SIZE / INSTRUCTION_SIZE)
+ * CALL_DUMMY_LENGTH)
+ /* Similarly we have to account for 64bit wide register
+ saves. */
+ + (32 * REGISTER_SIZE)
+ /* We always consider FP regs 8 bytes long. */
+ + (NUM_REGS - FP0_REGNUM) * 8
+ /* Similarly we have to account for 64bit wide register
+ saves. */
+ + (6 * REGISTER_SIZE)))))
{
- return read_memory_integer ((frame->frame
+ return read_memory_integer ((get_frame_base (frame)
+ (TARGET_PTR_BIT == 64 ? -16 : -20)),
TARGET_PTR_BIT / 8) & ~0x3;
}
handler caller, then we need to look in the saved
register area to get the return pointer (the values
in the registers may not correspond to anything useful). */
- if (frame->next
- && ((get_frame_type (frame->next) == SIGTRAMP_FRAME)
- || pc_in_interrupt_handler (frame->next->pc)))
+ if (get_next_frame (frame)
+ && ((get_frame_type (get_next_frame (frame)) == SIGTRAMP_FRAME)
+ || pc_in_interrupt_handler (get_frame_pc (get_next_frame (frame)))))
{
CORE_ADDR *saved_regs;
- hppa_frame_init_saved_regs (frame->next);
- saved_regs = get_frame_saved_regs (frame->next);
+ hppa_frame_init_saved_regs (get_next_frame (frame));
+ saved_regs = get_frame_saved_regs (get_next_frame (frame));
if (read_memory_integer (saved_regs[FLAGS_REGNUM],
TARGET_PTR_BIT / 8) & 0x2)
{
with a return pointer in %rp and the kernel call with
a return pointer in %r31. We return the %rp variant
if %r31 is the same as frame->pc. */
- if (pc == frame->pc)
+ if (pc == get_frame_pc (frame))
pc = read_memory_integer (saved_regs[RP_REGNUM],
TARGET_PTR_BIT / 8) & ~0x3;
}
frame is a signal or interrupt handler, then dig the right
information out of the saved register info. */
if (rp_offset == 0
- && frame->next
- && ((get_frame_type (frame->next) == SIGTRAMP_FRAME)
- || pc_in_interrupt_handler (frame->next->pc)))
+ && get_next_frame (frame)
+ && ((get_frame_type (get_next_frame (frame)) == SIGTRAMP_FRAME)
+ || pc_in_interrupt_handler (get_frame_pc (get_next_frame (frame)))))
{
CORE_ADDR *saved_regs;
- hppa_frame_init_saved_regs (frame->next);
- saved_regs = get_frame_saved_regs (frame->next);
+ hppa_frame_init_saved_regs (get_next_frame (frame));
+ saved_regs = get_frame_saved_regs (get_next_frame (frame));
if (read_memory_integer (saved_regs[FLAGS_REGNUM],
TARGET_PTR_BIT / 8) & 0x2)
{
with a return pointer in %rp and the kernel call with
a return pointer in %r31. We return the %rp variant
if %r31 is the same as frame->pc. */
- if (pc == frame->pc)
+ if (pc == get_frame_pc (frame))
pc = read_memory_integer (saved_regs[RP_REGNUM],
TARGET_PTR_BIT / 8) & ~0x3;
}
else
{
old_pc = pc;
- pc = read_memory_integer (frame->frame + rp_offset,
+ pc = read_memory_integer (get_frame_base (frame) + rp_offset,
TARGET_PTR_BIT / 8) & ~0x3;
}
}
int flags;
int framesize;
- if (frame->next && !fromleaf)
+ if (get_next_frame (frame) && !fromleaf)
return;
/* If the next frame represents a frameless function invocation then
frame. (we always want frame->frame to point at the lowest address
in the frame). */
if (framesize == -1)
- frame->frame = TARGET_READ_FP ();
+ deprecated_update_frame_base_hack (frame, TARGET_READ_FP ());
else
- frame->frame -= framesize;
+ deprecated_update_frame_base_hack (frame, get_frame_base (frame) - framesize);
return;
}
flags = read_register (FLAGS_REGNUM);
if (flags & 2) /* In system call? */
- frame->pc = read_register (31) & ~0x3;
+ deprecated_update_frame_pc_hack (frame, read_register (31) & ~0x3);
/* The outermost frame is always derived from PC-framesize
explain, but the parent *always* creates some stack space for
the child. So the child actually does have a frame of some
sorts, and its base is the high address in its parent's frame. */
- framesize = find_proc_framesize (frame->pc);
+ framesize = find_proc_framesize (get_frame_pc (frame));
if (framesize == -1)
- frame->frame = TARGET_READ_FP ();
+ deprecated_update_frame_base_hack (frame, TARGET_READ_FP ());
else
- frame->frame = read_register (SP_REGNUM) - framesize;
+ deprecated_update_frame_base_hack (frame, read_register (SP_REGNUM) - framesize);
}
\f
/* Given a GDB frame, determine the address of the calling function's
/* If this is a threaded application, and we see the
routine "__pthread_exit", treat it as the stack root
for this thread. */
- min_frame_symbol = lookup_minimal_symbol_by_pc (frame->pc);
- frame_symbol = find_pc_function (frame->pc);
+ min_frame_symbol = lookup_minimal_symbol_by_pc (get_frame_pc (frame));
+ frame_symbol = find_pc_function (get_frame_pc (frame));
if ((min_frame_symbol != 0) /* && (frame_symbol == 0) */ )
{
are easy; at *sp we have a full save state strucutre which we can
pull the old stack pointer from. Also see frame_saved_pc for
code to dig a saved PC out of the save state structure. */
- if (pc_in_interrupt_handler (frame->pc))
- frame_base = read_memory_integer (frame->frame + SP_REGNUM * 4,
+ if (pc_in_interrupt_handler (get_frame_pc (frame)))
+ frame_base = read_memory_integer (get_frame_base (frame) + SP_REGNUM * 4,
TARGET_PTR_BIT / 8);
#ifdef FRAME_BASE_BEFORE_SIGTRAMP
else if ((get_frame_type (frame) == SIGTRAMP_FRAME))
}
#endif
else
- frame_base = frame->frame;
+ frame_base = get_frame_base (frame);
/* Get frame sizes for the current frame and the frame of the
caller. */
- my_framesize = find_proc_framesize (frame->pc);
+ my_framesize = find_proc_framesize (get_frame_pc (frame));
caller_pc = DEPRECATED_FRAME_SAVED_PC (frame);
/* If we can't determine the caller's PC, then it's not likely we can
We use information from unwind descriptors to determine if %r3
is saved into the stack (Entry_GR field has this information). */
- for (tmp_frame = frame; tmp_frame; tmp_frame = tmp_frame->next)
+ for (tmp_frame = frame; tmp_frame; tmp_frame = get_next_frame (tmp_frame))
{
- u = find_unwind_entry (tmp_frame->pc);
+ u = find_unwind_entry (get_frame_pc (tmp_frame));
if (!u)
{
the dynamic linker will give you a PC that has none. Thus, I've
disabled this warning. */
#if 0
- warning ("Unable to find unwind for PC 0x%x -- Help!", tmp_frame->pc);
+ warning ("Unable to find unwind for PC 0x%x -- Help!", get_frame_pc (tmp_frame));
#endif
return (CORE_ADDR) 0;
}
if (u->Save_SP
|| (get_frame_type (tmp_frame) == SIGTRAMP_FRAME)
- || pc_in_interrupt_handler (tmp_frame->pc))
+ || pc_in_interrupt_handler (get_frame_pc (tmp_frame)))
break;
/* Entry_GR specifies the number of callee-saved general registers
pointer. */
if (u->Save_SP
&& !(get_frame_type (tmp_frame) == SIGTRAMP_FRAME)
- && !pc_in_interrupt_handler (tmp_frame->pc))
+ && !pc_in_interrupt_handler (get_frame_pc (tmp_frame)))
{
- return read_memory_integer (tmp_frame->frame, TARGET_PTR_BIT / 8);
+ return read_memory_integer (get_frame_base (tmp_frame), TARGET_PTR_BIT / 8);
}
/* %r3 was saved somewhere in the stack. Dig it out. */
else
{
/* Get the innermost frame. */
tmp_frame = frame;
- while (tmp_frame->next != NULL)
- tmp_frame = tmp_frame->next;
+ while (get_next_frame (tmp_frame) != NULL)
+ tmp_frame = get_next_frame (tmp_frame);
if (tmp_frame != saved_regs_frame)
{
struct unwind_table_entry *u, *next_u = NULL;
struct frame_info *next;
- u = find_unwind_entry (thisframe->pc);
+ u = find_unwind_entry (get_frame_pc (thisframe));
if (u == NULL)
return 1;
next = get_next_frame (thisframe);
if (next)
- next_u = find_unwind_entry (next->pc);
+ next_u = find_unwind_entry (get_frame_pc (next));
/* If this frame does not save SP, has no stack, isn't a stub,
and doesn't "call" an interrupt routine or signal handler caller,
then its not valid. */
if (u->Save_SP || u->Total_frame_size || u->stub_unwind.stub_type != 0
- || (thisframe->next && (get_frame_type (thisframe->next) == SIGTRAMP_FRAME))
+ || (get_next_frame (thisframe) && (get_frame_type (get_next_frame (thisframe)) == SIGTRAMP_FRAME))
|| (next_u && next_u->HP_UX_interrupt_marker))
return 1;
- if (pc_in_linker_stub (thisframe->pc))
+ if (pc_in_linker_stub (get_frame_pc (thisframe)))
return 1;
return 0;
find_dummy_frame_regs (struct frame_info *frame,
CORE_ADDR frame_saved_regs[])
{
- CORE_ADDR fp = frame->frame;
+ CORE_ADDR fp = get_frame_base (frame);
int i;
/* The 32bit and 64bit ABIs save RP into different locations. */
examine the dummy code to determine locations of saved registers;
instead, let find_dummy_frame_regs fill in the correct offsets
for the saved registers. */
- if ((frame_info->pc >= frame_info->frame
- && frame_info->pc <= (frame_info->frame
- /* A call dummy is sized in words, but it is
- actually a series of instructions. Account
- for that scaling factor. */
- + ((REGISTER_SIZE / INSTRUCTION_SIZE)
- * CALL_DUMMY_LENGTH)
- /* Similarly we have to account for 64bit
- wide register saves. */
- + (32 * REGISTER_SIZE)
- /* We always consider FP regs 8 bytes long. */
- + (NUM_REGS - FP0_REGNUM) * 8
- /* Similarly we have to account for 64bit
- wide register saves. */
- + (6 * REGISTER_SIZE))))
+ if ((get_frame_pc (frame_info) >= get_frame_base (frame_info)
+ && (get_frame_pc (frame_info)
+ <= (get_frame_base (frame_info)
+ /* A call dummy is sized in words, but it is actually a
+ series of instructions. Account for that scaling
+ factor. */
+ + ((REGISTER_SIZE / INSTRUCTION_SIZE)
+ * CALL_DUMMY_LENGTH)
+ /* Similarly we have to account for 64bit wide register
+ saves. */
+ + (32 * REGISTER_SIZE)
+ /* We always consider FP regs 8 bytes long. */
+ + (NUM_REGS - FP0_REGNUM) * 8
+ /* Similarly we have to account for 64bit wide register
+ saves. */
+ + (6 * REGISTER_SIZE)))))
find_dummy_frame_regs (frame_info, frame_saved_regs);
/* Interrupt handlers are special too. They lay out the register
state in the exact same order as the register numbers in GDB. */
- if (pc_in_interrupt_handler (frame_info->pc))
+ if (pc_in_interrupt_handler (get_frame_pc (frame_info)))
{
for (i = 0; i < NUM_REGS; i++)
{
/* SP is a little special. */
if (i == SP_REGNUM)
frame_saved_regs[SP_REGNUM]
- = read_memory_integer (frame_info->frame + SP_REGNUM * 4,
+ = read_memory_integer (get_frame_base (frame_info) + SP_REGNUM * 4,
TARGET_PTR_BIT / 8);
else
- frame_saved_regs[i] = frame_info->frame + i * 4;
+ frame_saved_regs[i] = get_frame_base (frame_info) + i * 4;
}
return;
}
/* The frame always represents the value of %sp at entry to the
current function (and is thus equivalent to the "saved" stack
pointer. */
- frame_saved_regs[SP_REGNUM] = frame_info->frame;
+ frame_saved_regs[SP_REGNUM] = get_frame_base (frame_info);
/* Loop until we find everything of interest or hit a branch.
GCC code. */
final_iteration = 0;
while ((save_gr || save_fr || save_rp || save_sp || stack_remaining > 0)
- && pc <= frame_info->pc)
+ && pc <= get_frame_pc (frame_info))
{
status = target_read_memory (pc, buf, 4);
inst = extract_unsigned_integer (buf, 4);
if (inst == 0x6bc23fd9) /* stw rp,-0x14(sr0,sp) */
{
save_rp = 0;
- frame_saved_regs[RP_REGNUM] = frame_info->frame - 20;
+ frame_saved_regs[RP_REGNUM] = get_frame_base (frame_info) - 20;
}
else if (inst == 0x0fc212c1) /* std rp,-0x10(sr0,sp) */
{
save_rp = 0;
- frame_saved_regs[RP_REGNUM] = frame_info->frame - 16;
+ frame_saved_regs[RP_REGNUM] = get_frame_base (frame_info) - 16;
}
/* Note if we saved SP into the stack. This also happens to indicate
if ( (inst & 0xffffc000) == 0x6fc10000 /* stw,ma r1,N(sr0,sp) */
|| (inst & 0xffffc00c) == 0x73c10008) /* std,ma r1,N(sr0,sp) */
{
- frame_saved_regs[FP_REGNUM] = frame_info->frame;
+ frame_saved_regs[FP_REGNUM] = get_frame_base (frame_info);
save_sp = 0;
}
/* stwm with a positive displacement is a *post modify*. */
if ((inst >> 26) == 0x1b
&& extract_14 (inst) >= 0)
- frame_saved_regs[reg] = frame_info->frame;
+ frame_saved_regs[reg] = get_frame_base (frame_info);
/* A std has explicit post_modify forms. */
else if ((inst & 0xfc00000c0) == 0x70000008)
- frame_saved_regs[reg] = frame_info->frame;
+ frame_saved_regs[reg] = get_frame_base (frame_info);
else
{
CORE_ADDR offset;
/* Handle code with and without frame pointers. */
if (u->Save_SP)
frame_saved_regs[reg]
- = frame_info->frame + offset;
+ = get_frame_base (frame_info) + offset;
else
frame_saved_regs[reg]
- = (frame_info->frame + (u->Total_frame_size << 3)
+ = (get_frame_base (frame_info) + (u->Total_frame_size << 3)
+ offset);
}
}
/* 1st HP CC FP register store. After this instruction
we've set enough state that the GCC and HPCC code are
both handled in the same manner. */
- frame_saved_regs[reg + FP4_REGNUM + 4] = frame_info->frame;
+ frame_saved_regs[reg + FP4_REGNUM + 4] = get_frame_base (frame_info);
fp_loc = 8;
}
else
{
frame_saved_regs[reg + FP0_REGNUM + 4]
- = frame_info->frame + fp_loc;
+ = get_frame_base (frame_info) + fp_loc;
fp_loc += 8;
}
}
return (struct exception_event_record *) NULL;
select_frame (fi);
- throw_addr = fi->pc;
+ throw_addr = get_frame_pc (fi);
/* Go back to original (top) frame */
select_frame (curr_frame);
CORE_ADDR
hppa_frame_args_address (struct frame_info *fi)
{
- return fi->frame;
+ return get_frame_base (fi);
}
CORE_ADDR
hppa_frame_locals_address (struct frame_info *fi)
{
- return fi->frame;
+ return get_frame_base (fi);
}
int
set_gdbarch_in_solib_call_trampoline (gdbarch, hppa_in_solib_call_trampoline);
set_gdbarch_in_solib_return_trampoline (gdbarch,
hppa_in_solib_return_trampoline);
- set_gdbarch_saved_pc_after_call (gdbarch, hppa_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, hppa_saved_pc_after_call);
set_gdbarch_inner_than (gdbarch, hppa_inner_than);
set_gdbarch_stack_align (gdbarch, hppa_stack_align);
set_gdbarch_decr_pc_after_break (gdbarch, 0);
#include "defs.h"
#include "gdb_string.h"
+#include "gdbcore.h"
#include "i386-tdep.h"
#include "osabi.h"
+#include "frame.h"
+#include "dummy-frame.h"
+
+static int
+i386_cygwin_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
+{
+ /* In the context where this is used, we get the saved PC before we've
+ successfully unwound far enough to be sure what we've got (it may
+ be a signal handler caller). If we're dealing with a signal
+ handler caller, this will return valid, which is fine. If not,
+ it'll make the correct test. */
+ return ((get_frame_type (thisframe) == SIGTRAMP_FRAME) || chain != 0);
+}
+/* Return the chain-pointer for FRAME. In the case of the i386, the
+ frame's nominal address is the address of a 4-byte word containing
+ the calling frame's address. */
+static CORE_ADDR
+i386_cygwin_frame_chain (struct frame_info *frame)
+{
+ if (pc_in_dummy_frame (get_frame_pc (frame)))
+ return get_frame_base (frame);
+
+ if (get_frame_type (frame) == SIGTRAMP_FRAME
+ || i386_frameless_signal_p (frame))
+ return get_frame_base (frame);
+
+ return read_memory_unsigned_integer (get_frame_base (frame), 4);
+}
static void
i386_cygwin_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
tdep->struct_return = reg_struct_return;
+ set_gdbarch_deprecated_frame_chain (gdbarch, i386_cygwin_frame_chain);
+ set_gdbarch_deprecated_frame_chain_valid (gdbarch, i386_cygwin_frame_chain_valid);
}
static enum gdb_osabi
if (fromleaf)
{
- frame->pc = SAVED_PC_AFTER_CALL (frame->next);
+ frame->pc = DEPRECATED_SAVED_PC_AFTER_CALL (frame->next);
return;
}
{
/* We know we're in a system call mini-frame; was it
NullApi or something else? */
- ra = SAVED_PC_AFTER_CALL (frame);
+ ra = DEPRECATED_SAVED_PC_AFTER_CALL (frame);
if (ra >= null_start && ra < null_end)
deprecated_set_frame_type (frame, SIGTRAMP_FRAME);
/* There might also be an indirect call to the mini-frame,
/* Which ptrace request retrieves which registers?
These apply to the corresponding SET requests as well. */
+
#define GETREGS_SUPPLIES(regno) \
((0 <= (regno) && (regno) <= 15) || (regno) == I386_LINUX_ORIG_EAX_REGNUM)
+
#define GETFPREGS_SUPPLIES(regno) \
(FP0_REGNUM <= (regno) && (regno) <= LAST_FPU_CTRL_REGNUM)
+
#define GETFPXREGS_SUPPLIES(regno) \
(FP0_REGNUM <= (regno) && (regno) <= MXCSR_REGNUM)
}
/* GNU/Linux LWP ID's are process ID's. */
- if ((tid = TIDGET (inferior_ptid)) == 0)
- tid = PIDGET (inferior_ptid); /* Not a threaded program. */
+ tid = TIDGET (inferior_ptid);
+ if (tid == 0)
+ tid = PIDGET (inferior_ptid); /* Not a threaded program. */
errno = 0;
val = ptrace (PTRACE_PEEKUSER, tid, register_addr (regno, 0), 0);
return;
/* GNU/Linux LWP ID's are process ID's. */
- if ((tid = TIDGET (inferior_ptid)) == 0)
- tid = PIDGET (inferior_ptid); /* Not a threaded program. */
+ tid = TIDGET (inferior_ptid);
+ if (tid == 0)
+ tid = PIDGET (inferior_ptid); /* Not a threaded program. */
errno = 0;
regcache_collect (regno, &val);
ptrace (PTRACE_POKEUSER, tid, register_addr (regno, 0), val);
if (errno != 0)
- error ("Couldn't read register %s (#%d): %s.", REGISTER_NAME (regno),
+ error ("Couldn't write register %s (#%d): %s.", REGISTER_NAME (regno),
regno, safe_strerror (errno));
}
\f
}
/* GNU/Linux LWP ID's are process ID's. */
- if ((tid = TIDGET (inferior_ptid)) == 0)
- tid = PIDGET (inferior_ptid); /* Not a threaded program. */
+ tid = TIDGET (inferior_ptid);
+ if (tid == 0)
+ tid = PIDGET (inferior_ptid); /* Not a threaded program. */
/* Use the PTRACE_GETFPXREGS request whenever possible, since it
transfers more registers in one system call, and we'll cache the
}
/* GNU/Linux LWP ID's are process ID's. */
- if ((tid = TIDGET (inferior_ptid)) == 0)
- tid = PIDGET (inferior_ptid); /* Not a threaded program. */
+ tid = TIDGET (inferior_ptid);
+ if (tid == 0)
+ tid = PIDGET (inferior_ptid); /* Not a threaded program. */
/* Use the PTRACE_SETFPXREGS requests whenever possible, since it
transfers more registers in one system call. But remember that
= lookup_minimal_symbol ("fixup", NULL, objfile);
if (fixup && SYMBOL_VALUE_ADDRESS (fixup) == pc)
- return (SAVED_PC_AFTER_CALL (get_current_frame ()));
+ return (DEPRECATED_SAVED_PC_AFTER_CALL (get_current_frame ()));
}
return 0;
/* Names of the registers. The first 10 registers match the register
numbering scheme used by GCC for stabs and DWARF. */
+
static char *i386_register_names[] =
{
"eax", "ecx", "edx", "ebx",
"mxcsr"
};
+static const int i386_num_register_names =
+ (sizeof (i386_register_names) / sizeof (*i386_register_names));
+
/* MMX registers. */
static char *i386_mmx_names[] =
"mm0", "mm1", "mm2", "mm3",
"mm4", "mm5", "mm6", "mm7"
};
-static const int mmx_num_regs = (sizeof (i386_mmx_names)
- / sizeof (i386_mmx_names[0]));
-#define MM0_REGNUM (NUM_REGS)
+
+static const int i386_num_mmx_regs =
+ (sizeof (i386_mmx_names) / sizeof (i386_mmx_names[0]));
+
+#define MM0_REGNUM NUM_REGS
static int
-i386_mmx_regnum_p (int reg)
+i386_mmx_regnum_p (int regnum)
{
- return (reg >= MM0_REGNUM && reg < MM0_REGNUM + mmx_num_regs);
+ return (regnum >= MM0_REGNUM
+ && regnum < MM0_REGNUM + i386_num_mmx_regs);
}
/* FP register? */
i386_fp_regnum_p (int regnum)
{
return (regnum < NUM_REGS
- && (FP0_REGNUM && FP0_REGNUM <= (regnum) && (regnum) < FPC_REGNUM));
+ && (FP0_REGNUM && FP0_REGNUM <= regnum && regnum < FPC_REGNUM));
}
int
i386_fpc_regnum_p (int regnum)
{
return (regnum < NUM_REGS
- && (FPC_REGNUM <= (regnum) && (regnum) < XMM0_REGNUM));
+ && (FPC_REGNUM <= regnum && regnum < XMM0_REGNUM));
}
/* SSE register? */
i386_sse_regnum_p (int regnum)
{
return (regnum < NUM_REGS
- && (XMM0_REGNUM <= (regnum) && (regnum) < MXCSR_REGNUM));
+ && (XMM0_REGNUM <= regnum && regnum < MXCSR_REGNUM));
}
int
i386_mxcsr_regnum_p (int regnum)
{
return (regnum < NUM_REGS
- && (regnum == MXCSR_REGNUM));
+ && regnum == MXCSR_REGNUM);
}
/* Return the name of register REG. */
const char *
i386_register_name (int reg)
{
- if (reg < 0)
- return NULL;
+ if (reg >= 0 && reg < i386_num_register_names)
+ return i386_register_names[reg];
+
if (i386_mmx_regnum_p (reg))
return i386_mmx_names[reg - MM0_REGNUM];
- if (reg >= sizeof (i386_register_names) / sizeof (*i386_register_names))
- return NULL;
- return i386_register_names[reg];
+ return NULL;
}
/* Convert stabs register number REG to the appropriate register
return read_memory_unsigned_integer (read_register (SP_REGNUM), 4);
}
-/* Return number of args passed to a frame.
- Can return -1, meaning no way to tell. */
-
-static int
-i386_frame_num_args (struct frame_info *fi)
-{
-#if 1
- return -1;
-#else
- /* This loses because not only might the compiler not be popping the
- args right after the function call, it might be popping args from
- both this call and a previous one, and we would say there are
- more args than there really are. */
-
- int retpc;
- unsigned char op;
- struct frame_info *pfi;
-
- /* On the i386, the instruction following the call could be:
- popl %ecx - one arg
- addl $imm, %esp - imm/4 args; imm may be 8 or 32 bits
- anything else - zero args. */
-
- int frameless;
-
- frameless = FRAMELESS_FUNCTION_INVOCATION (fi);
- if (frameless)
- /* In the absence of a frame pointer, GDB doesn't get correct
- values for nameless arguments. Return -1, so it doesn't print
- any nameless arguments. */
- return -1;
-
- pfi = get_prev_frame (fi);
- if (pfi == 0)
- {
- /* NOTE: This can happen if we are looking at the frame for
- main, because DEPRECATED_FRAME_CHAIN_VALID won't let us go
- into start. If we have debugging symbols, that's not really
- a big deal; it just means it will only show as many arguments
- to main as are declared. */
- return -1;
- }
- else
- {
- retpc = pfi->pc;
- op = read_memory_integer (retpc, 1);
- if (op == 0x59) /* pop %ecx */
- return 1;
- else if (op == 0x83)
- {
- op = read_memory_integer (retpc + 1, 1);
- if (op == 0xc4)
- /* addl $<signed imm 8 bits>, %esp */
- return (read_memory_integer (retpc + 2, 1) & 0xff) / 4;
- else
- return 0;
- }
- else if (op == 0x81) /* `add' with 32 bit immediate. */
- {
- op = read_memory_integer (retpc + 1, 1);
- if (op == 0xc4)
- /* addl $<imm 32>, %esp */
- return read_memory_integer (retpc + 2, 4) / 4;
- else
- return 0;
- }
- else
- {
- return 0;
- }
- }
-#endif
-}
-
/* Parse the first few instructions the function to see what registers
were stored.
char buf[8];
CORE_ADDR sp, jb_addr;
int jb_pc_offset = gdbarch_tdep (current_gdbarch)->jb_pc_offset;
- int len = TARGET_PTR_BIT / TARGET_CHAR_BIT;
+ int len = TYPE_LENGTH (builtin_type_void_func_ptr);
/* If JB_PC_OFFSET is -1, we have no way to find out where the
longjmp will land. */
if (target_read_memory (sp + len, buf, len))
return 0;
- jb_addr = extract_address (buf, len);
+ jb_addr = extract_typed_address (buf, builtin_type_void_func_ptr);
if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
return 0;
- *pc = extract_address (buf, len);
+ *pc = extract_typed_address (buf, builtin_type_void_func_ptr);
return 1;
}
\f
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- if (FP0_REGNUM == 0)
+ if (FP0_REGNUM < 0)
{
warning ("Cannot find floating-point return value.");
memset (valbuf, 0, len);
ULONGEST fstat;
char buf[FPU_REG_RAW_SIZE];
- if (FP0_REGNUM == 0)
+ if (FP0_REGNUM < 0)
{
warning ("Cannot set floating-point return value.");
return;
}
/* Map a cooked register onto a raw register or memory. For the i386,
- the MMX registers need to be mapped onto floating point registers. */
+ the MMX registers need to be mapped onto floating-point registers. */
static int
-mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
+i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
{
int mmxi;
ULONGEST fstat;
int tos;
int fpi;
+
mmxi = regnum - MM0_REGNUM;
regcache_raw_read_unsigned (regcache, FSTAT_REGNUM, &fstat);
tos = (fstat >> 11) & 0x7;
fpi = (mmxi + tos) % 8;
+
return (FP0_REGNUM + fpi);
}
if (i386_mmx_regnum_p (regnum))
{
char *mmx_buf = alloca (MAX_REGISTER_RAW_SIZE);
- int fpnum = mmx_regnum_to_fp_regnum (regcache, regnum);
- regcache_raw_read (regcache, fpnum, mmx_buf);
+ int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
+
/* Extract (always little endian). */
+ regcache_raw_read (regcache, fpnum, mmx_buf);
memcpy (buf, mmx_buf, REGISTER_RAW_SIZE (regnum));
}
else
if (i386_mmx_regnum_p (regnum))
{
char *mmx_buf = alloca (MAX_REGISTER_RAW_SIZE);
- int fpnum = mmx_regnum_to_fp_regnum (regcache, regnum);
+ int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
+
/* Read ... */
regcache_raw_read (regcache, fpnum, mmx_buf);
/* ... Modify ... (always little endian). */
i386_frameless_function_invocation);
set_gdbarch_deprecated_frame_chain (gdbarch, i386_frame_chain);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, i386_frame_saved_pc);
- set_gdbarch_saved_pc_after_call (gdbarch, i386_saved_pc_after_call);
- set_gdbarch_frame_num_args (gdbarch, i386_frame_num_args);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, i386_saved_pc_after_call);
+ set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
set_gdbarch_pc_in_sigtramp (gdbarch, i386_pc_in_sigtramp);
/* Wire in the MMX registers. */
#ifndef I386_TDEP_H
#define I386_TDEP_H
+struct reggroup;
+struct gdbarch;
+struct frame_info;
+
/* GDB's i386 target supports both the 32-bit Intel Architecture
(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
a similar register layout for both.
static void
i386lynx_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
- set_gdbarch_saved_pc_after_call (gdbarch, i386lynx_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, i386lynx_saved_pc_after_call);
}
\f
/* Intel 387 floating point stuff.
+
Copyright 1988, 1989, 1991, 1992, 1993, 1994, 1998, 1999, 2000,
- 2001, 2002 Free Software Foundation, Inc.
+ 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of GDB.
#include "i386-tdep.h"
-/* FIXME: Eliminate the next two functions when we have the time to
- change all the callers. */
-
-void i387_to_double (char *from, char *to);
-void double_to_i387 (char *from, char *to);
-
-void
-i387_to_double (char *from, char *to)
-{
- floatformat_to_double (&floatformat_i387_ext, from, (double *) to);
-}
-
-void
-double_to_i387 (char *from, char *to)
-{
- floatformat_from_double (&floatformat_i387_ext, (double *) from, to);
-}
-
\f
/* FIXME: The functions on this page are used by the old `info float'
implementations that a few of the i386 targets provide. These
#ifndef I387_TDEP_H
#define I387_TDEP_H
+struct gdbarch;
+struct ui_file;
+struct frame_info;
+
/* Print out the i387 floating point state. */
extern void i387_print_float_info (struct gdbarch *gdbarch,
static gdbarch_deprecated_extract_struct_value_address_ftype ia64_extract_struct_value_address;
static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
static gdbarch_frameless_function_invocation_ftype ia64_frameless_function_invocation;
-static gdbarch_saved_pc_after_call_ftype ia64_saved_pc_after_call;
+static gdbarch_deprecated_saved_pc_after_call_ftype ia64_saved_pc_after_call;
static void ia64_pop_frame_regular (struct frame_info *frame);
static struct type *is_float_or_hfa_type (struct type *t);
{
DOUBLEST val;
floatformat_to_doublest (&floatformat_ia64_ext, from, &val);
- store_floating(to, TYPE_LENGTH(type), val);
+ deprecated_store_floating (to, TYPE_LENGTH(type), val);
}
else
error("ia64_register_convert_to_virtual called with non floating point register number");
{
if (regnum >= IA64_FR0_REGNUM && regnum <= IA64_FR127_REGNUM)
{
- DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
+ DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
floatformat_from_doublest (&floatformat_ia64_ext, &val, to);
}
else
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
set_gdbarch_frameless_function_invocation (gdbarch, ia64_frameless_function_invocation);
- set_gdbarch_saved_pc_after_call (gdbarch, ia64_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, ia64_saved_pc_after_call);
set_gdbarch_deprecated_frame_chain (gdbarch, ia64_frame_chain);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, ia64_frame_saved_pc);
/* No traps are generated when attaching to inferior under Mach 3
or GNU hurd. */
#ifndef ATTACH_NO_WAIT
- stop_soon_quietly = 1;
+ /* Careful here. See comments in inferior.h. Basically some OSes
+ don't ignore SIGSTOPs on continue requests anymore. We need a
+ way for handle_inferior_event to reset the stop_signal variable
+ after an attach, and this is what STOP_QUIETLY_NO_SIGSTOP is for. */
+ stop_soon = STOP_QUIETLY_NO_SIGSTOP;
wait_for_inferior ();
+ stop_soon = NO_STOP_QUIETLY;
#endif
/*
#if !defined (INFERIOR_H)
#define INFERIOR_H 1
+struct target_waitstatus;
+struct frame_info;
+struct ui_file;
+struct type;
struct gdbarch;
struct regcache;
extern int step_multi;
-/* Nonzero means expecting a trap and caller will handle it themselves.
- It is used after attach, due to attaching to a process;
- when running in the shell before the child program has been exec'd;
- and when running some kinds of remote stuff (FIXME?). */
+/* Nonzero means expecting a trap and caller will handle it
+ themselves. It is used when running in the shell before the child
+ program has been exec'd; and when running some kinds of remote
+ stuff (FIXME?). */
+
+/* It is also used after attach, due to attaching to a process. This
+ is a bit trickier. When doing an attach, the kernel stops the
+ debuggee with a SIGSTOP. On newer GNU/Linux kernels (>= 2.5.61)
+ the handling of SIGSTOP for a ptraced process has changed. Earlier
+ versions of the kernel would ignore these SIGSTOPs, while now
+ SIGSTOP is treated like any other signal, i.e. it is not muffled.
+
+ If the gdb user does a 'continue' after the 'attach', gdb passes
+ the global variable stop_signal (which stores the signal from the
+ attach, SIGSTOP) to the ptrace(PTRACE_CONT,...) call. This is
+ problematic, because the kernel doesn't ignore such SIGSTOP
+ now. I.e. it is reported back to gdb, which in turn presents it
+ back to the user.
+
+ To avoid the problem, we use STOP_QUIETLY_NO_SIGSTOP, which allows
+ gdb to clear the value of stop_signal after the attach, so that it
+ is not passed back down to the kernel. */
+
+enum stop_kind
+ {
+ NO_STOP_QUIETLY = 0,
+ STOP_QUIETLY,
+ STOP_QUIETLY_NO_SIGSTOP
+ };
-extern int stop_soon_quietly;
+extern enum stop_kind stop_soon;
/* Nonzero if proceed is being used for a "finish" command or a similar
situation when stop_registers should be saved. */
when running in the shell before the child program has been exec'd;
and when running some kinds of remote stuff (FIXME?). */
-int stop_soon_quietly;
+enum stop_kind stop_soon;
/* Nonzero if proceed is being used for a "finish" command or a similar
situation when stop_registers should be saved. */
step_frame_id = null_frame_id;
step_over_calls = STEP_OVER_UNDEBUGGABLE;
stop_after_trap = 0;
- stop_soon_quietly = 0;
+ stop_soon = NO_STOP_QUIETLY;
proceed_to_finish = 0;
breakpoint_proceeded = 1; /* We're about to proceed... */
to be preserved over calls to it and cleared when the inferior
is started. */
static CORE_ADDR prev_pc;
-static CORE_ADDR prev_func_start;
static char *prev_func_name;
\f
{
init_thread_list ();
init_wait_for_inferior ();
- stop_soon_quietly = 1;
+ stop_soon = STOP_QUIETLY;
trap_expected = 0;
/* Always go on waiting for the target, regardless of the mode. */
{
/* These are meaningless until the first time through wait_for_inferior. */
prev_pc = 0;
- prev_func_start = 0;
prev_func_name = NULL;
#ifdef HP_OS_BUG
if (in_thread_list (inferior_ptid) && in_thread_list (ecs->ptid))
{ /* Perform infrun state context switch: */
/* Save infrun state for the old thread. */
- save_infrun_state (inferior_ptid, prev_pc,
- prev_func_start, prev_func_name,
+ save_infrun_state (inferior_ptid, prev_pc, prev_func_name,
trap_expected, step_resume_breakpoint,
through_sigtramp_breakpoint, step_range_start,
step_range_end, &step_frame_id,
ecs->current_line, ecs->current_symtab, step_sp);
/* Load infrun state for the new thread. */
- load_infrun_state (ecs->ptid, &prev_pc,
- &prev_func_start, &prev_func_name,
+ load_infrun_state (ecs->ptid, &prev_pc, &prev_func_name,
&trap_expected, &step_resume_breakpoint,
&through_sigtramp_breakpoint, &step_range_start,
&step_range_end, &step_frame_id,
might be the shell which has just loaded some objects,
otherwise add the symbols for the newly loaded objects. */
#ifdef SOLIB_ADD
- if (!stop_soon_quietly)
+ if (stop_soon == NO_STOP_QUIETLY)
{
/* Remove breakpoints, SOLIB_ADD might adjust
breakpoint addresses via breakpoint_re_set. */
if (stop_signal == TARGET_SIGNAL_TRAP
|| (breakpoints_inserted &&
(stop_signal == TARGET_SIGNAL_ILL
- || stop_signal == TARGET_SIGNAL_EMT)) || stop_soon_quietly)
+ || stop_signal == TARGET_SIGNAL_EMT))
+ || stop_soon == STOP_QUIETLY
+ || stop_soon == STOP_QUIETLY_NO_SIGSTOP)
{
if (stop_signal == TARGET_SIGNAL_TRAP && stop_after_trap)
{
stop_stepping (ecs);
return;
}
- if (stop_soon_quietly)
+
+ /* This is originated from start_remote(), start_inferior() and
+ shared libraries hook functions. */
+ if (stop_soon == STOP_QUIETLY)
+ {
+ stop_stepping (ecs);
+ return;
+ }
+
+ /* This originates from attach_command(). We need to overwrite
+ the stop_signal here, because some kernels don't ignore a
+ SIGSTOP in a subsequent ptrace(PTRACE_SONT,SOGSTOP) call.
+ See more comments in inferior.h. */
+ if (stop_soon == STOP_QUIETLY_NO_SIGSTOP)
{
stop_stepping (ecs);
+ if (stop_signal == TARGET_SIGNAL_STOP)
+ stop_signal = TARGET_SIGNAL_0;
return;
}
struct symtab_and_line sr_sal;
init_sal (&sr_sal); /* initialize to zeros */
- sr_sal.pc = ADDR_BITS_REMOVE (SAVED_PC_AFTER_CALL (get_current_frame ()));
+
+ /* NOTE: cagney/2003-04-06:
+
+ At this point the equality get_frame_pc() == get_frame_func()
+ should hold. This may make it possible for this code to tell the
+ frame where it's function is, instead of the reverse. This would
+ avoid the need to search for the frame's function, which can get
+ very messy when there is no debug info available (look at the
+ heuristic find pc start code found in targets like the MIPS). */
+
+ /* NOTE: cagney/2003-04-06:
+
+ The intent of DEPRECATED_SAVED_PC_AFTER_CALL was to:
+
+ - provide a very light weight equivalent to frame_unwind_pc()
+ (nee FRAME_SAVED_PC) that avoids the prologue analyzer
+
+ - avoid handling the case where the PC hasn't been saved in the
+ prologue analyzer
+
+ Unfortunatly, not five lines further down, is a call to
+ get_frame_id() and that is guarenteed to trigger the prologue
+ analyzer.
+
+ The `correct fix' is for the prologe analyzer to handle the case
+ where the prologue is incomplete (PC in prologue) and,
+ consequently, the return pc has not yet been saved. It should be
+ noted that the prologue analyzer needs to handle this case
+ anyway: frameless leaf functions that don't save the return PC;
+ single stepping through a prologue.
+
+ The d10v handles all this by bailing out of the prologue analsis
+ when it reaches the current instruction. */
+
+ if (DEPRECATED_SAVED_PC_AFTER_CALL_P ())
+ sr_sal.pc = ADDR_BITS_REMOVE (DEPRECATED_SAVED_PC_AFTER_CALL (get_current_frame ()));
+ else
+ sr_sal.pc = ADDR_BITS_REMOVE (frame_pc_unwind (get_current_frame ()));
sr_sal.section = find_pc_overlay (sr_sal.pc);
check_for_old_step_resume_breakpoint ();
time, just like we did above if we didn't break out of the
loop. */
prev_pc = read_pc ();
- prev_func_start = ecs->stop_func_start;
prev_func_name = ecs->stop_func_name;
}
{
/* Save the pc before execution, to compare with pc after stop. */
prev_pc = read_pc (); /* Might have been DECR_AFTER_BREAK */
- prev_func_start = ecs->stop_func_start; /* Ok, since if DECR_PC_AFTER
- BREAK is defined, the
- original pc would not have
- been at the start of a
- function. */
prev_func_name = ecs->stop_func_name;
if (ecs->update_step_sp)
enum step_over_calls_kind step_over_calls;
CORE_ADDR step_resume_break_address;
int stop_after_trap;
- int stop_soon_quietly;
+ int stop_soon;
struct regcache *stop_registers;
/* These are here because if call_function_by_hand has written some
inf_status->step_frame_id = step_frame_id;
inf_status->step_over_calls = step_over_calls;
inf_status->stop_after_trap = stop_after_trap;
- inf_status->stop_soon_quietly = stop_soon_quietly;
+ inf_status->stop_soon = stop_soon;
/* Save original bpstat chain here; replace it with copy of chain.
If caller's caller is walking the chain, they'll be happier if we
hand them back the original chain when restore_inferior_status is
step_frame_id = inf_status->step_frame_id;
step_over_calls = inf_status->step_over_calls;
stop_after_trap = inf_status->stop_after_trap;
- stop_soon_quietly = inf_status->stop_soon_quietly;
+ stop_soon = inf_status->stop_soon;
bpstat_clear (&stop_bpstat);
stop_bpstat = inf_status->stop_bpstat;
breakpoint_proceeded = inf_status->breakpoint_proceeded;
BLOCK_END (bl) = 0;
BLOCK_FUNCTION (bl) = NULL;
BLOCK_SUPERBLOCK (bl) = NULL;
+ BLOCK_NAMESPACE (bl) = NULL;
BLOCK_GCC_COMPILED (bl) = 0;
BLOCKVECTOR_BLOCK (bv, STATIC_BLOCK) = bl;
struct value;
struct objfile;
struct expression;
+struct ui_file;
+
/* enum exp_opcode; ANSI's `wisdom' didn't include forward enum decls. */
/* This used to be included to configure GDB for one or more specific
#if !defined (LINESPEC_H)
#define LINESPEC_H 1
+struct symtab;
+
extern struct symtabs_and_lines
decode_line_1 (char **argptr, int funfirstline,
struct symtab *default_symtab, int default_line,
-/* Interface GDB to Mach 3.0 operating systems.
- (Most) Mach 3.0 related routines live in this file.
-
- Copyright 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
- 2002 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/*
- * Author: Jukka Virtanen <jtv@hut.fi>
- * Computing Centre
- * Helsinki University of Technology
- * Finland
- *
- * Thanks to my friends who helped with ideas and testing:
- *
- * Johannes Helander, Antti Louko, Tero Mononen,
- * jvh@cs.hut.fi alo@hut.fi tmo@cs.hut.fi
- *
- * Tero Kivinen and Eamonn McManus
- * kivinen@cs.hut.fi emcmanus@gr.osf.org
- *
- */
-
-#include <stdio.h>
-
-#include <mach.h>
-#include <servers/netname.h>
-#include <servers/machid.h>
-#include <mach/message.h>
-#include <mach/notify.h>
-#include <mach_error.h>
-#include <mach/exception.h>
-#include <mach/vm_attributes.h>
-
-#include "defs.h"
-#include "inferior.h"
-#include "symtab.h"
-#include "value.h"
-#include "language.h"
-#include "target.h"
-#include "gdb_wait.h"
-#include "gdbcmd.h"
-#include "gdbcore.h"
-#include "regcache.h"
-
-#if 0
-#include <servers/machid_lib.h>
-#else
-#define MACH_TYPE_TASK 1
-#define MACH_TYPE_THREAD 2
-#endif
-
-/* Included only for signal names and NSIG
-
- * note: There are many problems in signal handling with
- * gdb in Mach 3.0 in general.
- */
-#include <signal.h>
-#define SIG_UNKNOWN 0 /* Exception that has no matching unix signal */
-
-#include <cthreads.h>
-
-/* This is what a cproc looks like. This is here partly because
- cthread_internals.h is not a header we can just #include, partly with
- an eye towards perhaps getting this to work with cross-debugging
- someday. Best solution is if CMU publishes a real interface to this
- stuff. */
-#define CPROC_NEXT_OFFSET 0
-#define CPROC_NEXT_SIZE (TARGET_PTR_BIT / HOST_CHAR_BIT)
-#define CPROC_INCARNATION_OFFSET (CPROC_NEXT_OFFSET + CPROC_NEXT_SIZE)
-#define CPROC_INCARNATION_SIZE (sizeof (cthread_t))
-#define CPROC_LIST_OFFSET (CPROC_INCARNATION_OFFSET + CPROC_INCARNATION_SIZE)
-#define CPROC_LIST_SIZE (TARGET_PTR_BIT / HOST_CHAR_BIT)
-#define CPROC_WAIT_OFFSET (CPROC_LIST_OFFSET + CPROC_LIST_SIZE)
-#define CPROC_WAIT_SIZE (TARGET_PTR_BIT / HOST_CHAR_BIT)
-#define CPROC_REPLY_OFFSET (CPROC_WAIT_OFFSET + CPROC_WAIT_SIZE)
-#define CPROC_REPLY_SIZE (sizeof (mach_port_t))
-#define CPROC_CONTEXT_OFFSET (CPROC_REPLY_OFFSET + CPROC_REPLY_SIZE)
-#define CPROC_CONTEXT_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
-#define CPROC_LOCK_OFFSET (CPROC_CONTEXT_OFFSET + CPROC_CONTEXT_SIZE)
-#define CPROC_LOCK_SIZE (sizeof (spin_lock_t))
-#define CPROC_STATE_OFFSET (CPROC_LOCK_OFFSET + CPROC_LOCK_SIZE)
-#define CPROC_STATE_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
-#define CPROC_WIRED_OFFSET (CPROC_STATE_OFFSET + CPROC_STATE_SIZE)
-#define CPROC_WIRED_SIZE (sizeof (mach_port_t))
-#define CPROC_BUSY_OFFSET (CPROC_WIRED_OFFSET + CPROC_WIRED_SIZE)
-#define CPROC_BUSY_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
-#define CPROC_MSG_OFFSET (CPROC_BUSY_OFFSET + CPROC_BUSY_SIZE)
-#define CPROC_MSG_SIZE (sizeof (mach_msg_header_t))
-#define CPROC_BASE_OFFSET (CPROC_MSG_OFFSET + CPROC_MSG_SIZE)
-#define CPROC_BASE_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
-#define CPROC_SIZE_OFFSET (CPROC_BASE_OFFSET + CPROC_BASE_SIZE)
-#define CPROC_SIZE_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
-#define CPROC_SIZE (CPROC_SIZE_OFFSET + CPROC_SIZE_SIZE)
-
-/* Values for the state field in the cproc. */
-#define CPROC_RUNNING 0
-#define CPROC_SWITCHING 1
-#define CPROC_BLOCKED 2
-#define CPROC_CONDWAIT 4
-
-/* For cproc and kernel thread mapping */
-typedef struct gdb_thread
- {
- mach_port_t name;
- CORE_ADDR sp;
- CORE_ADDR pc;
- CORE_ADDR fp;
- boolean_t in_emulator;
- int slotid;
-
- /* This is for the mthreads list. It points to the cproc list.
- Perhaps the two lists should be merged (or perhaps it was a mistake
- to make them both use a struct gdb_thread). */
- struct gdb_thread *cproc;
-
- /* These are for the cproc list, which is linked through the next field
- of the struct gdb_thread. */
- char raw_cproc[CPROC_SIZE];
- /* The cthread which is pointed to by the incarnation field from the
- cproc. This points to the copy we've read into GDB. */
- cthread_t cthread;
- /* Point back to the mthreads list. */
- int reverse_map;
- struct gdb_thread *next;
- }
- *gdb_thread_t;
-
-/*
- * Actions for Mach exceptions.
- *
- * sigmap field maps the exception to corresponding Unix signal.
- *
- * I do not know how to map the exception to unix signal
- * if SIG_UNKNOWN is specified.
- */
-
-struct exception_list
- {
- char *name;
- boolean_t forward;
- boolean_t print;
- int sigmap;
- }
-exception_map[] =
-{
- {
- "not_mach3_exception", FALSE, TRUE, SIG_UNKNOWN
- }
- ,
- {
- "EXC_BAD_ACCESS", FALSE, TRUE, SIGSEGV
- }
- ,
- {
- "EXC_BAD_INSTRUCTION", FALSE, TRUE, SIGILL
- }
- ,
- {
- "EXC_ARITHMETIC", FALSE, TRUE, SIGFPE
- }
- ,
- {
- "EXC_EMULATION", FALSE, TRUE, SIGEMT
- }
- , /* ??? */
- {
- "EXC_SOFTWARE", FALSE, TRUE, SIG_UNKNOWN
- }
- ,
- {
- "EXC_BREAKPOINT", FALSE, FALSE, SIGTRAP
- }
-};
-
-/* Mach exception table size */
-int max_exception = sizeof (exception_map) / sizeof (struct exception_list) - 1;
-
-#define MAX_EXCEPTION max_exception
-
-WAITTYPE wait_status;
-
-/* If you define this, intercepted bsd server calls will be
- * dumped while waiting the inferior to EXEC the correct
- * program
- */
-/* #define DUMP_SYSCALL /* debugging interceptor */
-
-/* xx_debug() outputs messages if this is nonzero.
- * If > 1, DUMP_SYSCALL will dump message contents.
- */
-int debug_level = 0;
-
-/* "Temporary" debug stuff */
-void
-xx_debug (char *fmt, int a, int b, int c)
-{
- if (debug_level)
- warning (fmt, a, b, c);
-}
-
-/* This is in libmach.a */
-extern mach_port_t name_server_port;
-
-/* Set in catch_exception_raise */
-int stop_exception, stop_code, stop_subcode;
-int stopped_in_exception;
-
-/* Thread that was the active thread when we stopped */
-thread_t stop_thread = MACH_PORT_NULL;
-
-char *hostname = "";
-
-/* Set when task is attached or created */
-boolean_t emulator_present = FALSE;
-
-task_t inferior_task;
-thread_t current_thread;
-
-/* Exception ports for inferior task */
-mach_port_t inferior_exception_port = MACH_PORT_NULL;
-mach_port_t inferior_old_exception_port = MACH_PORT_NULL;
-
-/* task exceptions and notifications */
-mach_port_t inferior_wait_port_set = MACH_PORT_NULL;
-mach_port_t our_notify_port = MACH_PORT_NULL;
-
-/* This is "inferior_wait_port_set" when not single stepping, and
- * "singlestepped_thread_port" when we are single stepping.
- *
- * This is protected by a cleanup function: discard_single_step()
- */
-mach_port_t currently_waiting_for = MACH_PORT_NULL;
-
-/* A port for external messages to gdb.
- * External in the meaning that they do not come
- * from the inferior_task, but rather from external
- * tasks.
- *
- * As a debugging feature:
- * A debugger debugging another debugger can stop the
- * inferior debugger by the following command sequence
- * (without running external programs)
- *
- * (top-gdb) set stop_inferior_gdb ()
- * (top-gdb) continue
- */
-mach_port_t our_message_port = MACH_PORT_NULL;
-
-/* For single stepping */
-mach_port_t thread_exception_port = MACH_PORT_NULL;
-mach_port_t thread_saved_exception_port = MACH_PORT_NULL;
-mach_port_t singlestepped_thread_port = MACH_PORT_NULL;
-
-/* For machid calls */
-mach_port_t mid_server = MACH_PORT_NULL;
-mach_port_t mid_auth = MACH_PORT_NULL;
-
-/* If gdb thinks the inferior task is not suspended, it
- * must take suspend/abort the threads when it reads the state.
- */
-int must_suspend_thread = 0;
-
-/* When single stepping, we switch the port that mach_really_wait() listens to.
- * This cleanup is a guard to prevent the port set from being left to
- * the singlestepped_thread_port when error() is called.
- * This is nonzero only when we are single stepping.
- */
-#define NULL_CLEANUP (struct cleanup *)0
-struct cleanup *cleanup_step = NULL_CLEANUP;
-\f
-
-static struct target_ops m3_ops;
-
-static void m3_kill_inferior ();
-\f
-#if 0
-#define MACH_TYPE_EXCEPTION_PORT -1
-#endif
-
-/* Chain of ports to remember requested notifications. */
-
-struct port_chain
- {
- struct port_chain *next;
- mach_port_t port;
- int type;
- int mid; /* Now only valid with MACH_TYPE_THREAD and */
- /* MACH_TYPE_THREAD */
- };
-typedef struct port_chain *port_chain_t;
-
-/* Room for chain nodes comes from pchain_obstack */
-struct obstack pchain_obstack;
-struct obstack *port_chain_obstack = &pchain_obstack;
-
-/* For thread handling */
-struct obstack Cproc_obstack;
-struct obstack *cproc_obstack = &Cproc_obstack;
-
-/* the list of notified ports */
-port_chain_t notify_chain = (port_chain_t) NULL;
-
-port_chain_t
-port_chain_insert (port_chain_t list, mach_port_t name, int type)
-{
- kern_return_t ret;
- port_chain_t new;
- int mid;
-
- if (!MACH_PORT_VALID (name))
- return list;
-
- if (type == MACH_TYPE_TASK || type == MACH_TYPE_THREAD)
- {
- if (!MACH_PORT_VALID (mid_server))
- {
- warning ("Machid server port invalid, can not map port 0x%x to MID",
- name);
- mid = name;
- }
- else
- {
- ret = machid_mach_register (mid_server, mid_auth, name, type, &mid);
-
- if (ret != KERN_SUCCESS)
- {
- warning ("Can not map name (0x%x) to MID with machid", name);
- mid = name;
- }
- }
- }
- else
- internal_error (__FILE__, __LINE__, "failed internal consistency check");
-
- new = (port_chain_t) obstack_alloc (port_chain_obstack,
- sizeof (struct port_chain));
- new->next = list;
- new->port = name;
- new->type = type;
- new->mid = mid;
-
- return new;
-}
-
-port_chain_t
-port_chain_delete (port_chain_t list, mach_port_t elem)
-{
- if (list)
- if (list->port == elem)
- list = list->next;
- else
- while (list->next)
- {
- if (list->next->port == elem)
- list->next = list->next->next; /* GCd with obstack_free() */
- else
- list = list->next;
- }
- return list;
-}
-
-void
-port_chain_destroy (struct obstack *ostack)
-{
- obstack_free (ostack, 0);
- obstack_init (ostack);
-}
-
-port_chain_t
-port_chain_member (port_chain_t list, mach_port_t elem)
-{
- while (list)
- {
- if (list->port == elem)
- return list;
- list = list->next;
- }
- return (port_chain_t) NULL;
-}
-\f
-int
-map_port_name_to_mid (mach_port_t name, int type)
-{
- port_chain_t elem;
-
- if (!MACH_PORT_VALID (name))
- return -1;
-
- elem = port_chain_member (notify_chain, name);
-
- if (elem && (elem->type == type))
- return elem->mid;
-
- if (elem)
- return -1;
-
- if (!MACH_PORT_VALID (mid_server))
- {
- warning ("Machid server port invalid, can not map port 0x%x to mid",
- name);
- return -1;
- }
- else
- {
- int mid;
- kern_return_t ret;
-
- ret = machid_mach_register (mid_server, mid_auth, name, type, &mid);
-
- if (ret != KERN_SUCCESS)
- {
- warning ("Can not map name (0x%x) to mid with machid", name);
- return -1;
- }
- return mid;
- }
-}
-\f
-/* Guard for currently_waiting_for and singlestepped_thread_port */
-static void
-discard_single_step (thread_t thread)
-{
- currently_waiting_for = inferior_wait_port_set;
-
- cleanup_step = NULL_CLEANUP;
- if (MACH_PORT_VALID (thread) && MACH_PORT_VALID (singlestepped_thread_port))
- setup_single_step (thread, FALSE);
-}
-
-setup_single_step (thread_t thread, boolean_t start_step)
-{
- kern_return_t ret;
-
- if (!MACH_PORT_VALID (thread))
- error ("Invalid thread supplied to setup_single_step");
- else
- {
- mach_port_t teport;
-
- /* Get the current thread exception port */
- ret = thread_get_exception_port (thread, &teport);
- CHK ("Getting thread's exception port", ret);
-
- if (start_step)
- {
- if (MACH_PORT_VALID (singlestepped_thread_port))
- {
- warning ("Singlestepped_thread_port (0x%x) is still valid?",
- singlestepped_thread_port);
- singlestepped_thread_port = MACH_PORT_NULL;
- }
-
- /* If we are already stepping this thread */
- if (MACH_PORT_VALID (teport) && teport == thread_exception_port)
- {
- ret = mach_port_deallocate (mach_task_self (), teport);
- CHK ("Could not deallocate thread exception port", ret);
- }
- else
- {
- ret = thread_set_exception_port (thread, thread_exception_port);
- CHK ("Setting exception port for thread", ret);
-#if 0
- /* Insert thread exception port to wait port set */
- ret = mach_port_move_member (mach_task_self (),
- thread_exception_port,
- inferior_wait_port_set);
- CHK ("Moving thread exception port to inferior_wait_port_set",
- ret);
-#endif
- thread_saved_exception_port = teport;
- }
-
- thread_trace (thread, TRUE);
-
- singlestepped_thread_port = thread_exception_port;
- currently_waiting_for = singlestepped_thread_port;
- cleanup_step = make_cleanup (discard_single_step, thread);
- }
- else
- {
- if (!MACH_PORT_VALID (teport))
- error ("Single stepped thread had an invalid exception port?");
-
- if (teport != thread_exception_port)
- error ("Single stepped thread had an unknown exception port?");
-
- ret = mach_port_deallocate (mach_task_self (), teport);
- CHK ("Couldn't deallocate thread exception port", ret);
-#if 0
- /* Remove thread exception port from wait port set */
- ret = mach_port_move_member (mach_task_self (),
- thread_exception_port,
- MACH_PORT_NULL);
- CHK ("Removing thread exception port from inferior_wait_port_set",
- ret);
-#endif
- /* Restore thread's old exception port */
- ret = thread_set_exception_port (thread,
- thread_saved_exception_port);
- CHK ("Restoring stepped thread's exception port", ret);
-
- if (MACH_PORT_VALID (thread_saved_exception_port))
- (void) mach_port_deallocate (mach_task_self (),
- thread_saved_exception_port);
-
- thread_trace (thread, FALSE);
-
- singlestepped_thread_port = MACH_PORT_NULL;
- currently_waiting_for = inferior_wait_port_set;
- if (cleanup_step)
- discard_cleanups (cleanup_step);
- }
- }
-}
-\f
-static
-request_notify (mach_port_t name, mach_msg_id_t variant, int type)
-{
- kern_return_t ret;
- mach_port_t previous_port_dummy = MACH_PORT_NULL;
-
- if (!MACH_PORT_VALID (name))
- return;
-
- if (port_chain_member (notify_chain, name))
- return;
-
- ret = mach_port_request_notification (mach_task_self (),
- name,
- variant,
- 1,
- our_notify_port,
- MACH_MSG_TYPE_MAKE_SEND_ONCE,
- &previous_port_dummy);
- CHK ("Serious: request_notify failed", ret);
-
- (void) mach_port_deallocate (mach_task_self (),
- previous_port_dummy);
-
- notify_chain = port_chain_insert (notify_chain, name, type);
-}
-
-reverse_msg_bits (mach_msg_header_t *msgp, int type)
-{
- int rbits, lbits;
- rbits = MACH_MSGH_BITS_REMOTE (msgp->msgh_bits);
- lbits = type;
- msgp->msgh_bits =
- (msgp->msgh_bits & ~MACH_MSGH_BITS_PORTS_MASK) |
- MACH_MSGH_BITS (lbits, rbits);
-}
-\f
-/* On the third day He said:
-
- Let this be global
- and then it was global.
-
- When creating the inferior fork, the
- child code in inflow.c sets the name of the
- bootstrap_port in its address space to this
- variable.
-
- The name is transferred to our address space
- with mach3_read_inferior().
-
- Thou shalt not do this with
- task_get_bootstrap_port() in this task, since
- the name in the inferior task is different than
- the one we get.
-
- For blessed are the meek, as they shall inherit
- the address space.
- */
-mach_port_t original_server_port_name = MACH_PORT_NULL;
-
-
-/* Called from inferior after FORK but before EXEC */
-static void
-m3_trace_me (void)
-{
- kern_return_t ret;
-
- /* Get the NAME of the bootstrap port in this task
- so that GDB can read it */
- ret = task_get_bootstrap_port (mach_task_self (),
- &original_server_port_name);
- if (ret != KERN_SUCCESS)
- internal_error (__FILE__, __LINE__, "failed internal consistency check");
- ret = mach_port_deallocate (mach_task_self (),
- original_server_port_name);
- if (ret != KERN_SUCCESS)
- internal_error (__FILE__, __LINE__, "failed internal consistency check");
-
- /* Suspend this task to let the parent change my ports.
- Resumed by the debugger */
- ret = task_suspend (mach_task_self ());
- if (ret != KERN_SUCCESS)
- internal_error (__FILE__, __LINE__, "failed internal consistency check");
-}
-\f
-/*
- * Intercept system calls to Unix server.
- * After EXEC_COUNTER calls to exec(), return.
- *
- * Pre-assertion: Child is suspended. (Not verified)
- * Post-condition: Child is suspended after EXEC_COUNTER exec() calls.
- */
-
-void
-intercept_exec_calls (int exec_counter)
-{
- int terminal_initted = 0;
-
- struct syscall_msg_t
- {
- mach_msg_header_t header;
- mach_msg_type_t type;
- char room[2000]; /* Enuff space */
- };
-
- struct syscall_msg_t syscall_in, syscall_out;
-
- mach_port_t fake_server;
- mach_port_t original_server_send;
- mach_port_t original_exec_reply;
- mach_port_t exec_reply;
- mach_port_t exec_reply_send;
- mach_msg_type_name_t acquired;
- mach_port_t emulator_server_port_name;
- struct task_basic_info info;
- mach_msg_type_number_t info_count;
-
- kern_return_t ret;
-
- if (exec_counter <= 0)
- return; /* We are already set up in the correct program */
-
- ret = mach_port_allocate (mach_task_self (),
- MACH_PORT_RIGHT_RECEIVE,
- &fake_server);
- CHK ("create inferior_fake_server port failed", ret);
-
- /* Wait for inferior_task to suspend itself */
- while (1)
- {
- info_count = sizeof (info);
- ret = task_info (inferior_task,
- TASK_BASIC_INFO,
- (task_info_t) & info,
- &info_count);
- CHK ("Task info", ret);
-
- if (info.suspend_count)
- break;
-
- /* Note that the definition of the parameter was undefined
- * at the time of this writing, so I just use an `ad hoc' value.
- */
- (void) swtch_pri (42); /* Universal Priority Value */
- }
-
- /* Read the inferior's bootstrap port name */
- if (!mach3_read_inferior (&original_server_port_name,
- &original_server_port_name,
- sizeof (original_server_port_name)))
- error ("Can't read inferior task bootstrap port name");
-
- /* @@ BUG: If more than 1 send right GDB will FAIL!!! */
- /* Should get refs, and set them back when restoring */
- /* Steal the original bsd server send right from inferior */
- ret = mach_port_extract_right (inferior_task,
- original_server_port_name,
- MACH_MSG_TYPE_MOVE_SEND,
- &original_server_send,
- &acquired);
- CHK ("mach_port_extract_right (bsd server send)", ret);
-
- if (acquired != MACH_MSG_TYPE_PORT_SEND)
- error ("Incorrect right extracted, send right to bsd server expected");
-
- ret = mach_port_insert_right (inferior_task,
- original_server_port_name,
- fake_server,
- MACH_MSG_TYPE_MAKE_SEND);
- CHK ("mach_port_insert_right (fake server send)", ret);
-
- xx_debug ("inferior task bsd server ports set up \nfs %x, ospn %x, oss %x\n",
- fake_server,
- original_server_port_name, original_server_send);
-
- /* A receive right to the reply generated by unix server exec() request */
- ret = mach_port_allocate (mach_task_self (),
- MACH_PORT_RIGHT_RECEIVE,
- &exec_reply);
- CHK ("create intercepted_reply_port port failed", ret);
-
- /* Pass this send right to Unix server so it replies to us after exec() */
- ret = mach_port_extract_right (mach_task_self (),
- exec_reply,
- MACH_MSG_TYPE_MAKE_SEND_ONCE,
- &exec_reply_send,
- &acquired);
- CHK ("mach_port_extract_right (exec_reply)", ret);
-
- if (acquired != MACH_MSG_TYPE_PORT_SEND_ONCE)
- error ("Incorrect right extracted, send once expected for exec reply");
-
- ret = mach_port_move_member (mach_task_self (),
- fake_server,
- inferior_wait_port_set);
- CHK ("Moving fake syscall port to inferior_wait_port_set", ret);
-
- xx_debug ("syscall fake server set up, resuming inferior\n");
-
- ret = task_resume (inferior_task);
- CHK ("task_resume (startup)", ret);
-
- /* Read requests from the inferior.
- Pass directly through everything else except exec() calls.
- */
- while (exec_counter > 0)
- {
- ret = mach_msg (&syscall_in.header, /* header */
- MACH_RCV_MSG, /* options */
- 0, /* send size */
- sizeof (struct syscall_msg_t), /* receive size */
- inferior_wait_port_set, /* receive_name */
- MACH_MSG_TIMEOUT_NONE,
- MACH_PORT_NULL);
- CHK ("mach_msg (intercepted sycall)", ret);
-
-#ifdef DUMP_SYSCALL
- print_msg (&syscall_in.header);
-#endif
-
- /* ASSERT : msgh_local_port == fake_server */
-
- if (notify_server (&syscall_in.header, &syscall_out.header))
- error ("received a notify while intercepting syscalls");
-
- if (syscall_in.header.msgh_id == MIG_EXEC_SYSCALL_ID)
- {
- xx_debug ("Received EXEC SYSCALL, counter = %d\n", exec_counter);
- if (exec_counter == 1)
- {
- original_exec_reply = syscall_in.header.msgh_remote_port;
- syscall_in.header.msgh_remote_port = exec_reply_send;
- }
-
- if (!terminal_initted)
- {
- /* Now that the child has exec'd we know it has already set its
- process group. On POSIX systems, tcsetpgrp will fail with
- EPERM if we try it before the child's setpgid. */
-
- /* Set up the "saved terminal modes" of the inferior
- based on what modes we are starting it with. */
- target_terminal_init ();
-
- /* Install inferior's terminal modes. */
- target_terminal_inferior ();
-
- terminal_initted = 1;
- }
-
- exec_counter--;
- }
-
- syscall_in.header.msgh_local_port = syscall_in.header.msgh_remote_port;
- syscall_in.header.msgh_remote_port = original_server_send;
-
- reverse_msg_bits (&syscall_in.header, MACH_MSG_TYPE_COPY_SEND);
-
- ret = mach_msg_send (&syscall_in.header);
- CHK ("Forwarded syscall", ret);
- }
-
- ret = mach_port_move_member (mach_task_self (),
- fake_server,
- MACH_PORT_NULL);
- CHK ("Moving fake syscall out of inferior_wait_port_set", ret);
-
- ret = mach_port_move_member (mach_task_self (),
- exec_reply,
- inferior_wait_port_set);
- CHK ("Moving exec_reply to inferior_wait_port_set", ret);
-
- ret = mach_msg (&syscall_in.header, /* header */
- MACH_RCV_MSG, /* options */
- 0, /* send size */
- sizeof (struct syscall_msg_t), /* receive size */
- inferior_wait_port_set, /* receive_name */
- MACH_MSG_TIMEOUT_NONE,
- MACH_PORT_NULL);
- CHK ("mach_msg (exec reply)", ret);
-
- ret = task_suspend (inferior_task);
- CHK ("Suspending inferior after last exec", ret);
-
- must_suspend_thread = 0;
-
- xx_debug ("Received exec reply from bsd server, suspended inferior task\n");
-
-#ifdef DUMP_SYSCALL
- print_msg (&syscall_in.header);
-#endif
-
- /* Message should appear as if it came from the unix server */
- syscall_in.header.msgh_local_port = MACH_PORT_NULL;
-
- /* and go to the inferior task original reply port */
- syscall_in.header.msgh_remote_port = original_exec_reply;
-
- reverse_msg_bits (&syscall_in.header, MACH_MSG_TYPE_MOVE_SEND_ONCE);
-
- ret = mach_msg_send (&syscall_in.header);
- CHK ("Forwarding exec reply to inferior", ret);
-
- /* Garbage collect */
- ret = mach_port_deallocate (inferior_task,
- original_server_port_name);
- CHK ("deallocating fake server send right", ret);
-
- ret = mach_port_insert_right (inferior_task,
- original_server_port_name,
- original_server_send,
- MACH_MSG_TYPE_MOVE_SEND);
- CHK ("Restoring the original bsd server send right", ret);
-
- ret = mach_port_destroy (mach_task_self (),
- fake_server);
- fake_server = MACH_PORT_DEAD;
- CHK ("mach_port_destroy (fake_server)", ret);
-
- ret = mach_port_destroy (mach_task_self (),
- exec_reply);
- exec_reply = MACH_PORT_DEAD;
- CHK ("mach_port_destroy (exec_reply)", ret);
-
- xx_debug ("Done with exec call interception\n");
-}
-
-void
-consume_send_rights (thread_array_t thread_list, int thread_count)
-{
- int index;
-
- if (!thread_count)
- return;
-
- for (index = 0; index < thread_count; index++)
- {
- /* Since thread kill command kills threads, don't check ret */
- (void) mach_port_deallocate (mach_task_self (),
- thread_list[index]);
- }
-}
-
-/* suspend/abort/resume a thread. */
-setup_thread (mach_port_t thread, int what)
-{
- kern_return_t ret;
-
- if (what)
- {
- ret = thread_suspend (thread);
- CHK ("setup_thread thread_suspend", ret);
-
- ret = thread_abort (thread);
- CHK ("setup_thread thread_abort", ret);
- }
- else
- {
- ret = thread_resume (thread);
- CHK ("setup_thread thread_resume", ret);
- }
-}
-
-int
-map_slot_to_mid (int slot, thread_array_t threads, int thread_count)
-{
- kern_return_t ret;
- int deallocate = 0;
- int index;
- int mid;
-
- if (!threads)
- {
- deallocate++;
- ret = task_threads (inferior_task, &threads, &thread_count);
- CHK ("Can not select a thread from a dead task", ret);
- }
-
- if (slot < 0 || slot >= thread_count)
- {
- if (deallocate)
- {
- consume_send_rights (threads, thread_count);
- (void) vm_deallocate (mach_task_self (), (vm_address_t) threads,
- (thread_count * sizeof (mach_port_t)));
- }
- if (slot < 0)
- error ("invalid slot number");
- else
- return -(slot + 1);
- }
-
- mid = map_port_name_to_mid (threads[slot], MACH_TYPE_THREAD);
-
- if (deallocate)
- {
- consume_send_rights (threads, thread_count);
- (void) vm_deallocate (mach_task_self (), (vm_address_t) threads,
- (thread_count * sizeof (mach_port_t)));
- }
-
- return mid;
-}
-
-static int
-parse_thread_id (char *arg, int thread_count, int slots)
-{
- kern_return_t ret;
- int mid;
- int slot;
- int index;
-
- if (arg == 0)
- return 0;
-
- while (*arg && (*arg == ' ' || *arg == '\t'))
- arg++;
-
- if (!*arg)
- return 0;
-
- /* Currently parse MID and @SLOTNUMBER */
- if (*arg != '@')
- {
- mid = atoi (arg);
- if (mid <= 0)
- error ("valid thread mid expected");
- return mid;
- }
-
- arg++;
- slot = atoi (arg);
-
- if (slot < 0)
- error ("invalid slot number");
-
- /* If you want slot numbers to remain slot numbers, set slots.
-
- * Well, since 0 is reserved, return the ordinal number
- * of the thread rather than the slot number. Awk, this
- * counts as a kludge.
- */
- if (slots)
- return -(slot + 1);
-
- if (thread_count && slot >= thread_count)
- return -(slot + 1);
-
- mid = map_slot_to_mid (slot);
-
- return mid;
-}
-
-/* THREAD_ID 0 is special; it selects the first kernel
- * thread from the list (i.e. SLOTNUMBER 0)
- * This is used when starting the program with 'run' or when attaching.
- *
- * If FLAG is 0 the context is not changed, and the registers, frame, etc
- * will continue to describe the old thread.
- *
- * If FLAG is nonzero, really select the thread.
- * If FLAG is 2, the THREAD_ID is a slotnumber instead of a mid.
- *
- */
-kern_return_t
-select_thread (mach_port_t task, int thread_id, int flag)
-{
- thread_array_t thread_list;
- int thread_count;
- kern_return_t ret;
- int index;
- thread_t new_thread = MACH_PORT_NULL;
-
- if (thread_id < 0)
- error ("Can't select cprocs without kernel thread");
-
- ret = task_threads (task, &thread_list, &thread_count);
- if (ret != KERN_SUCCESS)
- {
- warning ("Can not select a thread from a dead task");
- m3_kill_inferior ();
- return KERN_FAILURE;
- }
-
- if (thread_count == 0)
- {
- /* The task can not do anything anymore, but it still
- * exists as a container for memory and ports.
- */
- registers_changed ();
- warning ("Task %d has no threads",
- map_port_name_to_mid (task, MACH_TYPE_TASK));
- current_thread = MACH_PORT_NULL;
- (void) vm_deallocate (mach_task_self (),
- (vm_address_t) thread_list,
- (thread_count * sizeof (mach_port_t)));
- return KERN_FAILURE;
- }
-
- if (!thread_id || flag == 2)
- {
- /* First thread or a slotnumber */
- if (!thread_id)
- new_thread = thread_list[0];
- else
- {
- if (thread_id < thread_count)
- new_thread = thread_list[thread_id];
- else
- {
- (void) vm_deallocate (mach_task_self (),
- (vm_address_t) thread_list,
- (thread_count * sizeof (mach_port_t)));
- error ("No such thread slot number : %d", thread_id);
- }
- }
- }
- else
- {
- for (index = 0; index < thread_count; index++)
- if (thread_id == map_port_name_to_mid (thread_list[index],
- MACH_TYPE_THREAD))
- {
- new_thread = thread_list[index];
- index = -1;
- break;
- }
-
- if (index != -1)
- error ("No thread with mid %d", thread_id);
- }
-
- /* Notify when the selected thread dies */
- request_notify (new_thread, MACH_NOTIFY_DEAD_NAME, MACH_TYPE_THREAD);
-
- ret = vm_deallocate (mach_task_self (),
- (vm_address_t) thread_list,
- (thread_count * sizeof (mach_port_t)));
- CHK ("vm_deallocate", ret);
-
- if (!flag)
- current_thread = new_thread;
- else
- {
-#if 0
- if (MACH_PORT_VALID (current_thread))
- {
- /* Store the gdb's view of the thread we are deselecting
-
- * @@ I think gdb updates registers immediately when they are
- * changed, so don't do this.
- */
- ret = thread_abort (current_thread);
- CHK ("Could not abort system calls when saving state of old thread",
- ret);
- target_prepare_to_store ();
- target_store_registers (-1);
- }
-#endif
-
- registers_changed ();
-
- current_thread = new_thread;
-
- ret = thread_abort (current_thread);
- CHK ("Could not abort system calls when selecting a thread", ret);
-
- stop_pc = read_pc ();
- flush_cached_frames ();
-
- select_frame (get_current_frame ());
- }
-
- return KERN_SUCCESS;
-}
-
-/*
- * Switch to use thread named NEW_THREAD.
- * Return it's MID
- */
-int
-switch_to_thread (thread_t new_thread)
-{
- thread_t saved_thread = current_thread;
- int mid;
-
- mid = map_port_name_to_mid (new_thread,
- MACH_TYPE_THREAD);
- if (mid == -1)
- warning ("Can't map thread name 0x%x to mid", new_thread);
- else if (select_thread (inferior_task, mid, 1) != KERN_SUCCESS)
- {
- if (current_thread)
- current_thread = saved_thread;
- error ("Could not select thread %d", mid);
- }
-
- return mid;
-}
-
-/* Do this in gdb after doing FORK but before STARTUP_INFERIOR.
- * Note that the registers are not yet valid in the inferior task.
- */
-static int
-m3_trace_him (int pid)
-{
- kern_return_t ret;
-
- push_target (&m3_ops);
-
- inferior_task = task_by_pid (pid);
-
- if (!MACH_PORT_VALID (inferior_task))
- error ("Can not map Unix pid %d to Mach task", pid);
-
- /* Clean up previous notifications and create new ones */
- setup_notify_port (1);
-
- /* When notification appears, the inferior task has died */
- request_notify (inferior_task, MACH_NOTIFY_DEAD_NAME, MACH_TYPE_TASK);
-
- emulator_present = have_emulator_p (inferior_task);
-
- /* By default, select the first thread,
- * If task has no threads, gives a warning
- * Does not fetch registers, since they are not yet valid.
- */
- select_thread (inferior_task, 0, 0);
-
- inferior_exception_port = MACH_PORT_NULL;
-
- setup_exception_port ();
-
- xx_debug ("Now the debugged task is created\n");
-
- /* One trap to exec the shell, one to exec the program being debugged. */
- intercept_exec_calls (2);
-
- return pid;
-}
-
-setup_exception_port (void)
-{
- kern_return_t ret;
-
- ret = mach_port_allocate (mach_task_self (),
- MACH_PORT_RIGHT_RECEIVE,
- &inferior_exception_port);
- CHK ("mach_port_allocate", ret);
-
- /* add send right */
- ret = mach_port_insert_right (mach_task_self (),
- inferior_exception_port,
- inferior_exception_port,
- MACH_MSG_TYPE_MAKE_SEND);
- CHK ("mach_port_insert_right", ret);
-
- ret = mach_port_move_member (mach_task_self (),
- inferior_exception_port,
- inferior_wait_port_set);
- CHK ("mach_port_move_member", ret);
-
- ret = task_get_special_port (inferior_task,
- TASK_EXCEPTION_PORT,
- &inferior_old_exception_port);
- CHK ("task_get_special_port(old exc)", ret);
-
- ret = task_set_special_port (inferior_task,
- TASK_EXCEPTION_PORT,
- inferior_exception_port);
- CHK ("task_set_special_port", ret);
-
- ret = mach_port_deallocate (mach_task_self (),
- inferior_exception_port);
- CHK ("mack_port_deallocate", ret);
-
-#if 0
- /* When notify appears, the inferior_task's exception
- * port has been destroyed.
- *
- * Not used, since the dead_name_notification already
- * appears when task dies.
- *
- */
- request_notify (inferior_exception_port,
- MACH_NOTIFY_NO_SENDERS,
- MACH_TYPE_EXCEPTION_PORT);
-#endif
-}
-
-/* Nonzero if gdb is waiting for a message */
-int mach_really_waiting;
-
-/* Wait for the inferior to stop for some reason.
- - Loop on notifications until inferior_task dies.
- - Loop on exceptions until stopped_in_exception comes true.
- (e.g. we receive a single step trace trap)
- - a message arrives to gdb's message port
-
- There is no other way to exit this loop.
-
- Returns the inferior_ptid for rest of gdb.
- Side effects: Set *OURSTATUS. */
-ptid_t
-mach_really_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
-{
- kern_return_t ret;
- int w;
-
- struct msg
- {
- mach_msg_header_t header;
- mach_msg_type_t foo;
- int data[8000];
- }
- in_msg, out_msg;
-
- /* Either notify (death), exception or message can stop the inferior */
- stopped_in_exception = FALSE;
-
- while (1)
- {
- QUIT;
-
- stop_exception = stop_code = stop_subcode = -1;
- stop_thread = MACH_PORT_NULL;
-
- mach_really_waiting = 1;
- ret = mach_msg (&in_msg.header, /* header */
- MACH_RCV_MSG, /* options */
- 0, /* send size */
- sizeof (struct msg), /* receive size */
- currently_waiting_for, /* receive name */
- MACH_MSG_TIMEOUT_NONE,
- MACH_PORT_NULL);
- mach_really_waiting = 0;
- CHK ("mach_msg (receive)", ret);
-
- /* Check if we received a notify of the childs' death */
- if (notify_server (&in_msg.header, &out_msg.header))
- {
- /* If inferior_task is null then the inferior has
- gone away and we want to return to command level.
- Otherwise it was just an informative message and we
- need to look to see if there are any more. */
- if (inferior_task != MACH_PORT_NULL)
- continue;
- else
- {
- /* Collect Unix exit status for gdb */
-
- wait3 (&w, WNOHANG, 0);
-
- /* This mess is here to check that the rest of
- * gdb knows that the inferior died. It also
- * tries to hack around the fact that Mach 3.0 (mk69)
- * unix server (ux28) does not always know what
- * has happened to it's children when mach-magic
- * is applied on them.
- */
- if ((!WIFEXITED (w) && WIFSTOPPED (w)) ||
- (WIFEXITED (w) && WEXITSTATUS (w) > 0377))
- {
- WSETEXIT (w, 0);
- warning ("Using exit value 0 for terminated task");
- }
- else if (!WIFEXITED (w))
- {
- int sig = WTERMSIG (w);
-
- /* Signals cause problems. Warn the user. */
- if (sig != SIGKILL) /* Bad luck if garbage matches this */
- warning ("The terminating signal stuff may be nonsense");
- else if (sig > NSIG)
- {
- WSETEXIT (w, 0);
- warning ("Using exit value 0 for terminated task");
- }
- }
- store_waitstatus (ourstatus, w);
- return inferior_ptid;
- }
- }
-
- /* Hmm. Check for exception, as it was not a notification.
- exc_server() does an upcall to catch_exception_raise()
- if this rpc is an exception. Further actions are decided
- there.
- */
- if (!exc_server (&in_msg.header, &out_msg.header))
- {
-
- /* Not an exception, check for message.
-
- * Messages don't come from the inferior, or if they
- * do they better be asynchronous or it will hang.
- */
- if (gdb_message_server (&in_msg.header))
- continue;
-
- error ("Unrecognized message received in mach_really_wait");
- }
-
- /* Send the reply of the exception rpc to the suspended task */
- ret = mach_msg_send (&out_msg.header);
- CHK ("mach_msg_send (exc reply)", ret);
-
- if (stopped_in_exception)
- {
- /* Get unix state. May be changed in mach3_exception_actions() */
- wait3 (&w, WNOHANG, 0);
-
- mach3_exception_actions (&w, FALSE, "Task");
-
- store_waitstatus (ourstatus, w);
- return inferior_ptid;
- }
- }
-}
-
-/* Called by macro DO_QUIT() in utils.c(quit).
- * This is called just before calling error() to return to command level
- */
-void
-mach3_quit (void)
-{
- int mid;
- kern_return_t ret;
-
- if (mach_really_waiting)
- {
- ret = task_suspend (inferior_task);
-
- if (ret != KERN_SUCCESS)
- {
- warning ("Could not suspend task for interrupt: %s",
- mach_error_string (ret));
- mach_really_waiting = 0;
- return;
- }
- }
-
- must_suspend_thread = 0;
- mach_really_waiting = 0;
-
- mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
- if (mid == -1)
- {
- warning ("Selecting first existing kernel thread");
- mid = 0;
- }
-
- current_thread = MACH_PORT_NULL; /* Force setup */
- select_thread (inferior_task, mid, 1);
-
- return;
-}
-
-#if 0
-/* bogus bogus bogus. It is NOT OK to quit out of target_wait. */
-
-/* If ^C is typed when we are waiting for a message
- * and your Unix server is able to notice that we
- * should quit now.
- *
- * Called by REQUEST_QUIT() from utils.c(request_quit)
- */
-void
-mach3_request_quit (void)
-{
- if (mach_really_waiting)
- immediate_quit = 1;
-}
-#endif
-
-/*
- * Gdb message server.
- * Currently implemented is the STOP message, that causes
- * gdb to return to the command level like ^C had been typed from terminal.
- */
-int
-gdb_message_server (mach_msg_header_t *InP)
-{
- kern_return_t ret;
- int mid;
-
- if (InP->msgh_local_port == our_message_port)
- {
- /* A message coming to our_message_port. Check validity */
- switch (InP->msgh_id)
- {
-
- case GDB_MESSAGE_ID_STOP:
- ret = task_suspend (inferior_task);
- if (ret != KERN_SUCCESS)
- warning ("Could not suspend task for stop message: %s",
- mach_error_string (ret));
-
- /* QUIT in mach_really_wait() loop. */
- request_quit (0);
- break;
-
- default:
- warning ("Invalid message id %d received, ignored.",
- InP->msgh_id);
- break;
- }
-
- return 1;
- }
-
- /* Message not handled by this server */
- return 0;
-}
-
-/* NOTE: This is not an RPC call. It is a simpleroutine.
-
- * This is not called from this gdb code.
- *
- * It may be called by another debugger to cause this
- * debugger to enter command level:
- *
- * (gdb) set stop_inferior_gdb ()
- * (gdb) continue
- *
- * External program "stop-gdb" implements this also.
- */
-void
-stop_inferior_gdb (void)
-{
- kern_return_t ret;
-
- /* Code generated by mig, with minor cleanups :-)
-
- * simpleroutine stop_inferior_gdb (our_message_port : mach_port_t);
- */
-
- typedef struct
- {
- mach_msg_header_t Head;
- }
- Request;
-
- Request Mess;
-
- register Request *InP = &Mess;
-
- InP->Head.msgh_bits = MACH_MSGH_BITS (MACH_MSG_TYPE_COPY_SEND, 0);
-
- /* msgh_size passed as argument */
- InP->Head.msgh_remote_port = our_message_port;
- InP->Head.msgh_local_port = MACH_PORT_NULL;
- InP->Head.msgh_seqno = 0;
- InP->Head.msgh_id = GDB_MESSAGE_ID_STOP;
-
- ret = mach_msg (&InP->Head,
- MACH_SEND_MSG | MACH_MSG_OPTION_NONE,
- sizeof (Request),
- 0,
- MACH_PORT_NULL,
- MACH_MSG_TIMEOUT_NONE,
- MACH_PORT_NULL);
-}
-
-#ifdef THREAD_ALLOWED_TO_BREAK
-/*
- * Return 1 if the MID specifies the thread that caused the
- * last exception.
- * Since catch_exception_raise() selects the thread causing
- * the last exception to current_thread, we just check that
- * it is selected and the last exception was a breakpoint.
- */
-int
-mach_thread_for_breakpoint (int mid)
-{
- int cmid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
-
- if (mid < 0)
- {
- mid = map_slot_to_mid (-(mid + 1), 0, 0);
- if (mid < 0)
- return 0; /* Don't stop, no such slot */
- }
-
- if (!mid || cmid == -1)
- return 1; /* stop */
-
- return cmid == mid && stop_exception == EXC_BREAKPOINT;
-}
-#endif /* THREAD_ALLOWED_TO_BREAK */
-
-#ifdef THREAD_PARSE_ID
-/*
- * Map a thread id string (MID or a @SLOTNUMBER)
- * to a thread-id.
- *
- * 0 matches all threads.
- * Otherwise the meaning is defined only in this file.
- * (mach_thread_for_breakpoint uses it)
- *
- * @@ This allows non-existent MIDs to be specified.
- * It now also allows non-existent slots to be
- * specified. (Slot numbers stored are negative,
- * and the magnitude is one greater than the actual
- * slot index. (Since 0 is reserved))
- */
-int
-mach_thread_parse_id (char *arg)
-{
- int mid;
- if (arg == 0)
- error ("thread id expected");
- mid = parse_thread_id (arg, 0, 1);
-
- return mid;
-}
-#endif /* THREAD_PARSE_ID */
-
-#ifdef THREAD_OUTPUT_ID
-char *
-mach_thread_output_id (int mid)
-{
- static char foobar[20];
-
- if (mid > 0)
- sprintf (foobar, "mid %d", mid);
- else if (mid < 0)
- sprintf (foobar, "@%d", -(mid + 1));
- else
- sprintf (foobar, "*any thread*");
-
- return foobar;
-}
-#endif /* THREAD_OUTPUT_ID */
-
-/* Called with hook PREPARE_TO_PROCEED() from infrun.c.
-
- * If we have switched threads and stopped at breakpoint return 1 otherwise 0.
- *
- * if SELECT_IT is nonzero, reselect the thread that was active when
- * we stopped at a breakpoint.
- *
- * Note that this implementation is potentially redundant now that
- * default_prepare_to_proceed() has been added.
- *
- * FIXME This may not support switching threads after Ctrl-C
- * correctly. The default implementation does support this.
- */
-
-mach3_prepare_to_proceed (int select_it)
-{
- if (stop_thread &&
- stop_thread != current_thread &&
- stop_exception == EXC_BREAKPOINT)
- {
- int mid;
-
- if (!select_it)
- return 1;
-
- mid = switch_to_thread (stop_thread);
-
- return 1;
- }
-
- return 0;
-}
-
-/* this stuff here is an upcall via libmach/excServer.c
- and mach_really_wait which does the actual upcall.
-
- The code will pass the exception to the inferior if:
-
- - The task that signaled is not the inferior task
- (e.g. when debugging another debugger)
-
- - The user has explicitely requested to pass on the exceptions.
- (e.g to the default unix exception handler, which maps
- exceptions to signals, or the user has her own exception handler)
-
- - If the thread that signaled is being single-stepped and it
- has set it's own exception port and the exception is not
- EXC_BREAKPOINT. (Maybe this is not desirable?)
- */
-
-kern_return_t
-catch_exception_raise (mach_port_t port, thread_t thread, task_t task,
- int exception, int code, int subcode)
-{
- kern_return_t ret;
- boolean_t signal_thread;
- int mid = map_port_name_to_mid (thread, MACH_TYPE_THREAD);
-
- if (!MACH_PORT_VALID (thread))
- {
- /* If the exception was sent and thread dies before we
- receive it, THREAD will be MACH_PORT_DEAD
- */
-
- current_thread = thread = MACH_PORT_NULL;
- error ("Received exception from nonexistent thread");
- }
-
- /* Check if the task died in transit.
- * @@ Isn't the thread also invalid in such case?
- */
- if (!MACH_PORT_VALID (task))
- {
- current_thread = thread = MACH_PORT_NULL;
- error ("Received exception from nonexistent task");
- }
-
- if (exception < 0 || exception > MAX_EXCEPTION)
- internal_error (__FILE__, __LINE__,
- "catch_exception_raise: unknown exception code %d thread %d",
- exception,
- mid);
-
- if (!MACH_PORT_VALID (inferior_task))
- error ("got an exception, but inferior_task is null or dead");
-
- stop_exception = exception;
- stop_code = code;
- stop_subcode = subcode;
- stop_thread = thread;
-
- signal_thread = exception != EXC_BREAKPOINT &&
- port == singlestepped_thread_port &&
- MACH_PORT_VALID (thread_saved_exception_port);
-
- /* If it was not our inferior or if we want to forward
- * the exception to the inferior's handler, do it here
- *
- * Note: If you have forwarded EXC_BREAKPOINT I trust you know why.
- */
- if (task != inferior_task ||
- signal_thread ||
- exception_map[exception].forward)
- {
- mach_port_t eport = inferior_old_exception_port;
-
- if (signal_thread)
- {
- /*
- GDB now forwards the exeption to thread's original handler,
- since the user propably knows what he is doing.
- Give a message, though.
- */
-
- mach3_exception_actions ((WAITTYPE *) NULL, TRUE, "Thread");
- eport = thread_saved_exception_port;
- }
-
- /* Send the exception to the original handler */
- ret = exception_raise (eport,
- thread,
- task,
- exception,
- code,
- subcode);
-
- (void) mach_port_deallocate (mach_task_self (), task);
- (void) mach_port_deallocate (mach_task_self (), thread);
-
- /* If we come here, we don't want to trace any more, since we
- * will never stop for tracing anyway.
- */
- discard_single_step (thread);
-
- /* Do not stop the inferior */
- return ret;
- }
-
- /* Now gdb handles the exception */
- stopped_in_exception = TRUE;
-
- ret = task_suspend (task);
- CHK ("Error suspending inferior after exception", ret);
-
- must_suspend_thread = 0;
-
- if (current_thread != thread)
- {
- if (MACH_PORT_VALID (singlestepped_thread_port))
- /* Cleanup discards single stepping */
- error ("Exception from thread %d while singlestepping thread %d",
- mid,
- map_port_name_to_mid (current_thread, MACH_TYPE_THREAD));
-
- /* Then select the thread that caused the exception */
- if (select_thread (inferior_task, mid, 0) != KERN_SUCCESS)
- error ("Could not select thread %d causing exception", mid);
- else
- warning ("Gdb selected thread %d", mid);
- }
-
- /* If we receive an exception that is not breakpoint
- * exception, we interrupt the single step and return to
- * debugger. Trace condition is cleared.
- */
- if (MACH_PORT_VALID (singlestepped_thread_port))
- {
- if (stop_exception != EXC_BREAKPOINT)
- warning ("Single step interrupted by exception");
- else if (port == singlestepped_thread_port)
- {
- /* Single step exception occurred, remove trace bit
- * and return to gdb.
- */
- if (!MACH_PORT_VALID (current_thread))
- error ("Single stepped thread is not valid");
-
- /* Resume threads, but leave the task suspended */
- resume_all_threads (0);
- }
- else
- warning ("Breakpoint while single stepping?");
-
- discard_single_step (current_thread);
- }
-
- (void) mach_port_deallocate (mach_task_self (), task);
- (void) mach_port_deallocate (mach_task_self (), thread);
-
- return KERN_SUCCESS;
-}
-\f
-int
-port_valid (mach_port_t port, int mask)
-{
- kern_return_t ret;
- mach_port_type_t type;
-
- ret = mach_port_type (mach_task_self (),
- port,
- &type);
- if (ret != KERN_SUCCESS || (type & mask) != mask)
- return 0;
- return 1;
-}
-\f
-/* @@ No vm read cache implemented yet */
-boolean_t vm_read_cache_valid = FALSE;
-
-/*
- * Read inferior task's LEN bytes from ADDR and copy it to MYADDR
- * in gdb's address space.
- *
- * Return 0 on failure; number of bytes read otherwise.
- */
-int
-mach3_read_inferior (CORE_ADDR addr, char *myaddr, int length)
-{
- kern_return_t ret;
- vm_address_t low_address = (vm_address_t) trunc_page (addr);
- vm_size_t aligned_length =
- (vm_size_t) round_page (addr + length) - low_address;
- pointer_t copied_memory;
- int copy_count;
-
- /* Get memory from inferior with page aligned addresses */
- ret = vm_read (inferior_task,
- low_address,
- aligned_length,
- &copied_memory,
- ©_count);
- if (ret != KERN_SUCCESS)
- {
- /* the problem is that the inferior might be killed for whatever reason
- * before we go to mach_really_wait. This is one place that ought to
- * catch many of those errors.
- * @@ A better fix would be to make all external events to GDB
- * to arrive via a SINGLE port set. (Including user input!)
- */
-
- if (!port_valid (inferior_task, MACH_PORT_TYPE_SEND))
- {
- m3_kill_inferior ();
- error ("Inferior killed (task port invalid)");
- }
- else
- {
-#ifdef OSF
- extern int errno;
- /* valprint.c gives nicer format if this does not
- screw it. Eamonn seems to like this, so I enable
- it if OSF is defined...
- */
- warning ("[read inferior %x failed: %s]",
- addr, mach_error_string (ret));
- errno = 0;
-#endif
- return 0;
- }
- }
-
- memcpy (myaddr, (char *) addr - low_address + copied_memory, length);
-
- ret = vm_deallocate (mach_task_self (),
- copied_memory,
- copy_count);
- CHK ("mach3_read_inferior vm_deallocate failed", ret);
-
- return length;
-}
-
-#define CHK_GOTO_OUT(str,ret) \
- do if (ret != KERN_SUCCESS) { errstr = #str; goto out; } while(0)
-
-struct vm_region_list
-{
- struct vm_region_list *next;
- vm_prot_t protection;
- vm_address_t start;
- vm_size_t length;
-};
-
-struct obstack region_obstack;
-
-/*
- * Write inferior task's LEN bytes from ADDR and copy it to MYADDR
- * in gdb's address space.
- */
-int
-mach3_write_inferior (CORE_ADDR addr, char *myaddr, int length)
-{
- kern_return_t ret;
- vm_address_t low_address = (vm_address_t) trunc_page (addr);
- vm_size_t aligned_length =
- (vm_size_t) round_page (addr + length) - low_address;
- pointer_t copied_memory;
- int copy_count;
- int deallocate = 0;
-
- char *errstr = "Bug in mach3_write_inferior";
-
- struct vm_region_list *region_element;
- struct vm_region_list *region_head = (struct vm_region_list *) NULL;
-
- /* Get memory from inferior with page aligned addresses */
- ret = vm_read (inferior_task,
- low_address,
- aligned_length,
- &copied_memory,
- ©_count);
- CHK_GOTO_OUT ("mach3_write_inferior vm_read failed", ret);
-
- deallocate++;
-
- memcpy ((char *) addr - low_address + copied_memory, myaddr, length);
-
- obstack_init (®ion_obstack);
-
- /* Do writes atomically.
- * First check for holes and unwritable memory.
- */
- {
- vm_size_t remaining_length = aligned_length;
- vm_address_t region_address = low_address;
-
- struct vm_region_list *scan;
-
- while (region_address < low_address + aligned_length)
- {
- vm_prot_t protection;
- vm_prot_t max_protection;
- vm_inherit_t inheritance;
- boolean_t shared;
- mach_port_t object_name;
- vm_offset_t offset;
- vm_size_t region_length = remaining_length;
- vm_address_t old_address = region_address;
-
- ret = vm_region (inferior_task,
- ®ion_address,
- ®ion_length,
- &protection,
- &max_protection,
- &inheritance,
- &shared,
- &object_name,
- &offset);
- CHK_GOTO_OUT ("vm_region failed", ret);
-
- /* Check for holes in memory */
- if (old_address != region_address)
- {
- warning ("No memory at 0x%x. Nothing written",
- old_address);
- ret = KERN_SUCCESS;
- length = 0;
- goto out;
- }
-
- if (!(max_protection & VM_PROT_WRITE))
- {
- warning ("Memory at address 0x%x is unwritable. Nothing written",
- old_address);
- ret = KERN_SUCCESS;
- length = 0;
- goto out;
- }
-
- /* Chain the regions for later use */
- region_element =
- (struct vm_region_list *)
- obstack_alloc (®ion_obstack, sizeof (struct vm_region_list));
-
- region_element->protection = protection;
- region_element->start = region_address;
- region_element->length = region_length;
-
- /* Chain the regions along with protections */
- region_element->next = region_head;
- region_head = region_element;
-
- region_address += region_length;
- remaining_length = remaining_length - region_length;
- }
-
- /* If things fail after this, we give up.
- * Somebody is messing up inferior_task's mappings.
- */
-
- /* Enable writes to the chained vm regions */
- for (scan = region_head; scan; scan = scan->next)
- {
- boolean_t protection_changed = FALSE;
-
- if (!(scan->protection & VM_PROT_WRITE))
- {
- ret = vm_protect (inferior_task,
- scan->start,
- scan->length,
- FALSE,
- scan->protection | VM_PROT_WRITE);
- CHK_GOTO_OUT ("vm_protect: enable write failed", ret);
- }
- }
-
- ret = vm_write (inferior_task,
- low_address,
- copied_memory,
- aligned_length);
- CHK_GOTO_OUT ("vm_write failed", ret);
-
- /* Set up the original region protections, if they were changed */
- for (scan = region_head; scan; scan = scan->next)
- {
- boolean_t protection_changed = FALSE;
-
- if (!(scan->protection & VM_PROT_WRITE))
- {
- ret = vm_protect (inferior_task,
- scan->start,
- scan->length,
- FALSE,
- scan->protection);
- CHK_GOTO_OUT ("vm_protect: enable write failed", ret);
- }
- }
- }
-
-out:
- if (deallocate)
- {
- obstack_free (®ion_obstack, 0);
-
- (void) vm_deallocate (mach_task_self (),
- copied_memory,
- copy_count);
- }
-
- if (ret != KERN_SUCCESS)
- {
- warning ("%s %s", errstr, mach_error_string (ret));
- return 0;
- }
-
- return length;
-}
-
-/* Return 0 on failure, number of bytes handled otherwise. TARGET is
- ignored. */
-static int
-m3_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write,
- struct target_ops *target)
-{
- int result;
-
- if (write)
- result = mach3_write_inferior (memaddr, myaddr, len);
- else
- result = mach3_read_inferior (memaddr, myaddr, len);
-
- return result;
-}
-\f
-
-static char *
-translate_state (int state)
-{
- switch (state)
- {
- case TH_STATE_RUNNING:
- return ("R");
- case TH_STATE_STOPPED:
- return ("S");
- case TH_STATE_WAITING:
- return ("W");
- case TH_STATE_UNINTERRUPTIBLE:
- return ("U");
- case TH_STATE_HALTED:
- return ("H");
- default:
- return ("?");
- }
-}
-
-static char *
-translate_cstate (int state)
-{
- switch (state)
- {
- case CPROC_RUNNING:
- return "R";
- case CPROC_SWITCHING:
- return "S";
- case CPROC_BLOCKED:
- return "B";
- case CPROC_CONDWAIT:
- return "C";
- case CPROC_CONDWAIT | CPROC_SWITCHING:
- return "CS";
- default:
- return "?";
- }
-}
-
-/* type == MACH_MSG_TYPE_COPY_SEND || type == MACH_MSG_TYPE_MAKE_SEND */
-
-mach_port_t /* no mach_port_name_t found in include files. */
-map_inferior_port_name (mach_port_t inferior_name, mach_msg_type_name_t type)
-{
- kern_return_t ret;
- mach_msg_type_name_t acquired;
- mach_port_t iport;
-
- ret = mach_port_extract_right (inferior_task,
- inferior_name,
- type,
- &iport,
- &acquired);
- CHK ("mach_port_extract_right (map_inferior_port_name)", ret);
-
- if (acquired != MACH_MSG_TYPE_PORT_SEND)
- error ("Incorrect right extracted, (map_inferior_port_name)");
-
- ret = mach_port_deallocate (mach_task_self (),
- iport);
- CHK ("Deallocating mapped port (map_inferior_port_name)", ret);
-
- return iport;
-}
-
-/*
- * Naming convention:
- * Always return user defined name if found.
- * _K == A kernel thread with no matching CPROC
- * _C == A cproc with no current cthread
- * _t == A cthread with no user defined name
- *
- * The digits that follow the _names are the SLOT number of the
- * kernel thread if there is such a thing, otherwise just a negation
- * of the sequential number of such cprocs.
- */
-
-static char buf[7];
-
-static char *
-get_thread_name (gdb_thread_t one_cproc, int id)
-{
- if (one_cproc)
- if (one_cproc->cthread == NULL)
- {
- /* cproc not mapped to any cthread */
- sprintf (buf, "_C%d", id);
- }
- else if (!one_cproc->cthread->name)
- {
- /* cproc and cthread, but no name */
- sprintf (buf, "_t%d", id);
- }
- else
- return (char *) (one_cproc->cthread->name);
- else
- {
- if (id < 0)
- warning ("Inconsistency in thread name id %d", id);
-
- /* Kernel thread without cproc */
- sprintf (buf, "_K%d", id);
- }
-
- return buf;
-}
-
-int
-fetch_thread_info (mach_port_t task, gdb_thread_t *mthreads_out)
-{
- kern_return_t ret;
- thread_array_t th_table;
- int th_count;
- gdb_thread_t mthreads = NULL;
- int index;
-
- ret = task_threads (task, &th_table, &th_count);
- if (ret != KERN_SUCCESS)
- {
- warning ("Error getting inferior's thread list:%s",
- mach_error_string (ret));
- m3_kill_inferior ();
- return -1;
- }
-
- mthreads = (gdb_thread_t)
- obstack_alloc
- (cproc_obstack,
- th_count * sizeof (struct gdb_thread));
-
- for (index = 0; index < th_count; index++)
- {
- thread_t saved_thread = MACH_PORT_NULL;
- int mid;
-
- if (must_suspend_thread)
- setup_thread (th_table[index], 1);
-
- if (th_table[index] != current_thread)
- {
- saved_thread = current_thread;
-
- mid = switch_to_thread (th_table[index]);
- }
-
- mthreads[index].name = th_table[index];
- mthreads[index].cproc = NULL; /* map_cprocs_to_kernel_threads() */
- mthreads[index].in_emulator = FALSE;
- mthreads[index].slotid = index;
-
- mthreads[index].sp = read_register (SP_REGNUM);
- mthreads[index].fp = read_register (FP_REGNUM);
- mthreads[index].pc = read_pc ();
-
- if (MACH_PORT_VALID (saved_thread))
- mid = switch_to_thread (saved_thread);
-
- if (must_suspend_thread)
- setup_thread (th_table[index], 0);
- }
-
- consume_send_rights (th_table, th_count);
- ret = vm_deallocate (mach_task_self (), (vm_address_t) th_table,
- (th_count * sizeof (mach_port_t)));
- if (ret != KERN_SUCCESS)
- {
- warning ("Error trying to deallocate thread list : %s",
- mach_error_string (ret));
- }
-
- *mthreads_out = mthreads;
-
- return th_count;
-}
-
-
-/*
- * Current emulator always saves the USP on top of
- * emulator stack below struct emul_stack_top stuff.
- */
-CORE_ADDR
-fetch_usp_from_emulator_stack (CORE_ADDR sp)
-{
- CORE_ADDR stack_pointer;
-
- sp = (sp & ~(EMULATOR_STACK_SIZE - 1)) +
- EMULATOR_STACK_SIZE - sizeof (struct emul_stack_top);
-
- if (mach3_read_inferior (sp,
- &stack_pointer,
- sizeof (CORE_ADDR)) != sizeof (CORE_ADDR))
- {
- warning ("Can't read user sp from emulator stack address 0x%x", sp);
- return 0;
- }
-
- return stack_pointer;
-}
-
-#ifdef MK67
-
-/* get_emulation_vector() interface was changed after mk67 */
-#define EMUL_VECTOR_COUNT 400 /* Value does not matter too much */
-
-#endif /* MK67 */
-
-/* Check if the emulator exists at task's address space.
- */
-boolean_t
-have_emulator_p (task_t task)
-{
- kern_return_t ret;
-#ifndef EMUL_VECTOR_COUNT
- vm_offset_t *emulation_vector;
- int n;
-#else
- vm_offset_t emulation_vector[EMUL_VECTOR_COUNT];
- int n = EMUL_VECTOR_COUNT;
-#endif
- int i;
- int vector_start;
-
- ret = task_get_emulation_vector (task,
- &vector_start,
-#ifndef EMUL_VECTOR_COUNT
- &emulation_vector,
-#else
- emulation_vector,
-#endif
- &n);
- CHK ("task_get_emulation_vector", ret);
- xx_debug ("%d vectors from %d at 0x%08x\n",
- n, vector_start, emulation_vector);
-
- for (i = 0; i < n; i++)
- {
- vm_offset_t entry = emulation_vector[i];
-
- if (EMULATOR_BASE <= entry && entry <= EMULATOR_END)
- return TRUE;
- else if (entry)
- {
- static boolean_t informed = FALSE;
- if (!informed)
- {
- warning ("Emulation vector address 0x08%x outside emulator space",
- entry);
- informed = TRUE;
- }
- }
- }
- return FALSE;
-}
-
-/* Map cprocs to kernel threads and vice versa. */
-
-void
-map_cprocs_to_kernel_threads (gdb_thread_t cprocs, gdb_thread_t mthreads,
- int thread_count)
-{
- int index;
- gdb_thread_t scan;
- boolean_t all_mapped = TRUE;
- LONGEST stack_base;
- LONGEST stack_size;
-
- for (scan = cprocs; scan; scan = scan->next)
- {
- /* Default to: no kernel thread for this cproc */
- scan->reverse_map = -1;
-
- /* Check if the cproc is found by its stack */
- for (index = 0; index < thread_count; index++)
- {
- stack_base =
- extract_signed_integer (scan->raw_cproc + CPROC_BASE_OFFSET,
- CPROC_BASE_SIZE);
- stack_size =
- extract_signed_integer (scan->raw_cproc + CPROC_SIZE_OFFSET,
- CPROC_SIZE_SIZE);
- if ((mthreads + index)->sp > stack_base &&
- (mthreads + index)->sp <= stack_base + stack_size)
- {
- (mthreads + index)->cproc = scan;
- scan->reverse_map = index;
- break;
- }
- }
- all_mapped &= (scan->reverse_map != -1);
- }
-
- /* Check for threads that are currently in the emulator.
- * If so, they have a different stack, and the still unmapped
- * cprocs may well get mapped to these threads.
- *
- * If:
- * - cproc stack does not match any kernel thread stack pointer
- * - there is at least one extra kernel thread
- * that has no cproc mapped above.
- * - some kernel thread stack pointer points to emulator space
- * then we find the user stack pointer saved in the emulator
- * stack, and try to map that to the cprocs.
- *
- * Also set in_emulator for kernel threads.
- */
-
- if (emulator_present)
- {
- for (index = 0; index < thread_count; index++)
- {
- CORE_ADDR emul_sp;
- CORE_ADDR usp;
-
- gdb_thread_t mthread = (mthreads + index);
- emul_sp = mthread->sp;
-
- if (mthread->cproc == NULL &&
- EMULATOR_BASE <= emul_sp && emul_sp <= EMULATOR_END)
- {
- mthread->in_emulator = emulator_present;
-
- if (!all_mapped && cprocs)
- {
- usp = fetch_usp_from_emulator_stack (emul_sp);
-
- /* @@ Could be more accurate */
- if (!usp)
- error ("Zero stack pointer read from emulator?");
-
- /* Try to match this stack pointer to the cprocs that
- * don't yet have a kernel thread.
- */
- for (scan = cprocs; scan; scan = scan->next)
- {
-
- /* Check is this unmapped CPROC stack contains
- * the user stack pointer saved in the
- * emulator.
- */
- if (scan->reverse_map == -1)
- {
- stack_base =
- extract_signed_integer
- (scan->raw_cproc + CPROC_BASE_OFFSET,
- CPROC_BASE_SIZE);
- stack_size =
- extract_signed_integer
- (scan->raw_cproc + CPROC_SIZE_OFFSET,
- CPROC_SIZE_SIZE);
- if (usp > stack_base &&
- usp <= stack_base + stack_size)
- {
- mthread->cproc = scan;
- scan->reverse_map = index;
- break;
- }
- }
- }
- }
- }
- }
- }
-}
-\f
-/*
- * Format of the thread_list command
- *
- * slot mid sel name emul ks susp cstate wired address
- */
-#define TL_FORMAT "%-2.2s %5d%c %-10.10s %1.1s%s%-5.5s %-2.2s %-5.5s "
-
-#define TL_HEADER "\n@ MID Name KState CState Where\n"
-
-void
-print_tl_address (struct ui_file *stream, CORE_ADDR pc)
-{
- if (!lookup_minimal_symbol_by_pc (pc))
- fprintf_filtered (stream, local_hex_format (), pc);
- else
- {
- extern int addressprint;
- extern int asm_demangle;
-
- int store = addressprint;
- addressprint = 0;
- print_address_symbolic (pc, stream, asm_demangle, "");
- addressprint = store;
- }
-}
-\f
-/* For thread names, but also for gdb_message_port external name */
-#define MAX_NAME_LEN 50
-
-/* Returns the address of variable NAME or 0 if not found */
-CORE_ADDR
-lookup_address_of_variable (char *name)
-{
- struct symbol *sym;
- CORE_ADDR symaddr = 0;
- struct minimal_symbol *msymbol;
-
- sym = lookup_symbol (name,
- (struct block *) NULL,
- VAR_NAMESPACE,
- (int *) NULL,
- (struct symtab **) NULL);
-
- if (sym)
- symaddr = SYMBOL_VALUE (sym);
-
- if (!symaddr)
- {
- msymbol = lookup_minimal_symbol (name, NULL, NULL);
-
- if (msymbol && msymbol->type == mst_data)
- symaddr = SYMBOL_VALUE_ADDRESS (msymbol);
- }
-
- return symaddr;
-}
-
-static gdb_thread_t
-get_cprocs (void)
-{
- gdb_thread_t cproc_head;
- gdb_thread_t cproc_copy;
- CORE_ADDR their_cprocs;
- char *buf;
- char *name;
- cthread_t cthread;
- CORE_ADDR symaddr;
-
- buf = alloca (TARGET_PTR_BIT / HOST_CHAR_BIT);
- symaddr = lookup_address_of_variable ("cproc_list");
-
- if (!symaddr)
- {
- /* cproc_list is not in a file compiled with debugging
- symbols, but don't give up yet */
-
- symaddr = lookup_address_of_variable ("cprocs");
-
- if (symaddr)
- {
- static int informed = 0;
- if (!informed)
- {
- informed++;
- warning ("Your program is loaded with an old threads library.");
- warning ("GDB does not know the old form of threads");
- warning ("so things may not work.");
- }
- }
- }
-
- /* Stripped or no -lthreads loaded or "cproc_list" is in wrong segment. */
- if (!symaddr)
- return NULL;
-
- /* Get the address of the first cproc in the task */
- if (!mach3_read_inferior (symaddr,
- buf,
- TARGET_PTR_BIT / HOST_CHAR_BIT))
- error ("Can't read cproc master list at address (0x%x).", symaddr);
- their_cprocs = extract_address (buf, TARGET_PTR_BIT / HOST_CHAR_BIT);
-
- /* Scan the CPROCs in the task.
- CPROCs are chained with LIST field, not NEXT field, which
- chains mutexes, condition variables and queues */
-
- cproc_head = NULL;
-
- while (their_cprocs != (CORE_ADDR) 0)
- {
- CORE_ADDR cproc_copy_incarnation;
- cproc_copy = (gdb_thread_t) obstack_alloc (cproc_obstack,
- sizeof (struct gdb_thread));
-
- if (!mach3_read_inferior (their_cprocs,
- &cproc_copy->raw_cproc[0],
- CPROC_SIZE))
- error ("Can't read next cproc at 0x%x.", their_cprocs);
-
- their_cprocs =
- extract_address (cproc_copy->raw_cproc + CPROC_LIST_OFFSET,
- CPROC_LIST_SIZE);
- cproc_copy_incarnation =
- extract_address (cproc_copy->raw_cproc + CPROC_INCARNATION_OFFSET,
- CPROC_INCARNATION_SIZE);
-
- if (cproc_copy_incarnation == (CORE_ADDR) 0)
- cproc_copy->cthread = NULL;
- else
- {
- /* This CPROC has an attached CTHREAD. Get its name */
- cthread = (cthread_t) obstack_alloc (cproc_obstack,
- sizeof (struct cthread));
-
- if (!mach3_read_inferior (cproc_copy_incarnation,
- cthread,
- sizeof (struct cthread)))
- error ("Can't read next thread at 0x%x.",
- cproc_copy_incarnation);
-
- cproc_copy->cthread = cthread;
-
- if (cthread->name)
- {
- name = (char *) obstack_alloc (cproc_obstack, MAX_NAME_LEN);
-
- if (!mach3_read_inferior (cthread->name, name, MAX_NAME_LEN))
- error ("Can't read next thread's name at 0x%x.", cthread->name);
-
- cthread->name = name;
- }
- }
-
- /* insert in front */
- cproc_copy->next = cproc_head;
- cproc_head = cproc_copy;
- }
- return cproc_head;
-}
-
-#ifndef FETCH_CPROC_STATE
-/*
- * Check if your machine does not grok the way this routine
- * fetches the FP,PC and SP of a cproc that is not
- * currently attached to any kernel thread (e.g. its cproc.context
- * field points to the place in stack where the context
- * is saved).
- *
- * If it doesn't, define your own routine.
- */
-#define FETCH_CPROC_STATE(mth) mach3_cproc_state (mth)
-
-int
-mach3_cproc_state (gdb_thread_t mthread)
-{
- int context;
-
- if (!mthread || !mthread->cproc)
- return -1;
-
- context = extract_signed_integer
- (mthread->cproc->raw_cproc + CPROC_CONTEXT_OFFSET,
- CPROC_CONTEXT_SIZE);
- if (context == 0)
- return -1;
-
- mthread->sp = context + MACHINE_CPROC_SP_OFFSET;
-
- if (mach3_read_inferior (context + MACHINE_CPROC_PC_OFFSET,
- &mthread->pc,
- sizeof (CORE_ADDR)) != sizeof (CORE_ADDR))
- {
- warning ("Can't read cproc pc from inferior");
- return -1;
- }
-
- if (mach3_read_inferior (context + MACHINE_CPROC_FP_OFFSET,
- &mthread->fp,
- sizeof (CORE_ADDR)) != sizeof (CORE_ADDR))
- {
- warning ("Can't read cproc fp from inferior");
- return -1;
- }
-
- return 0;
-}
-#endif /* FETCH_CPROC_STATE */
-\f
-
-void
-thread_list_command (void)
-{
- thread_basic_info_data_t ths;
- int thread_count;
- gdb_thread_t cprocs;
- gdb_thread_t scan;
- int index;
- char *name;
- char selected;
- char *wired;
- int infoCnt;
- kern_return_t ret;
- mach_port_t mid_or_port;
- gdb_thread_t their_threads;
- gdb_thread_t kthread;
-
- int neworder = 1;
-
- char *fmt = "There are %d kernel threads in task %d.\n";
-
- int tmid = map_port_name_to_mid (inferior_task, MACH_TYPE_TASK);
-
- MACH_ERROR_NO_INFERIOR;
-
- thread_count = fetch_thread_info (inferior_task,
- &their_threads);
- if (thread_count == -1)
- return;
-
- if (thread_count == 1)
- fmt = "There is %d kernel thread in task %d.\n";
-
- printf_filtered (fmt, thread_count, tmid);
-
- puts_filtered (TL_HEADER);
-
- cprocs = get_cprocs ();
-
- map_cprocs_to_kernel_threads (cprocs, their_threads, thread_count);
-
- for (scan = cprocs; scan; scan = scan->next)
- {
- int mid;
- char buf[10];
- char slot[3];
- int cproc_state =
- extract_signed_integer
- (scan->raw_cproc + CPROC_STATE_OFFSET, CPROC_STATE_SIZE);
-
- selected = ' ';
-
- /* a wired cproc? */
- wired = (extract_address (scan->raw_cproc + CPROC_WIRED_OFFSET,
- CPROC_WIRED_SIZE)
- ? "wired" : "");
-
- if (scan->reverse_map != -1)
- kthread = (their_threads + scan->reverse_map);
- else
- kthread = NULL;
-
- if (kthread)
- {
- /* These cprocs have a kernel thread */
-
- mid = map_port_name_to_mid (kthread->name, MACH_TYPE_THREAD);
-
- infoCnt = THREAD_BASIC_INFO_COUNT;
-
- ret = thread_info (kthread->name,
- THREAD_BASIC_INFO,
- (thread_info_t) & ths,
- &infoCnt);
-
- if (ret != KERN_SUCCESS)
- {
- warning ("Unable to get basic info on thread %d : %s",
- mid,
- mach_error_string (ret));
- continue;
- }
-
- /* Who is the first to have more than 100 threads */
- sprintf (slot, "%d", kthread->slotid % 100);
-
- if (kthread->name == current_thread)
- selected = '*';
-
- if (ths.suspend_count)
- sprintf (buf, "%d", ths.suspend_count);
- else
- buf[0] = '\000';
-
-#if 0
- if (ths.flags & TH_FLAGS_SWAPPED)
- strcat (buf, "S");
-#endif
-
- if (ths.flags & TH_FLAGS_IDLE)
- strcat (buf, "I");
-
- printf_filtered (TL_FORMAT,
- slot,
- mid,
- selected,
- get_thread_name (scan, kthread->slotid),
- kthread->in_emulator ? "E" : "",
- translate_state (ths.run_state),
- buf,
- translate_cstate (cproc_state),
- wired);
- print_tl_address (gdb_stdout, kthread->pc);
- }
- else
- {
- /* These cprocs don't have a kernel thread.
- * find out the calling frame with
- * FETCH_CPROC_STATE.
- */
-
- struct gdb_thread state;
-
-#if 0
- /* jtv -> emcmanus: why do you want this here? */
- if (scan->incarnation == NULL)
- continue; /* EMcM */
-#endif
-
- printf_filtered (TL_FORMAT,
- "-",
- -neworder, /* Pseudo MID */
- selected,
- get_thread_name (scan, -neworder),
- "",
- "-", /* kernel state */
- "",
- translate_cstate (cproc_state),
- "");
- state.cproc = scan;
-
- if (FETCH_CPROC_STATE (&state) == -1)
- puts_filtered ("???");
- else
- print_tl_address (gdb_stdout, state.pc);
-
- neworder++;
- }
- puts_filtered ("\n");
- }
-
- /* Scan for kernel threads without cprocs */
- for (index = 0; index < thread_count; index++)
- {
- if (!their_threads[index].cproc)
- {
- int mid;
-
- char buf[10];
- char slot[3];
-
- mach_port_t name = their_threads[index].name;
-
- mid = map_port_name_to_mid (name, MACH_TYPE_THREAD);
-
- infoCnt = THREAD_BASIC_INFO_COUNT;
-
- ret = thread_info (name,
- THREAD_BASIC_INFO,
- (thread_info_t) & ths,
- &infoCnt);
-
- if (ret != KERN_SUCCESS)
- {
- warning ("Unable to get basic info on thread %d : %s",
- mid,
- mach_error_string (ret));
- continue;
- }
-
- sprintf (slot, "%d", index % 100);
-
- if (name == current_thread)
- selected = '*';
- else
- selected = ' ';
-
- if (ths.suspend_count)
- sprintf (buf, "%d", ths.suspend_count);
- else
- buf[0] = '\000';
-
-#if 0
- if (ths.flags & TH_FLAGS_SWAPPED)
- strcat (buf, "S");
-#endif
-
- if (ths.flags & TH_FLAGS_IDLE)
- strcat (buf, "I");
-
- printf_filtered (TL_FORMAT,
- slot,
- mid,
- selected,
- get_thread_name (NULL, index),
- their_threads[index].in_emulator ? "E" : "",
- translate_state (ths.run_state),
- buf,
- "", /* No cproc state */
- ""); /* Can't be wired */
- print_tl_address (gdb_stdout, their_threads[index].pc);
- puts_filtered ("\n");
- }
- }
-
- obstack_free (cproc_obstack, 0);
- obstack_init (cproc_obstack);
-}
-\f
-void
-thread_select_command (char *args, int from_tty)
-{
- int mid;
- thread_array_t thread_list;
- int thread_count;
- kern_return_t ret;
- int is_slot = 0;
-
- MACH_ERROR_NO_INFERIOR;
-
- if (!args)
- error_no_arg ("MID or @SLOTNUMBER to specify a thread to select");
-
- while (*args == ' ' || *args == '\t')
- args++;
-
- if (*args == '@')
- {
- is_slot++;
- args++;
- }
-
- mid = atoi (args);
-
- if (mid == 0)
- if (!is_slot || *args != '0') /* Rudimentary checks */
- error ("You must select threads by MID or @SLOTNUMBER");
-
- if (select_thread (inferior_task, mid, is_slot ? 2 : 1) != KERN_SUCCESS)
- return;
-
- if (from_tty)
- printf_filtered ("Thread %d selected\n",
- is_slot ? map_port_name_to_mid (current_thread,
- MACH_TYPE_THREAD) : mid);
-}
-\f
-thread_trace (mach_port_t thread, boolean_t set)
-{
- int flavor = TRACE_FLAVOR;
- unsigned int stateCnt = TRACE_FLAVOR_SIZE;
- kern_return_t ret;
- thread_state_data_t state;
-
- if (!MACH_PORT_VALID (thread))
- {
- warning ("thread_trace: invalid thread");
- return;
- }
-
- if (must_suspend_thread)
- setup_thread (thread, 1);
-
- ret = thread_get_state (thread, flavor, state, &stateCnt);
- CHK ("thread_trace: error reading thread state", ret);
-
- if (set)
- {
- TRACE_SET (thread, state);
- }
- else
- {
- if (!TRACE_CLEAR (thread, state))
- {
- if (must_suspend_thread)
- setup_thread (thread, 0);
- return;
- }
- }
-
- ret = thread_set_state (thread, flavor, state, stateCnt);
- CHK ("thread_trace: error writing thread state", ret);
- if (must_suspend_thread)
- setup_thread (thread, 0);
-}
-
-#ifdef FLUSH_INFERIOR_CACHE
-
-/* When over-writing code on some machines the I-Cache must be flushed
- explicitly, because it is not kept coherent by the lazy hardware.
- This definitely includes breakpoints, for instance, or else we
- end up looping in mysterious Bpt traps */
-
-flush_inferior_icache (CORE_ADDR pc, int amount)
-{
- vm_machine_attribute_val_t flush = MATTR_VAL_ICACHE_FLUSH;
- kern_return_t ret;
-
- ret = vm_machine_attribute (inferior_task,
- pc,
- amount,
- MATTR_CACHE,
- &flush);
- if (ret != KERN_SUCCESS)
- warning ("Error flushing inferior's cache : %s",
- mach_error_string (ret));
-}
-#endif /* FLUSH_INFERIOR_CACHE */
-\f
-
-static
-suspend_all_threads (int from_tty)
-{
- kern_return_t ret;
- thread_array_t thread_list;
- int thread_count, index;
- int infoCnt;
- thread_basic_info_data_t th_info;
-
-
- ret = task_threads (inferior_task, &thread_list, &thread_count);
- if (ret != KERN_SUCCESS)
- {
- warning ("Could not suspend inferior threads.");
- m3_kill_inferior ();
- throw_exception (RETURN_ERROR);
- }
-
- for (index = 0; index < thread_count; index++)
- {
- int mid;
-
- mid = map_port_name_to_mid (thread_list[index],
- MACH_TYPE_THREAD);
-
- ret = thread_suspend (thread_list[index]);
-
- if (ret != KERN_SUCCESS)
- warning ("Error trying to suspend thread %d : %s",
- mid, mach_error_string (ret));
-
- if (from_tty)
- {
- infoCnt = THREAD_BASIC_INFO_COUNT;
- ret = thread_info (thread_list[index],
- THREAD_BASIC_INFO,
- (thread_info_t) & th_info,
- &infoCnt);
- CHK ("suspend can't get thread info", ret);
-
- warning ("Thread %d suspend count is %d",
- mid, th_info.suspend_count);
- }
- }
-
- consume_send_rights (thread_list, thread_count);
- ret = vm_deallocate (mach_task_self (),
- (vm_address_t) thread_list,
- (thread_count * sizeof (int)));
- CHK ("Error trying to deallocate thread list", ret);
-}
-
-void
-thread_suspend_command (char *args, int from_tty)
-{
- kern_return_t ret;
- int mid;
- mach_port_t saved_thread;
- int infoCnt;
- thread_basic_info_data_t th_info;
-
- MACH_ERROR_NO_INFERIOR;
-
- if (!strcasecmp (args, "all"))
- {
- suspend_all_threads (from_tty);
- return;
- }
-
- saved_thread = current_thread;
-
- mid = parse_thread_id (args, 0, 0);
-
- if (mid < 0)
- error ("You can suspend only existing kernel threads with MID or @SLOTNUMBER");
-
- if (mid == 0)
- mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
- else if (select_thread (inferior_task, mid, 0) != KERN_SUCCESS)
- {
- if (current_thread)
- current_thread = saved_thread;
- error ("Could not select thread %d", mid);
- }
-
- ret = thread_suspend (current_thread);
- if (ret != KERN_SUCCESS)
- warning ("thread_suspend failed : %s",
- mach_error_string (ret));
-
- infoCnt = THREAD_BASIC_INFO_COUNT;
- ret = thread_info (current_thread,
- THREAD_BASIC_INFO,
- (thread_info_t) & th_info,
- &infoCnt);
- CHK ("suspend can't get thread info", ret);
-
- warning ("Thread %d suspend count is %d", mid, th_info.suspend_count);
-
- current_thread = saved_thread;
-}
-
-resume_all_threads (int from_tty)
-{
- kern_return_t ret;
- thread_array_t thread_list;
- int thread_count, index;
- int mid;
- int infoCnt;
- thread_basic_info_data_t th_info;
-
- ret = task_threads (inferior_task, &thread_list, &thread_count);
- if (ret != KERN_SUCCESS)
- {
- m3_kill_inferior ();
- error ("task_threads", mach_error_string (ret));
- }
-
- for (index = 0; index < thread_count; index++)
- {
- infoCnt = THREAD_BASIC_INFO_COUNT;
- ret = thread_info (thread_list[index],
- THREAD_BASIC_INFO,
- (thread_info_t) & th_info,
- &infoCnt);
- CHK ("resume_all can't get thread info", ret);
-
- mid = map_port_name_to_mid (thread_list[index],
- MACH_TYPE_THREAD);
-
- if (!th_info.suspend_count)
- {
- if (mid != -1 && from_tty)
- warning ("Thread %d is not suspended", mid);
- continue;
- }
-
- ret = thread_resume (thread_list[index]);
-
- if (ret != KERN_SUCCESS)
- warning ("Error trying to resume thread %d : %s",
- mid, mach_error_string (ret));
- else if (mid != -1 && from_tty)
- warning ("Thread %d suspend count is %d",
- mid, --th_info.suspend_count);
- }
-
- consume_send_rights (thread_list, thread_count);
- ret = vm_deallocate (mach_task_self (),
- (vm_address_t) thread_list,
- (thread_count * sizeof (int)));
- CHK ("Error trying to deallocate thread list", ret);
-}
-
-void
-thread_resume_command (char *args, int from_tty)
-{
- int mid;
- mach_port_t saved_thread;
- kern_return_t ret;
- thread_basic_info_data_t th_info;
- int infoCnt = THREAD_BASIC_INFO_COUNT;
-
- MACH_ERROR_NO_INFERIOR;
-
- if (!strcasecmp (args, "all"))
- {
- resume_all_threads (from_tty);
- return;
- }
-
- saved_thread = current_thread;
-
- mid = parse_thread_id (args, 0, 0);
-
- if (mid < 0)
- error ("You can resume only existing kernel threads with MID or @SLOTNUMBER");
-
- if (mid == 0)
- mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
- else if (select_thread (inferior_task, mid, 0) != KERN_SUCCESS)
- {
- if (current_thread)
- current_thread = saved_thread;
- throw_exception (RETURN_ERROR);
- }
-
- ret = thread_info (current_thread,
- THREAD_BASIC_INFO,
- (thread_info_t) & th_info,
- &infoCnt);
- CHK ("resume can't get thread info", ret);
-
- if (!th_info.suspend_count)
- {
- warning ("Thread %d is not suspended", mid);
- goto out;
- }
-
- ret = thread_resume (current_thread);
- if (ret != KERN_SUCCESS)
- warning ("thread_resume failed : %s",
- mach_error_string (ret));
- else
- {
- th_info.suspend_count--;
- warning ("Thread %d suspend count is %d", mid, th_info.suspend_count);
- }
-
-out:
- current_thread = saved_thread;
-}
-
-void
-thread_kill_command (char *args, int from_tty)
-{
- int mid;
- kern_return_t ret;
- int thread_count;
- thread_array_t thread_table;
- int index;
- mach_port_t thread_to_kill = MACH_PORT_NULL;
-
-
- MACH_ERROR_NO_INFERIOR;
-
- if (!args)
- error_no_arg ("thread mid to kill from the inferior task");
-
- mid = parse_thread_id (args, 0, 0);
-
- if (mid < 0)
- error ("You can kill only existing kernel threads with MID or @SLOTNUMBER");
-
- if (mid)
- {
- ret = machid_mach_port (mid_server, mid_auth, mid, &thread_to_kill);
- CHK ("thread_kill_command: machid_mach_port map failed", ret);
- }
- else
- mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
-
- /* Don't allow gdb to kill *any* thread in the system. Use mkill program for that */
- ret = task_threads (inferior_task, &thread_table, &thread_count);
- CHK ("Error getting inferior's thread list", ret);
-
- if (thread_to_kill == current_thread)
- {
- ret = thread_terminate (thread_to_kill);
- CHK ("Thread could not be terminated", ret);
-
- if (select_thread (inferior_task, 0, 1) != KERN_SUCCESS)
- warning ("Last thread was killed, use \"kill\" command to kill task");
- }
- else
- for (index = 0; index < thread_count; index++)
- if (thread_table[index] == thread_to_kill)
- {
- ret = thread_terminate (thread_to_kill);
- CHK ("Thread could not be terminated", ret);
- }
-
- if (thread_count > 1)
- consume_send_rights (thread_table, thread_count);
-
- ret = vm_deallocate (mach_task_self (), (vm_address_t) thread_table,
- (thread_count * sizeof (mach_port_t)));
- CHK ("Error trying to deallocate thread list", ret);
-
- warning ("Thread %d killed", mid);
-}
-\f
-
-/* Task specific commands; add more if you like */
-
-void
-task_resume_command (char *args, int from_tty)
-{
- kern_return_t ret;
- task_basic_info_data_t ta_info;
- int infoCnt = TASK_BASIC_INFO_COUNT;
- int mid = map_port_name_to_mid (inferior_task, MACH_TYPE_TASK);
-
- MACH_ERROR_NO_INFERIOR;
-
- /* Would be trivial to change, but is it desirable? */
- if (args)
- error ("Currently gdb can resume only it's inferior task");
-
- ret = task_info (inferior_task,
- TASK_BASIC_INFO,
- (task_info_t) & ta_info,
- &infoCnt);
- CHK ("task_resume_command: task_info failed", ret);
-
- if (ta_info.suspend_count == 0)
- error ("Inferior task %d is not suspended", mid);
- else if (ta_info.suspend_count == 1 &&
- from_tty &&
- !query ("Suspend count is now 1. Do you know what you are doing? "))
- error ("Task not resumed");
-
- ret = task_resume (inferior_task);
- CHK ("task_resume_command: task_resume", ret);
-
- if (ta_info.suspend_count == 1)
- {
- warning ("Inferior task %d is no longer suspended", mid);
- must_suspend_thread = 1;
- /* @@ This is not complete: Registers change all the time when not
- suspended! */
- registers_changed ();
- }
- else
- warning ("Inferior task %d suspend count is now %d",
- mid, ta_info.suspend_count - 1);
-}
-
-
-void
-task_suspend_command (char *args, int from_tty)
-{
- kern_return_t ret;
- task_basic_info_data_t ta_info;
- int infoCnt = TASK_BASIC_INFO_COUNT;
- int mid = map_port_name_to_mid (inferior_task, MACH_TYPE_TASK);
-
- MACH_ERROR_NO_INFERIOR;
-
- /* Would be trivial to change, but is it desirable? */
- if (args)
- error ("Currently gdb can suspend only it's inferior task");
-
- ret = task_suspend (inferior_task);
- CHK ("task_suspend_command: task_suspend", ret);
-
- must_suspend_thread = 0;
-
- ret = task_info (inferior_task,
- TASK_BASIC_INFO,
- (task_info_t) & ta_info,
- &infoCnt);
- CHK ("task_suspend_command: task_info failed", ret);
-
- warning ("Inferior task %d suspend count is now %d",
- mid, ta_info.suspend_count);
-}
-
-static char *
-get_size (int bytes)
-{
- static char size[30];
- int zz = bytes / 1024;
-
- if (zz / 1024)
- sprintf (size, "%-2.1f M", ((float) bytes) / (1024.0 * 1024.0));
- else
- sprintf (size, "%d K", zz);
-
- return size;
-}
-
-/* Does this require the target task to be suspended?? I don't think so. */
-void
-task_info_command (char *args, int from_tty)
-{
- int mid = -5;
- mach_port_t task;
- kern_return_t ret;
- task_basic_info_data_t ta_info;
- int infoCnt = TASK_BASIC_INFO_COUNT;
- int page_size = round_page (1);
- int thread_count = 0;
-
- if (MACH_PORT_VALID (inferior_task))
- mid = map_port_name_to_mid (inferior_task,
- MACH_TYPE_TASK);
-
- task = inferior_task;
-
- if (args)
- {
- int tmid = atoi (args);
-
- if (tmid <= 0)
- error ("Invalid mid %d for task info", tmid);
-
- if (tmid != mid)
- {
- mid = tmid;
- ret = machid_mach_port (mid_server, mid_auth, tmid, &task);
- CHK ("task_info_command: machid_mach_port map failed", ret);
- }
- }
-
- if (mid < 0)
- error ("You have to give the task MID as an argument");
-
- ret = task_info (task,
- TASK_BASIC_INFO,
- (task_info_t) & ta_info,
- &infoCnt);
- CHK ("task_info_command: task_info failed", ret);
-
- printf_filtered ("\nTask info for task %d:\n\n", mid);
- printf_filtered (" Suspend count : %d\n", ta_info.suspend_count);
- printf_filtered (" Base priority : %d\n", ta_info.base_priority);
- printf_filtered (" Virtual size : %s\n", get_size (ta_info.virtual_size));
- printf_filtered (" Resident size : %s\n", get_size (ta_info.resident_size));
-
- {
- thread_array_t thread_list;
-
- ret = task_threads (task, &thread_list, &thread_count);
- CHK ("task_info_command: task_threads", ret);
-
- printf_filtered (" Thread count : %d\n", thread_count);
-
- consume_send_rights (thread_list, thread_count);
- ret = vm_deallocate (mach_task_self (),
- (vm_address_t) thread_list,
- (thread_count * sizeof (int)));
- CHK ("Error trying to deallocate thread list", ret);
- }
- if (have_emulator_p (task))
- printf_filtered (" Emulator at : 0x%x..0x%x\n",
- EMULATOR_BASE, EMULATOR_END);
- else
- printf_filtered (" No emulator.\n");
-
- if (thread_count && task == inferior_task)
- printf_filtered ("\nUse the \"thread list\" command to see the threads\n");
-}
-\f
-/* You may either FORWARD the exception to the inferior, or KEEP
- * it and return to GDB command level.
- *
- * exception mid [ forward | keep ]
- */
-
-static void
-exception_command (char *args, int from_tty)
-{
- char *scan = args;
- int exception;
- int len;
-
- if (!args)
- error_no_arg ("exception number action");
-
- while (*scan == ' ' || *scan == '\t')
- scan++;
-
- if ('0' <= *scan && *scan <= '9')
- while ('0' <= *scan && *scan <= '9')
- scan++;
- else
- error ("exception number action");
-
- exception = atoi (args);
- if (exception <= 0 || exception > MAX_EXCEPTION)
- error ("Allowed exception numbers are in range 1..%d",
- MAX_EXCEPTION);
-
- if (*scan != ' ' && *scan != '\t')
- error ("exception number must be followed by a space");
- else
- while (*scan == ' ' || *scan == '\t')
- scan++;
-
- args = scan;
- len = 0;
- while (*scan)
- {
- len++;
- scan++;
- }
-
- if (!len)
- error ("exception number action");
-
- if (!strncasecmp (args, "forward", len))
- exception_map[exception].forward = TRUE;
- else if (!strncasecmp (args, "keep", len))
- exception_map[exception].forward = FALSE;
- else
- error ("exception action is either \"keep\" or \"forward\"");
-}
-
-static void
-print_exception_info (int exception)
-{
- boolean_t forward = exception_map[exception].forward;
-
- printf_filtered ("%s\t(%d): ", exception_map[exception].name,
- exception);
- if (!forward)
- if (exception_map[exception].sigmap != SIG_UNKNOWN)
- printf_filtered ("keep and handle as signal %d\n",
- exception_map[exception].sigmap);
- else
- printf_filtered ("keep and handle as unknown signal %d\n",
- exception_map[exception].sigmap);
- else
- printf_filtered ("forward exception to inferior\n");
-}
-
-void
-exception_info (char *args, int from_tty)
-{
- int exception;
-
- if (!args)
- for (exception = 1; exception <= MAX_EXCEPTION; exception++)
- print_exception_info (exception);
- else
- {
- exception = atoi (args);
-
- if (exception <= 0 || exception > MAX_EXCEPTION)
- error ("Invalid exception number, values from 1 to %d allowed",
- MAX_EXCEPTION);
- print_exception_info (exception);
- }
-}
-\f
-/* Check for actions for mach exceptions.
- */
-mach3_exception_actions (WAITTYPE *w, boolean_t force_print_only, char *who)
-{
- boolean_t force_print = FALSE;
-
-
- if (force_print_only ||
- exception_map[stop_exception].sigmap == SIG_UNKNOWN)
- force_print = TRUE;
- else
- WSETSTOP (*w, exception_map[stop_exception].sigmap);
-
- if (exception_map[stop_exception].print || force_print)
- {
- target_terminal_ours ();
-
- printf_filtered ("\n%s received %s exception : ",
- who,
- exception_map[stop_exception].name);
-
- wrap_here (" ");
-
- switch (stop_exception)
- {
- case EXC_BAD_ACCESS:
- printf_filtered ("referencing address 0x%x : %s\n",
- stop_subcode,
- mach_error_string (stop_code));
- break;
- case EXC_BAD_INSTRUCTION:
- printf_filtered
- ("illegal or undefined instruction. code %d subcode %d\n",
- stop_code, stop_subcode);
- break;
- case EXC_ARITHMETIC:
- printf_filtered ("code %d\n", stop_code);
- break;
- case EXC_EMULATION:
- printf_filtered ("code %d subcode %d\n", stop_code, stop_subcode);
- break;
- case EXC_SOFTWARE:
- printf_filtered ("%s specific, code 0x%x\n",
- stop_code < 0xffff ? "hardware" : "os emulation",
- stop_code);
- break;
- case EXC_BREAKPOINT:
- printf_filtered ("type %d (machine dependent)\n",
- stop_code);
- break;
- default:
- internal_error (__FILE__, __LINE__,
- "Unknown exception");
- }
- }
-}
-\f
-setup_notify_port (int create_new)
-{
- kern_return_t ret;
-
- if (MACH_PORT_VALID (our_notify_port))
- {
- ret = mach_port_destroy (mach_task_self (), our_notify_port);
- CHK ("Could not destroy our_notify_port", ret);
- }
-
- our_notify_port = MACH_PORT_NULL;
- notify_chain = (port_chain_t) NULL;
- port_chain_destroy (port_chain_obstack);
-
- if (create_new)
- {
- ret = mach_port_allocate (mach_task_self (),
- MACH_PORT_RIGHT_RECEIVE,
- &our_notify_port);
- if (ret != KERN_SUCCESS)
- internal_error (__FILE__, __LINE__,
- "Creating notify port %s", mach_error_string (ret));
-
- ret = mach_port_move_member (mach_task_self (),
- our_notify_port,
- inferior_wait_port_set);
- if (ret != KERN_SUCCESS)
- internal_error (__FILE__, __LINE__,
- "initial move member %s", mach_error_string (ret));
- }
-}
-
-/*
- * Register our message port to the net name server
- *
- * Currently used only by the external stop-gdb program
- * since ^C does not work if you would like to enter
- * gdb command level while debugging your program.
- *
- * NOTE: If the message port is sometimes used for other
- * purposes also, the NAME must not be a guessable one.
- * Then, there should be a way to change it.
- */
-
-char registered_name[MAX_NAME_LEN];
-
-void
-message_port_info (char *args, int from_tty)
-{
- if (registered_name[0])
- printf_filtered ("gdb's message port name: '%s'\n",
- registered_name);
- else
- printf_filtered ("gdb's message port is not currently registered\n");
-}
-
-void
-gdb_register_port (char *name, mach_port_t port)
-{
- kern_return_t ret;
- static int already_signed = 0;
- int len;
-
- if (!MACH_PORT_VALID (port) || !name || !*name)
- {
- warning ("Invalid registration request");
- return;
- }
-
- if (!already_signed)
- {
- ret = mach_port_insert_right (mach_task_self (),
- our_message_port,
- our_message_port,
- MACH_MSG_TYPE_MAKE_SEND);
- CHK ("Failed to create a signature to our_message_port", ret);
- already_signed = 1;
- }
- else if (already_signed > 1)
- {
- ret = netname_check_out (name_server_port,
- registered_name,
- our_message_port);
- CHK ("Failed to check out gdb's message port", ret);
- registered_name[0] = '\000';
- already_signed = 1;
- }
-
- ret = netname_check_in (name_server_port, /* Name server port */
- name, /* Name of service */
- our_message_port, /* Signature */
- port); /* Creates a new send right */
- CHK ("Failed to check in the port", ret);
-
- len = 0;
- while (len < MAX_NAME_LEN && *(name + len))
- {
- registered_name[len] = *(name + len);
- len++;
- }
- registered_name[len] = '\000';
- already_signed = 2;
-}
-
-struct cmd_list_element *cmd_thread_list;
-struct cmd_list_element *cmd_task_list;
-
-/*ARGSUSED */
-static void
-thread_command (char *arg, int from_tty)
-{
- printf_unfiltered ("\"thread\" must be followed by the name of a thread command.\n");
- help_list (cmd_thread_list, "thread ", -1, gdb_stdout);
-}
-
-/*ARGSUSED */
-static void
-task_command (char *arg, int from_tty)
-{
- printf_unfiltered ("\"task\" must be followed by the name of a task command.\n");
- help_list (cmd_task_list, "task ", -1, gdb_stdout);
-}
-
-add_mach_specific_commands (void)
-{
- /* Thread handling commands */
-
- /* FIXME: Move our thread support into the generic thread.c stuff so we
- can share that code. */
- add_prefix_cmd ("mthread", class_stack, thread_command,
- "Generic command for handling Mach threads in the debugged task.",
- &cmd_thread_list, "thread ", 0, &cmdlist);
-
- add_com_alias ("th", "mthread", class_stack, 1);
-
- add_cmd ("select", class_stack, thread_select_command,
- "Select and print MID of the selected thread",
- &cmd_thread_list);
- add_cmd ("list", class_stack, thread_list_command,
- "List info of task's threads. Selected thread is marked with '*'",
- &cmd_thread_list);
- add_cmd ("suspend", class_run, thread_suspend_command,
- "Suspend one or all of the threads in the selected task.",
- &cmd_thread_list);
- add_cmd ("resume", class_run, thread_resume_command,
- "Resume one or all of the threads in the selected task.",
- &cmd_thread_list);
- add_cmd ("kill", class_run, thread_kill_command,
- "Kill the specified thread MID from inferior task.",
- &cmd_thread_list);
-#if 0
- /* The rest of this support (condition_thread) was not merged. It probably
- should not be merged in this form, but instead added to the generic GDB
- thread support. */
- add_cmd ("break", class_breakpoint, condition_thread,
- "Breakpoint N will only be effective for thread MID or @SLOT\n\
- If MID/@SLOT is omitted allow all threads to break at breakpoint",
- &cmd_thread_list);
-#endif
- /* Thread command shorthands (for backward compatibility) */
- add_alias_cmd ("ts", "mthread select", 0, 0, &cmdlist);
- add_alias_cmd ("tl", "mthread list", 0, 0, &cmdlist);
-
- /* task handling commands */
-
- add_prefix_cmd ("task", class_stack, task_command,
- "Generic command for handling debugged task.",
- &cmd_task_list, "task ", 0, &cmdlist);
-
- add_com_alias ("ta", "task", class_stack, 1);
-
- add_cmd ("suspend", class_run, task_suspend_command,
- "Suspend the inferior task.",
- &cmd_task_list);
- add_cmd ("resume", class_run, task_resume_command,
- "Resume the inferior task.",
- &cmd_task_list);
- add_cmd ("info", no_class, task_info_command,
- "Print information about the specified task.",
- &cmd_task_list);
-
- /* Print my message port name */
-
- add_info ("message-port", message_port_info,
- "Returns the name of gdb's message port in the netnameserver");
-
- /* Exception commands */
-
- add_info ("exceptions", exception_info,
- "What debugger does when program gets various exceptions.\n\
-Specify an exception number as argument to print info on that\n\
-exception only.");
-
- add_com ("exception", class_run, exception_command,
- "Specify how to handle an exception.\n\
-Args are exception number followed by \"forward\" or \"keep\".\n\
-`Forward' means forward the exception to the program's normal exception\n\
-handler.\n\
-`Keep' means reenter debugger if this exception happens, and GDB maps\n\
-the exception to some signal (see info exception)\n\
-Normally \"keep\" is used to return to GDB on exception.");
-}
-
-kern_return_t
-do_mach_notify_dead_name (mach_port_t notify, mach_port_t name)
-{
- kern_return_t kr = KERN_SUCCESS;
-
- /* Find the thing that notified */
- port_chain_t element = port_chain_member (notify_chain, name);
-
- /* Take name of from unreceived dead name notification list */
- notify_chain = port_chain_delete (notify_chain, name);
-
- if (!element)
- error ("Received a dead name notify from unchained port (0x%x)", name);
-
- switch (element->type)
- {
-
- case MACH_TYPE_THREAD:
- target_terminal_ours_for_output ();
- if (name == current_thread)
- {
- printf_filtered ("\nCurrent thread %d died", element->mid);
- current_thread = MACH_PORT_NULL;
- }
- else
- printf_filtered ("\nThread %d died", element->mid);
-
- break;
-
- case MACH_TYPE_TASK:
- target_terminal_ours_for_output ();
- if (name != inferior_task)
- printf_filtered ("Task %d died, but it was not the selected task",
- element->mid);
- else
- {
- printf_filtered ("Current task %d died", element->mid);
-
- mach_port_destroy (mach_task_self (), name);
- inferior_task = MACH_PORT_NULL;
-
- if (notify_chain)
- warning ("There were still unreceived dead_name_notifications???");
-
- /* Destroy the old notifications */
- setup_notify_port (0);
-
- }
- break;
-
- default:
- error ("Unregistered dead_name 0x%x notification received. Type is %d, mid is 0x%x",
- name, element->type, element->mid);
- break;
- }
-
- return KERN_SUCCESS;
-}
-
-kern_return_t
-do_mach_notify_msg_accepted (mach_port_t notify, mach_port_t name)
-{
- warning ("do_mach_notify_msg_accepted : notify %x, name %x",
- notify, name);
- return KERN_SUCCESS;
-}
-
-kern_return_t
-do_mach_notify_no_senders (mach_port_t notify, mach_port_mscount_t mscount)
-{
- warning ("do_mach_notify_no_senders : notify %x, mscount %x",
- notify, mscount);
- return KERN_SUCCESS;
-}
-
-kern_return_t
-do_mach_notify_port_deleted (mach_port_t notify, mach_port_t name)
-{
- warning ("do_mach_notify_port_deleted : notify %x, name %x",
- notify, name);
- return KERN_SUCCESS;
-}
-
-kern_return_t
-do_mach_notify_port_destroyed (mach_port_t notify, mach_port_t rights)
-{
- warning ("do_mach_notify_port_destroyed : notify %x, rights %x",
- notify, rights);
- return KERN_SUCCESS;
-}
-
-kern_return_t
-do_mach_notify_send_once (mach_port_t notify)
-{
-#ifdef DUMP_SYSCALL
- /* MANY of these are generated. */
- warning ("do_mach_notify_send_once : notify %x",
- notify);
-#endif
- return KERN_SUCCESS;
-}
-
-/* Kills the inferior. It's gone when you call this */
-static void
-kill_inferior_fast (void)
-{
- WAITTYPE w;
-
- if (PIDGET (inferior_ptid) == 0 || PIDGET (inferior_ptid) == 1)
- return;
-
- /* kill() it, since the Unix server does not otherwise notice when
- * killed with task_terminate().
- */
- if (PIDGET (inferior_ptid) > 0)
- kill (PIDGET (inferior_ptid), SIGKILL);
-
- /* It's propably terminate already */
- (void) task_terminate (inferior_task);
-
- inferior_task = MACH_PORT_NULL;
- current_thread = MACH_PORT_NULL;
-
- wait3 (&w, WNOHANG, 0);
-
- setup_notify_port (0);
-}
-
-static void
-m3_kill_inferior (void)
-{
- kill_inferior_fast ();
- target_mourn_inferior ();
-}
-
-/* Clean up after the inferior dies. */
-
-static void
-m3_mourn_inferior (void)
-{
- unpush_target (&m3_ops);
- generic_mourn_inferior ();
-}
-\f
-
-/* Fork an inferior process, and start debugging it. */
-
-static void
-m3_create_inferior (char *exec_file, char *allargs, char **env)
-{
- fork_inferior (exec_file, allargs, env, m3_trace_me, m3_trace_him, NULL, NULL);
- /* We are at the first instruction we care about. */
- /* Pedal to the metal... */
- proceed ((CORE_ADDR) -1, 0, 0);
-}
-
-/* Mark our target-struct as eligible for stray "run" and "attach"
- commands. */
-static int
-m3_can_run (void)
-{
- return 1;
-}
-\f
-/* Mach 3.0 does not need ptrace for anything
- * Make sure nobody uses it on mach.
- */
-ptrace (int a, int b, int c, int d)
-{
- error ("Lose, Lose! Somebody called ptrace\n");
-}
-
-/* Resume execution of the inferior process.
- If STEP is nonzero, single-step it.
- If SIGNAL is nonzero, give it that signal. */
-
-void
-m3_resume (ptid_t ptid, int step, enum target_signal signal)
-{
- kern_return_t ret;
-
- if (step)
- {
- thread_basic_info_data_t th_info;
- unsigned int infoCnt = THREAD_BASIC_INFO_COUNT;
-
- /* There is no point in single stepping when current_thread
- * is dead.
- */
- if (!MACH_PORT_VALID (current_thread))
- error ("No thread selected; can not single step");
-
- /* If current_thread is suspended, tracing it would never return.
- */
- ret = thread_info (current_thread,
- THREAD_BASIC_INFO,
- (thread_info_t) & th_info,
- &infoCnt);
- CHK ("child_resume: can't get thread info", ret);
-
- if (th_info.suspend_count)
- error ("Can't trace a suspended thread. Use \"thread resume\" command to resume it");
- }
-
- vm_read_cache_valid = FALSE;
-
- if (signal && PIDGET (inferior_ptid) > 0) /* Do not signal, if attached by MID */
- kill (PIDGET (inferior_ptid), target_signal_to_host (signal));
-
- if (step)
- {
- suspend_all_threads (0);
-
- setup_single_step (current_thread, TRUE);
-
- ret = thread_resume (current_thread);
- CHK ("thread_resume", ret);
- }
-
- ret = task_resume (inferior_task);
- if (ret == KERN_FAILURE)
- warning ("Task was not suspended");
- else
- CHK ("Resuming task", ret);
-
- /* HACK HACK This is needed by the multiserver system HACK HACK */
- while ((ret = task_resume (inferior_task)) == KERN_SUCCESS)
- /* make sure it really runs */ ;
- /* HACK HACK This is needed by the multiserver system HACK HACK */
-}
-\f
-#ifdef ATTACH_DETACH
-
-/* Start debugging the process with the given task */
-void
-task_attach (task_t tid)
-{
- kern_return_t ret;
- inferior_task = tid;
-
- ret = task_suspend (inferior_task);
- CHK ("task_attach: task_suspend", ret);
-
- must_suspend_thread = 0;
-
- setup_notify_port (1);
-
- request_notify (inferior_task, MACH_NOTIFY_DEAD_NAME, MACH_TYPE_TASK);
-
- setup_exception_port ();
-
- emulator_present = have_emulator_p (inferior_task);
-
- attach_flag = 1;
-}
-
-/* Well, we can call error also here and leave the
- * target stack inconsistent. Sigh.
- * Fix this sometime (the only way to fail here is that
- * the task has no threads at all, which is rare, but
- * possible; or if the target task has died, which is also
- * possible, but unlikely, since it has been suspended.
- * (Someone must have killed it))
- */
-void
-attach_to_thread (void)
-{
- if (select_thread (inferior_task, 0, 1) != KERN_SUCCESS)
- error ("Could not select any threads to attach to");
-}
-
-mid_attach (int mid)
-{
- kern_return_t ret;
-
- ret = machid_mach_port (mid_server, mid_auth, mid, &inferior_task);
- CHK ("mid_attach: machid_mach_port", ret);
-
- task_attach (inferior_task);
-
- return mid;
-}
-
-/*
- * Start debugging the process whose unix process-id is PID.
- * A negative "pid" value is legal and signifies a mach_id not a unix pid.
- *
- * Prevent (possible unwanted) dangerous operations by enabled users
- * like "atta 0" or "atta foo" (equal to the previous :-) and
- * "atta pidself". Anyway, the latter is allowed by specifying a MID.
- */
-static int
-m3_do_attach (int pid)
-{
- kern_return_t ret;
-
- if (pid == 0)
- error ("MID=0, Debugging the master unix server does not compute");
-
- /* Foo. This assumes gdb has a unix pid */
- if (pid == getpid ())
- error ("I will debug myself only by mid. (Gdb would suspend itself!)");
-
- if (pid < 0)
- {
- mid_attach (-(pid));
-
- /* inferior_ptid will be NEGATIVE! */
- inferior_ptid = pid_to_ptid (pid);
-
- return PIDGET (inferior_ptid);
- }
-
- inferior_task = task_by_pid (pid);
- if (!MACH_PORT_VALID (inferior_task))
- error ("Cannot map Unix pid %d to Mach task port", pid);
-
- task_attach (inferior_task);
-
- inferior_ptid = pid_to_ptid (pid);
-
- return PIDGET (inferior_ptid);
-}
-
-/* Attach to process PID, then initialize for debugging it
- and wait for the trace-trap that results from attaching. */
-
-static void
-m3_attach (char *args, int from_tty)
-{
- char *exec_file;
- int pid;
-
- if (!args)
- error_no_arg ("process-id to attach");
-
- pid = atoi (args);
-
- if (pid == getpid ()) /* Trying to masturbate? */
- error ("I refuse to debug myself!");
-
- if (from_tty)
- {
- exec_file = (char *) get_exec_file (0);
-
- if (exec_file)
- printf_unfiltered ("Attaching to program `%s', %s\n", exec_file,
- target_pid_to_str (pid_to_ptid (pid)));
- else
- printf_unfiltered ("Attaching to %s\n",
- target_pid_to_str (pid_to_ptid (pid)));
-
- gdb_flush (gdb_stdout);
- }
-
- m3_do_attach (pid_to_ptid (pid));
- inferior_ptid = pid_to_ptid (pid);
- push_target (&m3_ops);
-}
-\f
-void
-deallocate_inferior_ports (void)
-{
- kern_return_t ret;
- thread_array_t thread_list;
- int thread_count, index;
-
- if (!MACH_PORT_VALID (inferior_task))
- return;
-
- ret = task_threads (inferior_task, &thread_list, &thread_count);
- if (ret != KERN_SUCCESS)
- {
- warning ("deallocate_inferior_ports: task_threads",
- mach_error_string (ret));
- return;
- }
-
- /* Get rid of send rights to task threads */
- for (index = 0; index < thread_count; index++)
- {
- int rights;
- ret = mach_port_get_refs (mach_task_self (),
- thread_list[index],
- MACH_PORT_RIGHT_SEND,
- &rights);
- CHK ("deallocate_inferior_ports: get refs", ret);
-
- if (rights > 0)
- {
- ret = mach_port_mod_refs (mach_task_self (),
- thread_list[index],
- MACH_PORT_RIGHT_SEND,
- -rights);
- CHK ("deallocate_inferior_ports: mod refs", ret);
- }
- }
-
- ret = mach_port_mod_refs (mach_task_self (),
- inferior_exception_port,
- MACH_PORT_RIGHT_RECEIVE,
- -1);
- CHK ("deallocate_inferior_ports: cannot get rid of exception port", ret);
-
- ret = mach_port_deallocate (mach_task_self (),
- inferior_task);
- CHK ("deallocate_task_port: deallocating inferior_task", ret);
-
- current_thread = MACH_PORT_NULL;
- inferior_task = MACH_PORT_NULL;
-}
-
-/* Stop debugging the process whose number is PID
- and continue it with signal number SIGNAL.
- SIGNAL = 0 means just continue it. */
-
-static void
-m3_do_detach (int signal)
-{
- kern_return_t ret;
-
- MACH_ERROR_NO_INFERIOR;
-
- if (current_thread != MACH_PORT_NULL)
- {
- /* Store the gdb's view of the thread we are deselecting
- * before we detach.
- * @@ I am really not sure if this is ever needeed.
- */
- target_prepare_to_store ();
- target_store_registers (-1);
- }
-
- ret = task_set_special_port (inferior_task,
- TASK_EXCEPTION_PORT,
- inferior_old_exception_port);
- CHK ("task_set_special_port", ret);
-
- /* Discard all requested notifications */
- setup_notify_port (0);
-
- if (remove_breakpoints ())
- warning ("Could not remove breakpoints when detaching");
-
- if (signal && PIDGET (inferior_ptid) > 0)
- kill (PIDGET (inferior_ptid), signal);
-
- /* the task might be dead by now */
- (void) task_resume (inferior_task);
-
- deallocate_inferior_ports ();
-
- attach_flag = 0;
-}
-
-/* Take a program previously attached to and detaches it.
- The program resumes execution and will no longer stop
- on signals, etc. We'd better not have left any breakpoints
- in the program or it'll die when it hits one. For this
- to work, it may be necessary for the process to have been
- previously attached. It *might* work if the program was
- started via fork. */
-
-static void
-m3_detach (char *args, int from_tty)
-{
- int siggnal = 0;
-
- if (from_tty)
- {
- char *exec_file = get_exec_file (0);
- if (exec_file == 0)
- exec_file = "";
- printf_unfiltered ("Detaching from program: %s %s\n",
- exec_file, target_pid_to_str (inferior_ptid));
- gdb_flush (gdb_stdout);
- }
- if (args)
- siggnal = atoi (args);
-
- m3_do_detach (siggnal);
- inferior_ptid = null_ptid;
- unpush_target (&m3_ops); /* Pop out of handling an inferior */
-}
-#endif /* ATTACH_DETACH */
-
-/* Get ready to modify the registers array. On machines which store
- individual registers, this doesn't need to do anything. On machines
- which store all the registers in one fell swoop, this makes sure
- that registers contains all the registers from the program being
- debugged. */
-
-static void
-m3_prepare_to_store (void)
-{
-#ifdef CHILD_PREPARE_TO_STORE
- CHILD_PREPARE_TO_STORE ();
-#endif
-}
-
-/* Print status information about what we're accessing. */
-
-static void
-m3_files_info (struct target_ops *ignore)
-{
- /* FIXME: should print MID and all that crap. */
- printf_unfiltered ("\tUsing the running image of %s %s.\n",
- attach_flag ? "attached" : "child", target_pid_to_str (inferior_ptid));
-}
-
-static void
-m3_open (char *arg, int from_tty)
-{
- error ("Use the \"run\" command to start a Unix child process.");
-}
-
-#ifdef DUMP_SYSCALL
-#define STR(x) #x
-
-char *bsd1_names[] =
-{
- "execve",
- "fork",
- "take_signal",
- "sigreturn",
- "getrusage",
- "chdir",
- "chroot",
- "open",
- "creat",
- "mknod",
- "link",
- "symlink",
- "unlink",
- "access",
- "stat",
- "readlink",
- "chmod",
- "chown",
- "utimes",
- "truncate",
- "rename",
- "mkdir",
- "rmdir",
- "xutimes",
- "mount",
- "umount",
- "acct",
- "setquota",
- "write_short",
- "write_long",
- "send_short",
- "send_long",
- "sendto_short",
- "sendto_long",
- "select",
- "task_by_pid",
- "recvfrom_short",
- "recvfrom_long",
- "setgroups",
- "setrlimit",
- "sigvec",
- "sigstack",
- "settimeofday",
- "adjtime",
- "setitimer",
- "sethostname",
- "bind",
- "accept",
- "connect",
- "setsockopt",
- "getsockopt",
- "getsockname",
- "getpeername",
- "init_process",
- "table_set",
- "table_get",
- "pioctl",
- "emulator_error",
- "readwrite",
- "share_wakeup",
- 0,
- "maprw_request_it",
- "maprw_release_it",
- "maprw_remap",
- "pid_by_task",
-};
-
-int bsd1_nnames = sizeof (bsd1_names) / sizeof (bsd1_names[0]);
-
-char *
-name_str (int name, char *buf)
-{
- switch (name)
- {
- case MACH_MSG_TYPE_BOOLEAN:
- return "boolean";
- case MACH_MSG_TYPE_INTEGER_16:
- return "short";
- case MACH_MSG_TYPE_INTEGER_32:
- return "long";
- case MACH_MSG_TYPE_CHAR:
- return "char";
- case MACH_MSG_TYPE_BYTE:
- return "byte";
- case MACH_MSG_TYPE_REAL:
- return "real";
- case MACH_MSG_TYPE_STRING:
- return "string";
- default:
- sprintf (buf, "%d", name);
- return buf;
- }
-}
-
-char *
-id_str (int id, char *buf)
-{
- char *p;
- if (id >= 101000 && id < 101000 + bsd1_nnames)
- {
- if (p = bsd1_names[id - 101000])
- return p;
- }
- if (id == 102000)
- return "psignal_retry";
- if (id == 100000)
- return "syscall";
- sprintf (buf, "%d", id);
- return buf;
-}
-
-print_msg (mach_msg_header_t *mp)
-{
- char *fmt_x = "%20s : 0x%08x\n";
- char *fmt_d = "%20s : %10d\n";
- char *fmt_s = "%20s : %s\n";
- char buf[100];
-
- puts_filtered ("\n");
-#define pr(fmt,h,x) printf_filtered(fmt,STR(x),(h).x)
- pr (fmt_x, (*mp), msgh_bits);
- pr (fmt_d, (*mp), msgh_size);
- pr (fmt_x, (*mp), msgh_remote_port);
- pr (fmt_x, (*mp), msgh_local_port);
- pr (fmt_d, (*mp), msgh_kind);
- printf_filtered (fmt_s, STR (msgh_id), id_str (mp->msgh_id, buf));
-
- if (debug_level > 1)
- {
- char *p, *ep, *dp;
- int plen;
- p = (char *) mp;
- ep = p + mp->msgh_size;
- p += sizeof (*mp);
- for (; p < ep; p += plen)
- {
- mach_msg_type_t *tp;
- mach_msg_type_long_t *tlp;
- int name, size, number;
- tp = (mach_msg_type_t *) p;
- if (tp->msgt_longform)
- {
- tlp = (mach_msg_type_long_t *) tp;
- name = tlp->msgtl_name;
- size = tlp->msgtl_size;
- number = tlp->msgtl_number;
- plen = sizeof (*tlp);
- }
- else
- {
- name = tp->msgt_name;
- size = tp->msgt_size;
- number = tp->msgt_number;
- plen = sizeof (*tp);
- }
- printf_filtered ("name=%-16s size=%2d number=%7d inline=%d long=%d deal=%d\n",
- name_str (name, buf), size, number, tp->msgt_inline,
- tp->msgt_longform, tp->msgt_deallocate);
- dp = p + plen;
- if (tp->msgt_inline)
- {
- int l;
- l = size * number / 8;
- l = (l + sizeof (long) - 1) & ~((sizeof (long)) - 1);
- plen += l;
- print_data (dp, size, number);
- }
- else
- {
- plen += sizeof (int *);
- }
- printf_filtered ("plen=%d\n", plen);
- }
- }
-}
-
-print_data (char *p, int size, int number)
-{
- int *ip;
- short *sp;
- int i;
-
- switch (size)
- {
- case 8:
- for (i = 0; i < number; i++)
- {
- printf_filtered (" %02x", p[i]);
- }
- break;
- case 16:
- sp = (short *) p;
- for (i = 0; i < number; i++)
- {
- printf_filtered (" %04x", sp[i]);
- }
- break;
- case 32:
- ip = (int *) p;
- for (i = 0; i < number; i++)
- {
- printf_filtered (" %08x", ip[i]);
- }
- break;
- }
- puts_filtered ("\n");
-}
-#endif /* DUMP_SYSCALL */
-
-static void
-m3_stop (void)
-{
- error ("to_stop target function not implemented");
-}
-
-static char *
-m3_pid_to_exec_file (int pid)
-{
- error ("to_pid_to_exec_file target function not implemented");
- return NULL; /* To keep all compilers happy. */
-}
-
-static void
-init_m3_ops (void)
-{
- m3_ops.to_shortname = "mach";
- m3_ops.to_longname = "Mach child process";
- m3_ops.to_doc = "Mach child process (started by the \"run\" command).";
- m3_ops.to_open = m3_open;
- m3_ops.to_attach = m3_attach;
- m3_ops.to_detach = m3_detach;
- m3_ops.to_resume = m3_resume;
- m3_ops.to_wait = mach_really_wait;
- m3_ops.to_fetch_registers = fetch_inferior_registers;
- m3_ops.to_store_registers = store_inferior_registers;
- m3_ops.to_prepare_to_store = m3_prepare_to_store;
- m3_ops.to_xfer_memory = m3_xfer_memory;
- m3_ops.to_files_info = m3_files_info;
- m3_ops.to_insert_breakpoint = memory_insert_breakpoint;
- m3_ops.to_remove_breakpoint = memory_remove_breakpoint;
- m3_ops.to_terminal_init = terminal_init_inferior;
- m3_ops.to_terminal_inferior = terminal_inferior;
- m3_ops.to_terminal_ours_for_output = terminal_ours_for_output;
- m3_ops.to_terminal_save_ours = terminal_save_ours;
- m3_ops.to_terminal_ours = terminal_ours;
- m3_ops.to_terminal_info = child_terminal_info;
- m3_ops.to_kill = m3_kill_inferior;
- m3_ops.to_create_inferior = m3_create_inferior;
- m3_ops.to_mourn_inferior = m3_mourn_inferior;
- m3_ops.to_can_run = m3_can_run;
- m3_ops.to_stop = m3_stop;
- m3_ops.to_pid_to_exec_file = m3_pid_to_exec_file;
- m3_ops.to_stratum = process_stratum;
- m3_ops.to_has_all_memory = 1;
- m3_ops.to_has_memory = 1;
- m3_ops.to_has_stack = 1;
- m3_ops.to_has_registers = 1;
- m3_ops.to_has_execution = 1;
- m3_ops.to_magic = OPS_MAGIC;
-}
-
-void
-_initialize_m3_nat (void)
-{
- kern_return_t ret;
-
- init_m3_ops ();
- add_target (&m3_ops);
-
- ret = mach_port_allocate (mach_task_self (),
- MACH_PORT_RIGHT_PORT_SET,
- &inferior_wait_port_set);
- if (ret != KERN_SUCCESS)
- internal_error (__FILE__, __LINE__,
- "initial port set %s", mach_error_string (ret));
-
- /* mach_really_wait now waits for this */
- currently_waiting_for = inferior_wait_port_set;
-
- ret = netname_look_up (name_server_port, hostname, "MachID", &mid_server);
- if (ret != KERN_SUCCESS)
- {
- mid_server = MACH_PORT_NULL;
-
- warning ("initialize machid: netname_lookup_up(MachID) : %s",
- mach_error_string (ret));
- warning ("Some (most?) features disabled...");
- }
-
- mid_auth = mach_privileged_host_port ();
- if (mid_auth == MACH_PORT_NULL)
- mid_auth = mach_task_self ();
-
- obstack_init (port_chain_obstack);
-
- ret = mach_port_allocate (mach_task_self (),
- MACH_PORT_RIGHT_RECEIVE,
- &thread_exception_port);
- CHK ("Creating thread_exception_port for single stepping", ret);
-
- ret = mach_port_insert_right (mach_task_self (),
- thread_exception_port,
- thread_exception_port,
- MACH_MSG_TYPE_MAKE_SEND);
- CHK ("Inserting send right to thread_exception_port", ret);
-
- /* Allocate message port */
- ret = mach_port_allocate (mach_task_self (),
- MACH_PORT_RIGHT_RECEIVE,
- &our_message_port);
- if (ret != KERN_SUCCESS)
- warning ("Creating message port %s", mach_error_string (ret));
- else
- {
- char buf[MAX_NAME_LEN];
- ret = mach_port_move_member (mach_task_self (),
- our_message_port,
- inferior_wait_port_set);
- if (ret != KERN_SUCCESS)
- warning ("message move member %s", mach_error_string (ret));
-
-
- /* @@@@ No way to change message port name currently */
- /* Foo. This assumes gdb has a unix pid */
- sprintf (buf, "gdb-%d", getpid ());
- gdb_register_port (buf, our_message_port);
- }
-
- /* Heap for thread commands */
- obstack_init (cproc_obstack);
-
- add_mach_specific_commands ();
-}
+// OBSOLETE /* Interface GDB to Mach 3.0 operating systems.
+// OBSOLETE (Most) Mach 3.0 related routines live in this file.
+// OBSOLETE
+// OBSOLETE Copyright 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
+// OBSOLETE 2002 Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Author: Jukka Virtanen <jtv@hut.fi>
+// OBSOLETE * Computing Centre
+// OBSOLETE * Helsinki University of Technology
+// OBSOLETE * Finland
+// OBSOLETE *
+// OBSOLETE * Thanks to my friends who helped with ideas and testing:
+// OBSOLETE *
+// OBSOLETE * Johannes Helander, Antti Louko, Tero Mononen,
+// OBSOLETE * jvh@cs.hut.fi alo@hut.fi tmo@cs.hut.fi
+// OBSOLETE *
+// OBSOLETE * Tero Kivinen and Eamonn McManus
+// OBSOLETE * kivinen@cs.hut.fi emcmanus@gr.osf.org
+// OBSOLETE *
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE #include <stdio.h>
+// OBSOLETE
+// OBSOLETE #include <mach.h>
+// OBSOLETE #include <servers/netname.h>
+// OBSOLETE #include <servers/machid.h>
+// OBSOLETE #include <mach/message.h>
+// OBSOLETE #include <mach/notify.h>
+// OBSOLETE #include <mach_error.h>
+// OBSOLETE #include <mach/exception.h>
+// OBSOLETE #include <mach/vm_attributes.h>
+// OBSOLETE
+// OBSOLETE #include "defs.h"
+// OBSOLETE #include "inferior.h"
+// OBSOLETE #include "symtab.h"
+// OBSOLETE #include "value.h"
+// OBSOLETE #include "language.h"
+// OBSOLETE #include "target.h"
+// OBSOLETE #include "gdb_wait.h"
+// OBSOLETE #include "gdbcmd.h"
+// OBSOLETE #include "gdbcore.h"
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE #if 0
+// OBSOLETE #include <servers/machid_lib.h>
+// OBSOLETE #else
+// OBSOLETE #define MACH_TYPE_TASK 1
+// OBSOLETE #define MACH_TYPE_THREAD 2
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* Included only for signal names and NSIG
+// OBSOLETE
+// OBSOLETE * note: There are many problems in signal handling with
+// OBSOLETE * gdb in Mach 3.0 in general.
+// OBSOLETE */
+// OBSOLETE #include <signal.h>
+// OBSOLETE #define SIG_UNKNOWN 0 /* Exception that has no matching unix signal */
+// OBSOLETE
+// OBSOLETE #include <cthreads.h>
+// OBSOLETE
+// OBSOLETE /* This is what a cproc looks like. This is here partly because
+// OBSOLETE cthread_internals.h is not a header we can just #include, partly with
+// OBSOLETE an eye towards perhaps getting this to work with cross-debugging
+// OBSOLETE someday. Best solution is if CMU publishes a real interface to this
+// OBSOLETE stuff. */
+// OBSOLETE #define CPROC_NEXT_OFFSET 0
+// OBSOLETE #define CPROC_NEXT_SIZE (TARGET_PTR_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_INCARNATION_OFFSET (CPROC_NEXT_OFFSET + CPROC_NEXT_SIZE)
+// OBSOLETE #define CPROC_INCARNATION_SIZE (sizeof (cthread_t))
+// OBSOLETE #define CPROC_LIST_OFFSET (CPROC_INCARNATION_OFFSET + CPROC_INCARNATION_SIZE)
+// OBSOLETE #define CPROC_LIST_SIZE (TARGET_PTR_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_WAIT_OFFSET (CPROC_LIST_OFFSET + CPROC_LIST_SIZE)
+// OBSOLETE #define CPROC_WAIT_SIZE (TARGET_PTR_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_REPLY_OFFSET (CPROC_WAIT_OFFSET + CPROC_WAIT_SIZE)
+// OBSOLETE #define CPROC_REPLY_SIZE (sizeof (mach_port_t))
+// OBSOLETE #define CPROC_CONTEXT_OFFSET (CPROC_REPLY_OFFSET + CPROC_REPLY_SIZE)
+// OBSOLETE #define CPROC_CONTEXT_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_LOCK_OFFSET (CPROC_CONTEXT_OFFSET + CPROC_CONTEXT_SIZE)
+// OBSOLETE #define CPROC_LOCK_SIZE (sizeof (spin_lock_t))
+// OBSOLETE #define CPROC_STATE_OFFSET (CPROC_LOCK_OFFSET + CPROC_LOCK_SIZE)
+// OBSOLETE #define CPROC_STATE_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_WIRED_OFFSET (CPROC_STATE_OFFSET + CPROC_STATE_SIZE)
+// OBSOLETE #define CPROC_WIRED_SIZE (sizeof (mach_port_t))
+// OBSOLETE #define CPROC_BUSY_OFFSET (CPROC_WIRED_OFFSET + CPROC_WIRED_SIZE)
+// OBSOLETE #define CPROC_BUSY_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_MSG_OFFSET (CPROC_BUSY_OFFSET + CPROC_BUSY_SIZE)
+// OBSOLETE #define CPROC_MSG_SIZE (sizeof (mach_msg_header_t))
+// OBSOLETE #define CPROC_BASE_OFFSET (CPROC_MSG_OFFSET + CPROC_MSG_SIZE)
+// OBSOLETE #define CPROC_BASE_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_SIZE_OFFSET (CPROC_BASE_OFFSET + CPROC_BASE_SIZE)
+// OBSOLETE #define CPROC_SIZE_SIZE (TARGET_INT_BIT / HOST_CHAR_BIT)
+// OBSOLETE #define CPROC_SIZE (CPROC_SIZE_OFFSET + CPROC_SIZE_SIZE)
+// OBSOLETE
+// OBSOLETE /* Values for the state field in the cproc. */
+// OBSOLETE #define CPROC_RUNNING 0
+// OBSOLETE #define CPROC_SWITCHING 1
+// OBSOLETE #define CPROC_BLOCKED 2
+// OBSOLETE #define CPROC_CONDWAIT 4
+// OBSOLETE
+// OBSOLETE /* For cproc and kernel thread mapping */
+// OBSOLETE typedef struct gdb_thread
+// OBSOLETE {
+// OBSOLETE mach_port_t name;
+// OBSOLETE CORE_ADDR sp;
+// OBSOLETE CORE_ADDR pc;
+// OBSOLETE CORE_ADDR fp;
+// OBSOLETE boolean_t in_emulator;
+// OBSOLETE int slotid;
+// OBSOLETE
+// OBSOLETE /* This is for the mthreads list. It points to the cproc list.
+// OBSOLETE Perhaps the two lists should be merged (or perhaps it was a mistake
+// OBSOLETE to make them both use a struct gdb_thread). */
+// OBSOLETE struct gdb_thread *cproc;
+// OBSOLETE
+// OBSOLETE /* These are for the cproc list, which is linked through the next field
+// OBSOLETE of the struct gdb_thread. */
+// OBSOLETE char raw_cproc[CPROC_SIZE];
+// OBSOLETE /* The cthread which is pointed to by the incarnation field from the
+// OBSOLETE cproc. This points to the copy we've read into GDB. */
+// OBSOLETE cthread_t cthread;
+// OBSOLETE /* Point back to the mthreads list. */
+// OBSOLETE int reverse_map;
+// OBSOLETE struct gdb_thread *next;
+// OBSOLETE }
+// OBSOLETE *gdb_thread_t;
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Actions for Mach exceptions.
+// OBSOLETE *
+// OBSOLETE * sigmap field maps the exception to corresponding Unix signal.
+// OBSOLETE *
+// OBSOLETE * I do not know how to map the exception to unix signal
+// OBSOLETE * if SIG_UNKNOWN is specified.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE struct exception_list
+// OBSOLETE {
+// OBSOLETE char *name;
+// OBSOLETE boolean_t forward;
+// OBSOLETE boolean_t print;
+// OBSOLETE int sigmap;
+// OBSOLETE }
+// OBSOLETE exception_map[] =
+// OBSOLETE {
+// OBSOLETE {
+// OBSOLETE "not_mach3_exception", FALSE, TRUE, SIG_UNKNOWN
+// OBSOLETE }
+// OBSOLETE ,
+// OBSOLETE {
+// OBSOLETE "EXC_BAD_ACCESS", FALSE, TRUE, SIGSEGV
+// OBSOLETE }
+// OBSOLETE ,
+// OBSOLETE {
+// OBSOLETE "EXC_BAD_INSTRUCTION", FALSE, TRUE, SIGILL
+// OBSOLETE }
+// OBSOLETE ,
+// OBSOLETE {
+// OBSOLETE "EXC_ARITHMETIC", FALSE, TRUE, SIGFPE
+// OBSOLETE }
+// OBSOLETE ,
+// OBSOLETE {
+// OBSOLETE "EXC_EMULATION", FALSE, TRUE, SIGEMT
+// OBSOLETE }
+// OBSOLETE , /* ??? */
+// OBSOLETE {
+// OBSOLETE "EXC_SOFTWARE", FALSE, TRUE, SIG_UNKNOWN
+// OBSOLETE }
+// OBSOLETE ,
+// OBSOLETE {
+// OBSOLETE "EXC_BREAKPOINT", FALSE, FALSE, SIGTRAP
+// OBSOLETE }
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE /* Mach exception table size */
+// OBSOLETE int max_exception = sizeof (exception_map) / sizeof (struct exception_list) - 1;
+// OBSOLETE
+// OBSOLETE #define MAX_EXCEPTION max_exception
+// OBSOLETE
+// OBSOLETE WAITTYPE wait_status;
+// OBSOLETE
+// OBSOLETE /* If you define this, intercepted bsd server calls will be
+// OBSOLETE * dumped while waiting the inferior to EXEC the correct
+// OBSOLETE * program
+// OBSOLETE */
+// OBSOLETE /* #define DUMP_SYSCALL /* debugging interceptor */
+// OBSOLETE
+// OBSOLETE /* xx_debug() outputs messages if this is nonzero.
+// OBSOLETE * If > 1, DUMP_SYSCALL will dump message contents.
+// OBSOLETE */
+// OBSOLETE int debug_level = 0;
+// OBSOLETE
+// OBSOLETE /* "Temporary" debug stuff */
+// OBSOLETE void
+// OBSOLETE xx_debug (char *fmt, int a, int b, int c)
+// OBSOLETE {
+// OBSOLETE if (debug_level)
+// OBSOLETE warning (fmt, a, b, c);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* This is in libmach.a */
+// OBSOLETE extern mach_port_t name_server_port;
+// OBSOLETE
+// OBSOLETE /* Set in catch_exception_raise */
+// OBSOLETE int stop_exception, stop_code, stop_subcode;
+// OBSOLETE int stopped_in_exception;
+// OBSOLETE
+// OBSOLETE /* Thread that was the active thread when we stopped */
+// OBSOLETE thread_t stop_thread = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE char *hostname = "";
+// OBSOLETE
+// OBSOLETE /* Set when task is attached or created */
+// OBSOLETE boolean_t emulator_present = FALSE;
+// OBSOLETE
+// OBSOLETE task_t inferior_task;
+// OBSOLETE thread_t current_thread;
+// OBSOLETE
+// OBSOLETE /* Exception ports for inferior task */
+// OBSOLETE mach_port_t inferior_exception_port = MACH_PORT_NULL;
+// OBSOLETE mach_port_t inferior_old_exception_port = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE /* task exceptions and notifications */
+// OBSOLETE mach_port_t inferior_wait_port_set = MACH_PORT_NULL;
+// OBSOLETE mach_port_t our_notify_port = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE /* This is "inferior_wait_port_set" when not single stepping, and
+// OBSOLETE * "singlestepped_thread_port" when we are single stepping.
+// OBSOLETE *
+// OBSOLETE * This is protected by a cleanup function: discard_single_step()
+// OBSOLETE */
+// OBSOLETE mach_port_t currently_waiting_for = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE /* A port for external messages to gdb.
+// OBSOLETE * External in the meaning that they do not come
+// OBSOLETE * from the inferior_task, but rather from external
+// OBSOLETE * tasks.
+// OBSOLETE *
+// OBSOLETE * As a debugging feature:
+// OBSOLETE * A debugger debugging another debugger can stop the
+// OBSOLETE * inferior debugger by the following command sequence
+// OBSOLETE * (without running external programs)
+// OBSOLETE *
+// OBSOLETE * (top-gdb) set stop_inferior_gdb ()
+// OBSOLETE * (top-gdb) continue
+// OBSOLETE */
+// OBSOLETE mach_port_t our_message_port = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE /* For single stepping */
+// OBSOLETE mach_port_t thread_exception_port = MACH_PORT_NULL;
+// OBSOLETE mach_port_t thread_saved_exception_port = MACH_PORT_NULL;
+// OBSOLETE mach_port_t singlestepped_thread_port = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE /* For machid calls */
+// OBSOLETE mach_port_t mid_server = MACH_PORT_NULL;
+// OBSOLETE mach_port_t mid_auth = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE /* If gdb thinks the inferior task is not suspended, it
+// OBSOLETE * must take suspend/abort the threads when it reads the state.
+// OBSOLETE */
+// OBSOLETE int must_suspend_thread = 0;
+// OBSOLETE
+// OBSOLETE /* When single stepping, we switch the port that mach_really_wait() listens to.
+// OBSOLETE * This cleanup is a guard to prevent the port set from being left to
+// OBSOLETE * the singlestepped_thread_port when error() is called.
+// OBSOLETE * This is nonzero only when we are single stepping.
+// OBSOLETE */
+// OBSOLETE #define NULL_CLEANUP (struct cleanup *)0
+// OBSOLETE struct cleanup *cleanup_step = NULL_CLEANUP;
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE static struct target_ops m3_ops;
+// OBSOLETE
+// OBSOLETE static void m3_kill_inferior ();
+// OBSOLETE \f
+// OBSOLETE #if 0
+// OBSOLETE #define MACH_TYPE_EXCEPTION_PORT -1
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* Chain of ports to remember requested notifications. */
+// OBSOLETE
+// OBSOLETE struct port_chain
+// OBSOLETE {
+// OBSOLETE struct port_chain *next;
+// OBSOLETE mach_port_t port;
+// OBSOLETE int type;
+// OBSOLETE int mid; /* Now only valid with MACH_TYPE_THREAD and */
+// OBSOLETE /* MACH_TYPE_THREAD */
+// OBSOLETE };
+// OBSOLETE typedef struct port_chain *port_chain_t;
+// OBSOLETE
+// OBSOLETE /* Room for chain nodes comes from pchain_obstack */
+// OBSOLETE struct obstack pchain_obstack;
+// OBSOLETE struct obstack *port_chain_obstack = &pchain_obstack;
+// OBSOLETE
+// OBSOLETE /* For thread handling */
+// OBSOLETE struct obstack Cproc_obstack;
+// OBSOLETE struct obstack *cproc_obstack = &Cproc_obstack;
+// OBSOLETE
+// OBSOLETE /* the list of notified ports */
+// OBSOLETE port_chain_t notify_chain = (port_chain_t) NULL;
+// OBSOLETE
+// OBSOLETE port_chain_t
+// OBSOLETE port_chain_insert (port_chain_t list, mach_port_t name, int type)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE port_chain_t new;
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (name))
+// OBSOLETE return list;
+// OBSOLETE
+// OBSOLETE if (type == MACH_TYPE_TASK || type == MACH_TYPE_THREAD)
+// OBSOLETE {
+// OBSOLETE if (!MACH_PORT_VALID (mid_server))
+// OBSOLETE {
+// OBSOLETE warning ("Machid server port invalid, can not map port 0x%x to MID",
+// OBSOLETE name);
+// OBSOLETE mid = name;
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE ret = machid_mach_register (mid_server, mid_auth, name, type, &mid);
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Can not map name (0x%x) to MID with machid", name);
+// OBSOLETE mid = name;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE internal_error (__FILE__, __LINE__, "failed internal consistency check");
+// OBSOLETE
+// OBSOLETE new = (port_chain_t) obstack_alloc (port_chain_obstack,
+// OBSOLETE sizeof (struct port_chain));
+// OBSOLETE new->next = list;
+// OBSOLETE new->port = name;
+// OBSOLETE new->type = type;
+// OBSOLETE new->mid = mid;
+// OBSOLETE
+// OBSOLETE return new;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE port_chain_t
+// OBSOLETE port_chain_delete (port_chain_t list, mach_port_t elem)
+// OBSOLETE {
+// OBSOLETE if (list)
+// OBSOLETE if (list->port == elem)
+// OBSOLETE list = list->next;
+// OBSOLETE else
+// OBSOLETE while (list->next)
+// OBSOLETE {
+// OBSOLETE if (list->next->port == elem)
+// OBSOLETE list->next = list->next->next; /* GCd with obstack_free() */
+// OBSOLETE else
+// OBSOLETE list = list->next;
+// OBSOLETE }
+// OBSOLETE return list;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE port_chain_destroy (struct obstack *ostack)
+// OBSOLETE {
+// OBSOLETE obstack_free (ostack, 0);
+// OBSOLETE obstack_init (ostack);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE port_chain_t
+// OBSOLETE port_chain_member (port_chain_t list, mach_port_t elem)
+// OBSOLETE {
+// OBSOLETE while (list)
+// OBSOLETE {
+// OBSOLETE if (list->port == elem)
+// OBSOLETE return list;
+// OBSOLETE list = list->next;
+// OBSOLETE }
+// OBSOLETE return (port_chain_t) NULL;
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE int
+// OBSOLETE map_port_name_to_mid (mach_port_t name, int type)
+// OBSOLETE {
+// OBSOLETE port_chain_t elem;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (name))
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE elem = port_chain_member (notify_chain, name);
+// OBSOLETE
+// OBSOLETE if (elem && (elem->type == type))
+// OBSOLETE return elem->mid;
+// OBSOLETE
+// OBSOLETE if (elem)
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (mid_server))
+// OBSOLETE {
+// OBSOLETE warning ("Machid server port invalid, can not map port 0x%x to mid",
+// OBSOLETE name);
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE ret = machid_mach_register (mid_server, mid_auth, name, type, &mid);
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Can not map name (0x%x) to mid with machid", name);
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE return mid;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* Guard for currently_waiting_for and singlestepped_thread_port */
+// OBSOLETE static void
+// OBSOLETE discard_single_step (thread_t thread)
+// OBSOLETE {
+// OBSOLETE currently_waiting_for = inferior_wait_port_set;
+// OBSOLETE
+// OBSOLETE cleanup_step = NULL_CLEANUP;
+// OBSOLETE if (MACH_PORT_VALID (thread) && MACH_PORT_VALID (singlestepped_thread_port))
+// OBSOLETE setup_single_step (thread, FALSE);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE setup_single_step (thread_t thread, boolean_t start_step)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (thread))
+// OBSOLETE error ("Invalid thread supplied to setup_single_step");
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE mach_port_t teport;
+// OBSOLETE
+// OBSOLETE /* Get the current thread exception port */
+// OBSOLETE ret = thread_get_exception_port (thread, &teport);
+// OBSOLETE CHK ("Getting thread's exception port", ret);
+// OBSOLETE
+// OBSOLETE if (start_step)
+// OBSOLETE {
+// OBSOLETE if (MACH_PORT_VALID (singlestepped_thread_port))
+// OBSOLETE {
+// OBSOLETE warning ("Singlestepped_thread_port (0x%x) is still valid?",
+// OBSOLETE singlestepped_thread_port);
+// OBSOLETE singlestepped_thread_port = MACH_PORT_NULL;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* If we are already stepping this thread */
+// OBSOLETE if (MACH_PORT_VALID (teport) && teport == thread_exception_port)
+// OBSOLETE {
+// OBSOLETE ret = mach_port_deallocate (mach_task_self (), teport);
+// OBSOLETE CHK ("Could not deallocate thread exception port", ret);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE ret = thread_set_exception_port (thread, thread_exception_port);
+// OBSOLETE CHK ("Setting exception port for thread", ret);
+// OBSOLETE #if 0
+// OBSOLETE /* Insert thread exception port to wait port set */
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE thread_exception_port,
+// OBSOLETE inferior_wait_port_set);
+// OBSOLETE CHK ("Moving thread exception port to inferior_wait_port_set",
+// OBSOLETE ret);
+// OBSOLETE #endif
+// OBSOLETE thread_saved_exception_port = teport;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE thread_trace (thread, TRUE);
+// OBSOLETE
+// OBSOLETE singlestepped_thread_port = thread_exception_port;
+// OBSOLETE currently_waiting_for = singlestepped_thread_port;
+// OBSOLETE cleanup_step = make_cleanup (discard_single_step, thread);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE if (!MACH_PORT_VALID (teport))
+// OBSOLETE error ("Single stepped thread had an invalid exception port?");
+// OBSOLETE
+// OBSOLETE if (teport != thread_exception_port)
+// OBSOLETE error ("Single stepped thread had an unknown exception port?");
+// OBSOLETE
+// OBSOLETE ret = mach_port_deallocate (mach_task_self (), teport);
+// OBSOLETE CHK ("Couldn't deallocate thread exception port", ret);
+// OBSOLETE #if 0
+// OBSOLETE /* Remove thread exception port from wait port set */
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE thread_exception_port,
+// OBSOLETE MACH_PORT_NULL);
+// OBSOLETE CHK ("Removing thread exception port from inferior_wait_port_set",
+// OBSOLETE ret);
+// OBSOLETE #endif
+// OBSOLETE /* Restore thread's old exception port */
+// OBSOLETE ret = thread_set_exception_port (thread,
+// OBSOLETE thread_saved_exception_port);
+// OBSOLETE CHK ("Restoring stepped thread's exception port", ret);
+// OBSOLETE
+// OBSOLETE if (MACH_PORT_VALID (thread_saved_exception_port))
+// OBSOLETE (void) mach_port_deallocate (mach_task_self (),
+// OBSOLETE thread_saved_exception_port);
+// OBSOLETE
+// OBSOLETE thread_trace (thread, FALSE);
+// OBSOLETE
+// OBSOLETE singlestepped_thread_port = MACH_PORT_NULL;
+// OBSOLETE currently_waiting_for = inferior_wait_port_set;
+// OBSOLETE if (cleanup_step)
+// OBSOLETE discard_cleanups (cleanup_step);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE static
+// OBSOLETE request_notify (mach_port_t name, mach_msg_id_t variant, int type)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE mach_port_t previous_port_dummy = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (name))
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE if (port_chain_member (notify_chain, name))
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE ret = mach_port_request_notification (mach_task_self (),
+// OBSOLETE name,
+// OBSOLETE variant,
+// OBSOLETE 1,
+// OBSOLETE our_notify_port,
+// OBSOLETE MACH_MSG_TYPE_MAKE_SEND_ONCE,
+// OBSOLETE &previous_port_dummy);
+// OBSOLETE CHK ("Serious: request_notify failed", ret);
+// OBSOLETE
+// OBSOLETE (void) mach_port_deallocate (mach_task_self (),
+// OBSOLETE previous_port_dummy);
+// OBSOLETE
+// OBSOLETE notify_chain = port_chain_insert (notify_chain, name, type);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE reverse_msg_bits (mach_msg_header_t *msgp, int type)
+// OBSOLETE {
+// OBSOLETE int rbits, lbits;
+// OBSOLETE rbits = MACH_MSGH_BITS_REMOTE (msgp->msgh_bits);
+// OBSOLETE lbits = type;
+// OBSOLETE msgp->msgh_bits =
+// OBSOLETE (msgp->msgh_bits & ~MACH_MSGH_BITS_PORTS_MASK) |
+// OBSOLETE MACH_MSGH_BITS (lbits, rbits);
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* On the third day He said:
+// OBSOLETE
+// OBSOLETE Let this be global
+// OBSOLETE and then it was global.
+// OBSOLETE
+// OBSOLETE When creating the inferior fork, the
+// OBSOLETE child code in inflow.c sets the name of the
+// OBSOLETE bootstrap_port in its address space to this
+// OBSOLETE variable.
+// OBSOLETE
+// OBSOLETE The name is transferred to our address space
+// OBSOLETE with mach3_read_inferior().
+// OBSOLETE
+// OBSOLETE Thou shalt not do this with
+// OBSOLETE task_get_bootstrap_port() in this task, since
+// OBSOLETE the name in the inferior task is different than
+// OBSOLETE the one we get.
+// OBSOLETE
+// OBSOLETE For blessed are the meek, as they shall inherit
+// OBSOLETE the address space.
+// OBSOLETE */
+// OBSOLETE mach_port_t original_server_port_name = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE /* Called from inferior after FORK but before EXEC */
+// OBSOLETE static void
+// OBSOLETE m3_trace_me (void)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE /* Get the NAME of the bootstrap port in this task
+// OBSOLETE so that GDB can read it */
+// OBSOLETE ret = task_get_bootstrap_port (mach_task_self (),
+// OBSOLETE &original_server_port_name);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE internal_error (__FILE__, __LINE__, "failed internal consistency check");
+// OBSOLETE ret = mach_port_deallocate (mach_task_self (),
+// OBSOLETE original_server_port_name);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE internal_error (__FILE__, __LINE__, "failed internal consistency check");
+// OBSOLETE
+// OBSOLETE /* Suspend this task to let the parent change my ports.
+// OBSOLETE Resumed by the debugger */
+// OBSOLETE ret = task_suspend (mach_task_self ());
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE internal_error (__FILE__, __LINE__, "failed internal consistency check");
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /*
+// OBSOLETE * Intercept system calls to Unix server.
+// OBSOLETE * After EXEC_COUNTER calls to exec(), return.
+// OBSOLETE *
+// OBSOLETE * Pre-assertion: Child is suspended. (Not verified)
+// OBSOLETE * Post-condition: Child is suspended after EXEC_COUNTER exec() calls.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE intercept_exec_calls (int exec_counter)
+// OBSOLETE {
+// OBSOLETE int terminal_initted = 0;
+// OBSOLETE
+// OBSOLETE struct syscall_msg_t
+// OBSOLETE {
+// OBSOLETE mach_msg_header_t header;
+// OBSOLETE mach_msg_type_t type;
+// OBSOLETE char room[2000]; /* Enuff space */
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE struct syscall_msg_t syscall_in, syscall_out;
+// OBSOLETE
+// OBSOLETE mach_port_t fake_server;
+// OBSOLETE mach_port_t original_server_send;
+// OBSOLETE mach_port_t original_exec_reply;
+// OBSOLETE mach_port_t exec_reply;
+// OBSOLETE mach_port_t exec_reply_send;
+// OBSOLETE mach_msg_type_name_t acquired;
+// OBSOLETE mach_port_t emulator_server_port_name;
+// OBSOLETE struct task_basic_info info;
+// OBSOLETE mach_msg_type_number_t info_count;
+// OBSOLETE
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (exec_counter <= 0)
+// OBSOLETE return; /* We are already set up in the correct program */
+// OBSOLETE
+// OBSOLETE ret = mach_port_allocate (mach_task_self (),
+// OBSOLETE MACH_PORT_RIGHT_RECEIVE,
+// OBSOLETE &fake_server);
+// OBSOLETE CHK ("create inferior_fake_server port failed", ret);
+// OBSOLETE
+// OBSOLETE /* Wait for inferior_task to suspend itself */
+// OBSOLETE while (1)
+// OBSOLETE {
+// OBSOLETE info_count = sizeof (info);
+// OBSOLETE ret = task_info (inferior_task,
+// OBSOLETE TASK_BASIC_INFO,
+// OBSOLETE (task_info_t) & info,
+// OBSOLETE &info_count);
+// OBSOLETE CHK ("Task info", ret);
+// OBSOLETE
+// OBSOLETE if (info.suspend_count)
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE /* Note that the definition of the parameter was undefined
+// OBSOLETE * at the time of this writing, so I just use an `ad hoc' value.
+// OBSOLETE */
+// OBSOLETE (void) swtch_pri (42); /* Universal Priority Value */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Read the inferior's bootstrap port name */
+// OBSOLETE if (!mach3_read_inferior (&original_server_port_name,
+// OBSOLETE &original_server_port_name,
+// OBSOLETE sizeof (original_server_port_name)))
+// OBSOLETE error ("Can't read inferior task bootstrap port name");
+// OBSOLETE
+// OBSOLETE /* @@ BUG: If more than 1 send right GDB will FAIL!!! */
+// OBSOLETE /* Should get refs, and set them back when restoring */
+// OBSOLETE /* Steal the original bsd server send right from inferior */
+// OBSOLETE ret = mach_port_extract_right (inferior_task,
+// OBSOLETE original_server_port_name,
+// OBSOLETE MACH_MSG_TYPE_MOVE_SEND,
+// OBSOLETE &original_server_send,
+// OBSOLETE &acquired);
+// OBSOLETE CHK ("mach_port_extract_right (bsd server send)", ret);
+// OBSOLETE
+// OBSOLETE if (acquired != MACH_MSG_TYPE_PORT_SEND)
+// OBSOLETE error ("Incorrect right extracted, send right to bsd server expected");
+// OBSOLETE
+// OBSOLETE ret = mach_port_insert_right (inferior_task,
+// OBSOLETE original_server_port_name,
+// OBSOLETE fake_server,
+// OBSOLETE MACH_MSG_TYPE_MAKE_SEND);
+// OBSOLETE CHK ("mach_port_insert_right (fake server send)", ret);
+// OBSOLETE
+// OBSOLETE xx_debug ("inferior task bsd server ports set up \nfs %x, ospn %x, oss %x\n",
+// OBSOLETE fake_server,
+// OBSOLETE original_server_port_name, original_server_send);
+// OBSOLETE
+// OBSOLETE /* A receive right to the reply generated by unix server exec() request */
+// OBSOLETE ret = mach_port_allocate (mach_task_self (),
+// OBSOLETE MACH_PORT_RIGHT_RECEIVE,
+// OBSOLETE &exec_reply);
+// OBSOLETE CHK ("create intercepted_reply_port port failed", ret);
+// OBSOLETE
+// OBSOLETE /* Pass this send right to Unix server so it replies to us after exec() */
+// OBSOLETE ret = mach_port_extract_right (mach_task_self (),
+// OBSOLETE exec_reply,
+// OBSOLETE MACH_MSG_TYPE_MAKE_SEND_ONCE,
+// OBSOLETE &exec_reply_send,
+// OBSOLETE &acquired);
+// OBSOLETE CHK ("mach_port_extract_right (exec_reply)", ret);
+// OBSOLETE
+// OBSOLETE if (acquired != MACH_MSG_TYPE_PORT_SEND_ONCE)
+// OBSOLETE error ("Incorrect right extracted, send once expected for exec reply");
+// OBSOLETE
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE fake_server,
+// OBSOLETE inferior_wait_port_set);
+// OBSOLETE CHK ("Moving fake syscall port to inferior_wait_port_set", ret);
+// OBSOLETE
+// OBSOLETE xx_debug ("syscall fake server set up, resuming inferior\n");
+// OBSOLETE
+// OBSOLETE ret = task_resume (inferior_task);
+// OBSOLETE CHK ("task_resume (startup)", ret);
+// OBSOLETE
+// OBSOLETE /* Read requests from the inferior.
+// OBSOLETE Pass directly through everything else except exec() calls.
+// OBSOLETE */
+// OBSOLETE while (exec_counter > 0)
+// OBSOLETE {
+// OBSOLETE ret = mach_msg (&syscall_in.header, /* header */
+// OBSOLETE MACH_RCV_MSG, /* options */
+// OBSOLETE 0, /* send size */
+// OBSOLETE sizeof (struct syscall_msg_t), /* receive size */
+// OBSOLETE inferior_wait_port_set, /* receive_name */
+// OBSOLETE MACH_MSG_TIMEOUT_NONE,
+// OBSOLETE MACH_PORT_NULL);
+// OBSOLETE CHK ("mach_msg (intercepted sycall)", ret);
+// OBSOLETE
+// OBSOLETE #ifdef DUMP_SYSCALL
+// OBSOLETE print_msg (&syscall_in.header);
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* ASSERT : msgh_local_port == fake_server */
+// OBSOLETE
+// OBSOLETE if (notify_server (&syscall_in.header, &syscall_out.header))
+// OBSOLETE error ("received a notify while intercepting syscalls");
+// OBSOLETE
+// OBSOLETE if (syscall_in.header.msgh_id == MIG_EXEC_SYSCALL_ID)
+// OBSOLETE {
+// OBSOLETE xx_debug ("Received EXEC SYSCALL, counter = %d\n", exec_counter);
+// OBSOLETE if (exec_counter == 1)
+// OBSOLETE {
+// OBSOLETE original_exec_reply = syscall_in.header.msgh_remote_port;
+// OBSOLETE syscall_in.header.msgh_remote_port = exec_reply_send;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!terminal_initted)
+// OBSOLETE {
+// OBSOLETE /* Now that the child has exec'd we know it has already set its
+// OBSOLETE process group. On POSIX systems, tcsetpgrp will fail with
+// OBSOLETE EPERM if we try it before the child's setpgid. */
+// OBSOLETE
+// OBSOLETE /* Set up the "saved terminal modes" of the inferior
+// OBSOLETE based on what modes we are starting it with. */
+// OBSOLETE target_terminal_init ();
+// OBSOLETE
+// OBSOLETE /* Install inferior's terminal modes. */
+// OBSOLETE target_terminal_inferior ();
+// OBSOLETE
+// OBSOLETE terminal_initted = 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE exec_counter--;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE syscall_in.header.msgh_local_port = syscall_in.header.msgh_remote_port;
+// OBSOLETE syscall_in.header.msgh_remote_port = original_server_send;
+// OBSOLETE
+// OBSOLETE reverse_msg_bits (&syscall_in.header, MACH_MSG_TYPE_COPY_SEND);
+// OBSOLETE
+// OBSOLETE ret = mach_msg_send (&syscall_in.header);
+// OBSOLETE CHK ("Forwarded syscall", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE fake_server,
+// OBSOLETE MACH_PORT_NULL);
+// OBSOLETE CHK ("Moving fake syscall out of inferior_wait_port_set", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE exec_reply,
+// OBSOLETE inferior_wait_port_set);
+// OBSOLETE CHK ("Moving exec_reply to inferior_wait_port_set", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_msg (&syscall_in.header, /* header */
+// OBSOLETE MACH_RCV_MSG, /* options */
+// OBSOLETE 0, /* send size */
+// OBSOLETE sizeof (struct syscall_msg_t), /* receive size */
+// OBSOLETE inferior_wait_port_set, /* receive_name */
+// OBSOLETE MACH_MSG_TIMEOUT_NONE,
+// OBSOLETE MACH_PORT_NULL);
+// OBSOLETE CHK ("mach_msg (exec reply)", ret);
+// OBSOLETE
+// OBSOLETE ret = task_suspend (inferior_task);
+// OBSOLETE CHK ("Suspending inferior after last exec", ret);
+// OBSOLETE
+// OBSOLETE must_suspend_thread = 0;
+// OBSOLETE
+// OBSOLETE xx_debug ("Received exec reply from bsd server, suspended inferior task\n");
+// OBSOLETE
+// OBSOLETE #ifdef DUMP_SYSCALL
+// OBSOLETE print_msg (&syscall_in.header);
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* Message should appear as if it came from the unix server */
+// OBSOLETE syscall_in.header.msgh_local_port = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE /* and go to the inferior task original reply port */
+// OBSOLETE syscall_in.header.msgh_remote_port = original_exec_reply;
+// OBSOLETE
+// OBSOLETE reverse_msg_bits (&syscall_in.header, MACH_MSG_TYPE_MOVE_SEND_ONCE);
+// OBSOLETE
+// OBSOLETE ret = mach_msg_send (&syscall_in.header);
+// OBSOLETE CHK ("Forwarding exec reply to inferior", ret);
+// OBSOLETE
+// OBSOLETE /* Garbage collect */
+// OBSOLETE ret = mach_port_deallocate (inferior_task,
+// OBSOLETE original_server_port_name);
+// OBSOLETE CHK ("deallocating fake server send right", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_insert_right (inferior_task,
+// OBSOLETE original_server_port_name,
+// OBSOLETE original_server_send,
+// OBSOLETE MACH_MSG_TYPE_MOVE_SEND);
+// OBSOLETE CHK ("Restoring the original bsd server send right", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_destroy (mach_task_self (),
+// OBSOLETE fake_server);
+// OBSOLETE fake_server = MACH_PORT_DEAD;
+// OBSOLETE CHK ("mach_port_destroy (fake_server)", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_destroy (mach_task_self (),
+// OBSOLETE exec_reply);
+// OBSOLETE exec_reply = MACH_PORT_DEAD;
+// OBSOLETE CHK ("mach_port_destroy (exec_reply)", ret);
+// OBSOLETE
+// OBSOLETE xx_debug ("Done with exec call interception\n");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE consume_send_rights (thread_array_t thread_list, int thread_count)
+// OBSOLETE {
+// OBSOLETE int index;
+// OBSOLETE
+// OBSOLETE if (!thread_count)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE {
+// OBSOLETE /* Since thread kill command kills threads, don't check ret */
+// OBSOLETE (void) mach_port_deallocate (mach_task_self (),
+// OBSOLETE thread_list[index]);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* suspend/abort/resume a thread. */
+// OBSOLETE setup_thread (mach_port_t thread, int what)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (what)
+// OBSOLETE {
+// OBSOLETE ret = thread_suspend (thread);
+// OBSOLETE CHK ("setup_thread thread_suspend", ret);
+// OBSOLETE
+// OBSOLETE ret = thread_abort (thread);
+// OBSOLETE CHK ("setup_thread thread_abort", ret);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE ret = thread_resume (thread);
+// OBSOLETE CHK ("setup_thread thread_resume", ret);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE map_slot_to_mid (int slot, thread_array_t threads, int thread_count)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int deallocate = 0;
+// OBSOLETE int index;
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE if (!threads)
+// OBSOLETE {
+// OBSOLETE deallocate++;
+// OBSOLETE ret = task_threads (inferior_task, &threads, &thread_count);
+// OBSOLETE CHK ("Can not select a thread from a dead task", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (slot < 0 || slot >= thread_count)
+// OBSOLETE {
+// OBSOLETE if (deallocate)
+// OBSOLETE {
+// OBSOLETE consume_send_rights (threads, thread_count);
+// OBSOLETE (void) vm_deallocate (mach_task_self (), (vm_address_t) threads,
+// OBSOLETE (thread_count * sizeof (mach_port_t)));
+// OBSOLETE }
+// OBSOLETE if (slot < 0)
+// OBSOLETE error ("invalid slot number");
+// OBSOLETE else
+// OBSOLETE return -(slot + 1);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE mid = map_port_name_to_mid (threads[slot], MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE if (deallocate)
+// OBSOLETE {
+// OBSOLETE consume_send_rights (threads, thread_count);
+// OBSOLETE (void) vm_deallocate (mach_task_self (), (vm_address_t) threads,
+// OBSOLETE (thread_count * sizeof (mach_port_t)));
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return mid;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE parse_thread_id (char *arg, int thread_count, int slots)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int mid;
+// OBSOLETE int slot;
+// OBSOLETE int index;
+// OBSOLETE
+// OBSOLETE if (arg == 0)
+// OBSOLETE return 0;
+// OBSOLETE
+// OBSOLETE while (*arg && (*arg == ' ' || *arg == '\t'))
+// OBSOLETE arg++;
+// OBSOLETE
+// OBSOLETE if (!*arg)
+// OBSOLETE return 0;
+// OBSOLETE
+// OBSOLETE /* Currently parse MID and @SLOTNUMBER */
+// OBSOLETE if (*arg != '@')
+// OBSOLETE {
+// OBSOLETE mid = atoi (arg);
+// OBSOLETE if (mid <= 0)
+// OBSOLETE error ("valid thread mid expected");
+// OBSOLETE return mid;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE arg++;
+// OBSOLETE slot = atoi (arg);
+// OBSOLETE
+// OBSOLETE if (slot < 0)
+// OBSOLETE error ("invalid slot number");
+// OBSOLETE
+// OBSOLETE /* If you want slot numbers to remain slot numbers, set slots.
+// OBSOLETE
+// OBSOLETE * Well, since 0 is reserved, return the ordinal number
+// OBSOLETE * of the thread rather than the slot number. Awk, this
+// OBSOLETE * counts as a kludge.
+// OBSOLETE */
+// OBSOLETE if (slots)
+// OBSOLETE return -(slot + 1);
+// OBSOLETE
+// OBSOLETE if (thread_count && slot >= thread_count)
+// OBSOLETE return -(slot + 1);
+// OBSOLETE
+// OBSOLETE mid = map_slot_to_mid (slot);
+// OBSOLETE
+// OBSOLETE return mid;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* THREAD_ID 0 is special; it selects the first kernel
+// OBSOLETE * thread from the list (i.e. SLOTNUMBER 0)
+// OBSOLETE * This is used when starting the program with 'run' or when attaching.
+// OBSOLETE *
+// OBSOLETE * If FLAG is 0 the context is not changed, and the registers, frame, etc
+// OBSOLETE * will continue to describe the old thread.
+// OBSOLETE *
+// OBSOLETE * If FLAG is nonzero, really select the thread.
+// OBSOLETE * If FLAG is 2, the THREAD_ID is a slotnumber instead of a mid.
+// OBSOLETE *
+// OBSOLETE */
+// OBSOLETE kern_return_t
+// OBSOLETE select_thread (mach_port_t task, int thread_id, int flag)
+// OBSOLETE {
+// OBSOLETE thread_array_t thread_list;
+// OBSOLETE int thread_count;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int index;
+// OBSOLETE thread_t new_thread = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE if (thread_id < 0)
+// OBSOLETE error ("Can't select cprocs without kernel thread");
+// OBSOLETE
+// OBSOLETE ret = task_threads (task, &thread_list, &thread_count);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Can not select a thread from a dead task");
+// OBSOLETE m3_kill_inferior ();
+// OBSOLETE return KERN_FAILURE;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (thread_count == 0)
+// OBSOLETE {
+// OBSOLETE /* The task can not do anything anymore, but it still
+// OBSOLETE * exists as a container for memory and ports.
+// OBSOLETE */
+// OBSOLETE registers_changed ();
+// OBSOLETE warning ("Task %d has no threads",
+// OBSOLETE map_port_name_to_mid (task, MACH_TYPE_TASK));
+// OBSOLETE current_thread = MACH_PORT_NULL;
+// OBSOLETE (void) vm_deallocate (mach_task_self (),
+// OBSOLETE (vm_address_t) thread_list,
+// OBSOLETE (thread_count * sizeof (mach_port_t)));
+// OBSOLETE return KERN_FAILURE;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!thread_id || flag == 2)
+// OBSOLETE {
+// OBSOLETE /* First thread or a slotnumber */
+// OBSOLETE if (!thread_id)
+// OBSOLETE new_thread = thread_list[0];
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE if (thread_id < thread_count)
+// OBSOLETE new_thread = thread_list[thread_id];
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE (void) vm_deallocate (mach_task_self (),
+// OBSOLETE (vm_address_t) thread_list,
+// OBSOLETE (thread_count * sizeof (mach_port_t)));
+// OBSOLETE error ("No such thread slot number : %d", thread_id);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE if (thread_id == map_port_name_to_mid (thread_list[index],
+// OBSOLETE MACH_TYPE_THREAD))
+// OBSOLETE {
+// OBSOLETE new_thread = thread_list[index];
+// OBSOLETE index = -1;
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (index != -1)
+// OBSOLETE error ("No thread with mid %d", thread_id);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Notify when the selected thread dies */
+// OBSOLETE request_notify (new_thread, MACH_NOTIFY_DEAD_NAME, MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE ret = vm_deallocate (mach_task_self (),
+// OBSOLETE (vm_address_t) thread_list,
+// OBSOLETE (thread_count * sizeof (mach_port_t)));
+// OBSOLETE CHK ("vm_deallocate", ret);
+// OBSOLETE
+// OBSOLETE if (!flag)
+// OBSOLETE current_thread = new_thread;
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE #if 0
+// OBSOLETE if (MACH_PORT_VALID (current_thread))
+// OBSOLETE {
+// OBSOLETE /* Store the gdb's view of the thread we are deselecting
+// OBSOLETE
+// OBSOLETE * @@ I think gdb updates registers immediately when they are
+// OBSOLETE * changed, so don't do this.
+// OBSOLETE */
+// OBSOLETE ret = thread_abort (current_thread);
+// OBSOLETE CHK ("Could not abort system calls when saving state of old thread",
+// OBSOLETE ret);
+// OBSOLETE target_prepare_to_store ();
+// OBSOLETE target_store_registers (-1);
+// OBSOLETE }
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE registers_changed ();
+// OBSOLETE
+// OBSOLETE current_thread = new_thread;
+// OBSOLETE
+// OBSOLETE ret = thread_abort (current_thread);
+// OBSOLETE CHK ("Could not abort system calls when selecting a thread", ret);
+// OBSOLETE
+// OBSOLETE stop_pc = read_pc ();
+// OBSOLETE flush_cached_frames ();
+// OBSOLETE
+// OBSOLETE select_frame (get_current_frame ());
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Switch to use thread named NEW_THREAD.
+// OBSOLETE * Return it's MID
+// OBSOLETE */
+// OBSOLETE int
+// OBSOLETE switch_to_thread (thread_t new_thread)
+// OBSOLETE {
+// OBSOLETE thread_t saved_thread = current_thread;
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE mid = map_port_name_to_mid (new_thread,
+// OBSOLETE MACH_TYPE_THREAD);
+// OBSOLETE if (mid == -1)
+// OBSOLETE warning ("Can't map thread name 0x%x to mid", new_thread);
+// OBSOLETE else if (select_thread (inferior_task, mid, 1) != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE if (current_thread)
+// OBSOLETE current_thread = saved_thread;
+// OBSOLETE error ("Could not select thread %d", mid);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return mid;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Do this in gdb after doing FORK but before STARTUP_INFERIOR.
+// OBSOLETE * Note that the registers are not yet valid in the inferior task.
+// OBSOLETE */
+// OBSOLETE static int
+// OBSOLETE m3_trace_him (int pid)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE push_target (&m3_ops);
+// OBSOLETE
+// OBSOLETE inferior_task = task_by_pid (pid);
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (inferior_task))
+// OBSOLETE error ("Can not map Unix pid %d to Mach task", pid);
+// OBSOLETE
+// OBSOLETE /* Clean up previous notifications and create new ones */
+// OBSOLETE setup_notify_port (1);
+// OBSOLETE
+// OBSOLETE /* When notification appears, the inferior task has died */
+// OBSOLETE request_notify (inferior_task, MACH_NOTIFY_DEAD_NAME, MACH_TYPE_TASK);
+// OBSOLETE
+// OBSOLETE emulator_present = have_emulator_p (inferior_task);
+// OBSOLETE
+// OBSOLETE /* By default, select the first thread,
+// OBSOLETE * If task has no threads, gives a warning
+// OBSOLETE * Does not fetch registers, since they are not yet valid.
+// OBSOLETE */
+// OBSOLETE select_thread (inferior_task, 0, 0);
+// OBSOLETE
+// OBSOLETE inferior_exception_port = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE setup_exception_port ();
+// OBSOLETE
+// OBSOLETE xx_debug ("Now the debugged task is created\n");
+// OBSOLETE
+// OBSOLETE /* One trap to exec the shell, one to exec the program being debugged. */
+// OBSOLETE intercept_exec_calls (2);
+// OBSOLETE
+// OBSOLETE return pid;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE setup_exception_port (void)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE ret = mach_port_allocate (mach_task_self (),
+// OBSOLETE MACH_PORT_RIGHT_RECEIVE,
+// OBSOLETE &inferior_exception_port);
+// OBSOLETE CHK ("mach_port_allocate", ret);
+// OBSOLETE
+// OBSOLETE /* add send right */
+// OBSOLETE ret = mach_port_insert_right (mach_task_self (),
+// OBSOLETE inferior_exception_port,
+// OBSOLETE inferior_exception_port,
+// OBSOLETE MACH_MSG_TYPE_MAKE_SEND);
+// OBSOLETE CHK ("mach_port_insert_right", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE inferior_exception_port,
+// OBSOLETE inferior_wait_port_set);
+// OBSOLETE CHK ("mach_port_move_member", ret);
+// OBSOLETE
+// OBSOLETE ret = task_get_special_port (inferior_task,
+// OBSOLETE TASK_EXCEPTION_PORT,
+// OBSOLETE &inferior_old_exception_port);
+// OBSOLETE CHK ("task_get_special_port(old exc)", ret);
+// OBSOLETE
+// OBSOLETE ret = task_set_special_port (inferior_task,
+// OBSOLETE TASK_EXCEPTION_PORT,
+// OBSOLETE inferior_exception_port);
+// OBSOLETE CHK ("task_set_special_port", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_deallocate (mach_task_self (),
+// OBSOLETE inferior_exception_port);
+// OBSOLETE CHK ("mack_port_deallocate", ret);
+// OBSOLETE
+// OBSOLETE #if 0
+// OBSOLETE /* When notify appears, the inferior_task's exception
+// OBSOLETE * port has been destroyed.
+// OBSOLETE *
+// OBSOLETE * Not used, since the dead_name_notification already
+// OBSOLETE * appears when task dies.
+// OBSOLETE *
+// OBSOLETE */
+// OBSOLETE request_notify (inferior_exception_port,
+// OBSOLETE MACH_NOTIFY_NO_SENDERS,
+// OBSOLETE MACH_TYPE_EXCEPTION_PORT);
+// OBSOLETE #endif
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Nonzero if gdb is waiting for a message */
+// OBSOLETE int mach_really_waiting;
+// OBSOLETE
+// OBSOLETE /* Wait for the inferior to stop for some reason.
+// OBSOLETE - Loop on notifications until inferior_task dies.
+// OBSOLETE - Loop on exceptions until stopped_in_exception comes true.
+// OBSOLETE (e.g. we receive a single step trace trap)
+// OBSOLETE - a message arrives to gdb's message port
+// OBSOLETE
+// OBSOLETE There is no other way to exit this loop.
+// OBSOLETE
+// OBSOLETE Returns the inferior_ptid for rest of gdb.
+// OBSOLETE Side effects: Set *OURSTATUS. */
+// OBSOLETE ptid_t
+// OBSOLETE mach_really_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int w;
+// OBSOLETE
+// OBSOLETE struct msg
+// OBSOLETE {
+// OBSOLETE mach_msg_header_t header;
+// OBSOLETE mach_msg_type_t foo;
+// OBSOLETE int data[8000];
+// OBSOLETE }
+// OBSOLETE in_msg, out_msg;
+// OBSOLETE
+// OBSOLETE /* Either notify (death), exception or message can stop the inferior */
+// OBSOLETE stopped_in_exception = FALSE;
+// OBSOLETE
+// OBSOLETE while (1)
+// OBSOLETE {
+// OBSOLETE QUIT;
+// OBSOLETE
+// OBSOLETE stop_exception = stop_code = stop_subcode = -1;
+// OBSOLETE stop_thread = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE mach_really_waiting = 1;
+// OBSOLETE ret = mach_msg (&in_msg.header, /* header */
+// OBSOLETE MACH_RCV_MSG, /* options */
+// OBSOLETE 0, /* send size */
+// OBSOLETE sizeof (struct msg), /* receive size */
+// OBSOLETE currently_waiting_for, /* receive name */
+// OBSOLETE MACH_MSG_TIMEOUT_NONE,
+// OBSOLETE MACH_PORT_NULL);
+// OBSOLETE mach_really_waiting = 0;
+// OBSOLETE CHK ("mach_msg (receive)", ret);
+// OBSOLETE
+// OBSOLETE /* Check if we received a notify of the childs' death */
+// OBSOLETE if (notify_server (&in_msg.header, &out_msg.header))
+// OBSOLETE {
+// OBSOLETE /* If inferior_task is null then the inferior has
+// OBSOLETE gone away and we want to return to command level.
+// OBSOLETE Otherwise it was just an informative message and we
+// OBSOLETE need to look to see if there are any more. */
+// OBSOLETE if (inferior_task != MACH_PORT_NULL)
+// OBSOLETE continue;
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE /* Collect Unix exit status for gdb */
+// OBSOLETE
+// OBSOLETE wait3 (&w, WNOHANG, 0);
+// OBSOLETE
+// OBSOLETE /* This mess is here to check that the rest of
+// OBSOLETE * gdb knows that the inferior died. It also
+// OBSOLETE * tries to hack around the fact that Mach 3.0 (mk69)
+// OBSOLETE * unix server (ux28) does not always know what
+// OBSOLETE * has happened to it's children when mach-magic
+// OBSOLETE * is applied on them.
+// OBSOLETE */
+// OBSOLETE if ((!WIFEXITED (w) && WIFSTOPPED (w)) ||
+// OBSOLETE (WIFEXITED (w) && WEXITSTATUS (w) > 0377))
+// OBSOLETE {
+// OBSOLETE WSETEXIT (w, 0);
+// OBSOLETE warning ("Using exit value 0 for terminated task");
+// OBSOLETE }
+// OBSOLETE else if (!WIFEXITED (w))
+// OBSOLETE {
+// OBSOLETE int sig = WTERMSIG (w);
+// OBSOLETE
+// OBSOLETE /* Signals cause problems. Warn the user. */
+// OBSOLETE if (sig != SIGKILL) /* Bad luck if garbage matches this */
+// OBSOLETE warning ("The terminating signal stuff may be nonsense");
+// OBSOLETE else if (sig > NSIG)
+// OBSOLETE {
+// OBSOLETE WSETEXIT (w, 0);
+// OBSOLETE warning ("Using exit value 0 for terminated task");
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE store_waitstatus (ourstatus, w);
+// OBSOLETE return inferior_ptid;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Hmm. Check for exception, as it was not a notification.
+// OBSOLETE exc_server() does an upcall to catch_exception_raise()
+// OBSOLETE if this rpc is an exception. Further actions are decided
+// OBSOLETE there.
+// OBSOLETE */
+// OBSOLETE if (!exc_server (&in_msg.header, &out_msg.header))
+// OBSOLETE {
+// OBSOLETE
+// OBSOLETE /* Not an exception, check for message.
+// OBSOLETE
+// OBSOLETE * Messages don't come from the inferior, or if they
+// OBSOLETE * do they better be asynchronous or it will hang.
+// OBSOLETE */
+// OBSOLETE if (gdb_message_server (&in_msg.header))
+// OBSOLETE continue;
+// OBSOLETE
+// OBSOLETE error ("Unrecognized message received in mach_really_wait");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Send the reply of the exception rpc to the suspended task */
+// OBSOLETE ret = mach_msg_send (&out_msg.header);
+// OBSOLETE CHK ("mach_msg_send (exc reply)", ret);
+// OBSOLETE
+// OBSOLETE if (stopped_in_exception)
+// OBSOLETE {
+// OBSOLETE /* Get unix state. May be changed in mach3_exception_actions() */
+// OBSOLETE wait3 (&w, WNOHANG, 0);
+// OBSOLETE
+// OBSOLETE mach3_exception_actions (&w, FALSE, "Task");
+// OBSOLETE
+// OBSOLETE store_waitstatus (ourstatus, w);
+// OBSOLETE return inferior_ptid;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Called by macro DO_QUIT() in utils.c(quit).
+// OBSOLETE * This is called just before calling error() to return to command level
+// OBSOLETE */
+// OBSOLETE void
+// OBSOLETE mach3_quit (void)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (mach_really_waiting)
+// OBSOLETE {
+// OBSOLETE ret = task_suspend (inferior_task);
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Could not suspend task for interrupt: %s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE mach_really_waiting = 0;
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE must_suspend_thread = 0;
+// OBSOLETE mach_really_waiting = 0;
+// OBSOLETE
+// OBSOLETE mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
+// OBSOLETE if (mid == -1)
+// OBSOLETE {
+// OBSOLETE warning ("Selecting first existing kernel thread");
+// OBSOLETE mid = 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE current_thread = MACH_PORT_NULL; /* Force setup */
+// OBSOLETE select_thread (inferior_task, mid, 1);
+// OBSOLETE
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #if 0
+// OBSOLETE /* bogus bogus bogus. It is NOT OK to quit out of target_wait. */
+// OBSOLETE
+// OBSOLETE /* If ^C is typed when we are waiting for a message
+// OBSOLETE * and your Unix server is able to notice that we
+// OBSOLETE * should quit now.
+// OBSOLETE *
+// OBSOLETE * Called by REQUEST_QUIT() from utils.c(request_quit)
+// OBSOLETE */
+// OBSOLETE void
+// OBSOLETE mach3_request_quit (void)
+// OBSOLETE {
+// OBSOLETE if (mach_really_waiting)
+// OBSOLETE immediate_quit = 1;
+// OBSOLETE }
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Gdb message server.
+// OBSOLETE * Currently implemented is the STOP message, that causes
+// OBSOLETE * gdb to return to the command level like ^C had been typed from terminal.
+// OBSOLETE */
+// OBSOLETE int
+// OBSOLETE gdb_message_server (mach_msg_header_t *InP)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE if (InP->msgh_local_port == our_message_port)
+// OBSOLETE {
+// OBSOLETE /* A message coming to our_message_port. Check validity */
+// OBSOLETE switch (InP->msgh_id)
+// OBSOLETE {
+// OBSOLETE
+// OBSOLETE case GDB_MESSAGE_ID_STOP:
+// OBSOLETE ret = task_suspend (inferior_task);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("Could not suspend task for stop message: %s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE
+// OBSOLETE /* QUIT in mach_really_wait() loop. */
+// OBSOLETE request_quit (0);
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE default:
+// OBSOLETE warning ("Invalid message id %d received, ignored.",
+// OBSOLETE InP->msgh_id);
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Message not handled by this server */
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* NOTE: This is not an RPC call. It is a simpleroutine.
+// OBSOLETE
+// OBSOLETE * This is not called from this gdb code.
+// OBSOLETE *
+// OBSOLETE * It may be called by another debugger to cause this
+// OBSOLETE * debugger to enter command level:
+// OBSOLETE *
+// OBSOLETE * (gdb) set stop_inferior_gdb ()
+// OBSOLETE * (gdb) continue
+// OBSOLETE *
+// OBSOLETE * External program "stop-gdb" implements this also.
+// OBSOLETE */
+// OBSOLETE void
+// OBSOLETE stop_inferior_gdb (void)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE /* Code generated by mig, with minor cleanups :-)
+// OBSOLETE
+// OBSOLETE * simpleroutine stop_inferior_gdb (our_message_port : mach_port_t);
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE typedef struct
+// OBSOLETE {
+// OBSOLETE mach_msg_header_t Head;
+// OBSOLETE }
+// OBSOLETE Request;
+// OBSOLETE
+// OBSOLETE Request Mess;
+// OBSOLETE
+// OBSOLETE register Request *InP = &Mess;
+// OBSOLETE
+// OBSOLETE InP->Head.msgh_bits = MACH_MSGH_BITS (MACH_MSG_TYPE_COPY_SEND, 0);
+// OBSOLETE
+// OBSOLETE /* msgh_size passed as argument */
+// OBSOLETE InP->Head.msgh_remote_port = our_message_port;
+// OBSOLETE InP->Head.msgh_local_port = MACH_PORT_NULL;
+// OBSOLETE InP->Head.msgh_seqno = 0;
+// OBSOLETE InP->Head.msgh_id = GDB_MESSAGE_ID_STOP;
+// OBSOLETE
+// OBSOLETE ret = mach_msg (&InP->Head,
+// OBSOLETE MACH_SEND_MSG | MACH_MSG_OPTION_NONE,
+// OBSOLETE sizeof (Request),
+// OBSOLETE 0,
+// OBSOLETE MACH_PORT_NULL,
+// OBSOLETE MACH_MSG_TIMEOUT_NONE,
+// OBSOLETE MACH_PORT_NULL);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #ifdef THREAD_ALLOWED_TO_BREAK
+// OBSOLETE /*
+// OBSOLETE * Return 1 if the MID specifies the thread that caused the
+// OBSOLETE * last exception.
+// OBSOLETE * Since catch_exception_raise() selects the thread causing
+// OBSOLETE * the last exception to current_thread, we just check that
+// OBSOLETE * it is selected and the last exception was a breakpoint.
+// OBSOLETE */
+// OBSOLETE int
+// OBSOLETE mach_thread_for_breakpoint (int mid)
+// OBSOLETE {
+// OBSOLETE int cmid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE if (mid < 0)
+// OBSOLETE {
+// OBSOLETE mid = map_slot_to_mid (-(mid + 1), 0, 0);
+// OBSOLETE if (mid < 0)
+// OBSOLETE return 0; /* Don't stop, no such slot */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!mid || cmid == -1)
+// OBSOLETE return 1; /* stop */
+// OBSOLETE
+// OBSOLETE return cmid == mid && stop_exception == EXC_BREAKPOINT;
+// OBSOLETE }
+// OBSOLETE #endif /* THREAD_ALLOWED_TO_BREAK */
+// OBSOLETE
+// OBSOLETE #ifdef THREAD_PARSE_ID
+// OBSOLETE /*
+// OBSOLETE * Map a thread id string (MID or a @SLOTNUMBER)
+// OBSOLETE * to a thread-id.
+// OBSOLETE *
+// OBSOLETE * 0 matches all threads.
+// OBSOLETE * Otherwise the meaning is defined only in this file.
+// OBSOLETE * (mach_thread_for_breakpoint uses it)
+// OBSOLETE *
+// OBSOLETE * @@ This allows non-existent MIDs to be specified.
+// OBSOLETE * It now also allows non-existent slots to be
+// OBSOLETE * specified. (Slot numbers stored are negative,
+// OBSOLETE * and the magnitude is one greater than the actual
+// OBSOLETE * slot index. (Since 0 is reserved))
+// OBSOLETE */
+// OBSOLETE int
+// OBSOLETE mach_thread_parse_id (char *arg)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE if (arg == 0)
+// OBSOLETE error ("thread id expected");
+// OBSOLETE mid = parse_thread_id (arg, 0, 1);
+// OBSOLETE
+// OBSOLETE return mid;
+// OBSOLETE }
+// OBSOLETE #endif /* THREAD_PARSE_ID */
+// OBSOLETE
+// OBSOLETE #ifdef THREAD_OUTPUT_ID
+// OBSOLETE char *
+// OBSOLETE mach_thread_output_id (int mid)
+// OBSOLETE {
+// OBSOLETE static char foobar[20];
+// OBSOLETE
+// OBSOLETE if (mid > 0)
+// OBSOLETE sprintf (foobar, "mid %d", mid);
+// OBSOLETE else if (mid < 0)
+// OBSOLETE sprintf (foobar, "@%d", -(mid + 1));
+// OBSOLETE else
+// OBSOLETE sprintf (foobar, "*any thread*");
+// OBSOLETE
+// OBSOLETE return foobar;
+// OBSOLETE }
+// OBSOLETE #endif /* THREAD_OUTPUT_ID */
+// OBSOLETE
+// OBSOLETE /* Called with hook PREPARE_TO_PROCEED() from infrun.c.
+// OBSOLETE
+// OBSOLETE * If we have switched threads and stopped at breakpoint return 1 otherwise 0.
+// OBSOLETE *
+// OBSOLETE * if SELECT_IT is nonzero, reselect the thread that was active when
+// OBSOLETE * we stopped at a breakpoint.
+// OBSOLETE *
+// OBSOLETE * Note that this implementation is potentially redundant now that
+// OBSOLETE * default_prepare_to_proceed() has been added.
+// OBSOLETE *
+// OBSOLETE * FIXME This may not support switching threads after Ctrl-C
+// OBSOLETE * correctly. The default implementation does support this.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE mach3_prepare_to_proceed (int select_it)
+// OBSOLETE {
+// OBSOLETE if (stop_thread &&
+// OBSOLETE stop_thread != current_thread &&
+// OBSOLETE stop_exception == EXC_BREAKPOINT)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE if (!select_it)
+// OBSOLETE return 1;
+// OBSOLETE
+// OBSOLETE mid = switch_to_thread (stop_thread);
+// OBSOLETE
+// OBSOLETE return 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* this stuff here is an upcall via libmach/excServer.c
+// OBSOLETE and mach_really_wait which does the actual upcall.
+// OBSOLETE
+// OBSOLETE The code will pass the exception to the inferior if:
+// OBSOLETE
+// OBSOLETE - The task that signaled is not the inferior task
+// OBSOLETE (e.g. when debugging another debugger)
+// OBSOLETE
+// OBSOLETE - The user has explicitely requested to pass on the exceptions.
+// OBSOLETE (e.g to the default unix exception handler, which maps
+// OBSOLETE exceptions to signals, or the user has her own exception handler)
+// OBSOLETE
+// OBSOLETE - If the thread that signaled is being single-stepped and it
+// OBSOLETE has set it's own exception port and the exception is not
+// OBSOLETE EXC_BREAKPOINT. (Maybe this is not desirable?)
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE kern_return_t
+// OBSOLETE catch_exception_raise (mach_port_t port, thread_t thread, task_t task,
+// OBSOLETE int exception, int code, int subcode)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE boolean_t signal_thread;
+// OBSOLETE int mid = map_port_name_to_mid (thread, MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (thread))
+// OBSOLETE {
+// OBSOLETE /* If the exception was sent and thread dies before we
+// OBSOLETE receive it, THREAD will be MACH_PORT_DEAD
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE current_thread = thread = MACH_PORT_NULL;
+// OBSOLETE error ("Received exception from nonexistent thread");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Check if the task died in transit.
+// OBSOLETE * @@ Isn't the thread also invalid in such case?
+// OBSOLETE */
+// OBSOLETE if (!MACH_PORT_VALID (task))
+// OBSOLETE {
+// OBSOLETE current_thread = thread = MACH_PORT_NULL;
+// OBSOLETE error ("Received exception from nonexistent task");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (exception < 0 || exception > MAX_EXCEPTION)
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "catch_exception_raise: unknown exception code %d thread %d",
+// OBSOLETE exception,
+// OBSOLETE mid);
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (inferior_task))
+// OBSOLETE error ("got an exception, but inferior_task is null or dead");
+// OBSOLETE
+// OBSOLETE stop_exception = exception;
+// OBSOLETE stop_code = code;
+// OBSOLETE stop_subcode = subcode;
+// OBSOLETE stop_thread = thread;
+// OBSOLETE
+// OBSOLETE signal_thread = exception != EXC_BREAKPOINT &&
+// OBSOLETE port == singlestepped_thread_port &&
+// OBSOLETE MACH_PORT_VALID (thread_saved_exception_port);
+// OBSOLETE
+// OBSOLETE /* If it was not our inferior or if we want to forward
+// OBSOLETE * the exception to the inferior's handler, do it here
+// OBSOLETE *
+// OBSOLETE * Note: If you have forwarded EXC_BREAKPOINT I trust you know why.
+// OBSOLETE */
+// OBSOLETE if (task != inferior_task ||
+// OBSOLETE signal_thread ||
+// OBSOLETE exception_map[exception].forward)
+// OBSOLETE {
+// OBSOLETE mach_port_t eport = inferior_old_exception_port;
+// OBSOLETE
+// OBSOLETE if (signal_thread)
+// OBSOLETE {
+// OBSOLETE /*
+// OBSOLETE GDB now forwards the exeption to thread's original handler,
+// OBSOLETE since the user propably knows what he is doing.
+// OBSOLETE Give a message, though.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE mach3_exception_actions ((WAITTYPE *) NULL, TRUE, "Thread");
+// OBSOLETE eport = thread_saved_exception_port;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Send the exception to the original handler */
+// OBSOLETE ret = exception_raise (eport,
+// OBSOLETE thread,
+// OBSOLETE task,
+// OBSOLETE exception,
+// OBSOLETE code,
+// OBSOLETE subcode);
+// OBSOLETE
+// OBSOLETE (void) mach_port_deallocate (mach_task_self (), task);
+// OBSOLETE (void) mach_port_deallocate (mach_task_self (), thread);
+// OBSOLETE
+// OBSOLETE /* If we come here, we don't want to trace any more, since we
+// OBSOLETE * will never stop for tracing anyway.
+// OBSOLETE */
+// OBSOLETE discard_single_step (thread);
+// OBSOLETE
+// OBSOLETE /* Do not stop the inferior */
+// OBSOLETE return ret;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Now gdb handles the exception */
+// OBSOLETE stopped_in_exception = TRUE;
+// OBSOLETE
+// OBSOLETE ret = task_suspend (task);
+// OBSOLETE CHK ("Error suspending inferior after exception", ret);
+// OBSOLETE
+// OBSOLETE must_suspend_thread = 0;
+// OBSOLETE
+// OBSOLETE if (current_thread != thread)
+// OBSOLETE {
+// OBSOLETE if (MACH_PORT_VALID (singlestepped_thread_port))
+// OBSOLETE /* Cleanup discards single stepping */
+// OBSOLETE error ("Exception from thread %d while singlestepping thread %d",
+// OBSOLETE mid,
+// OBSOLETE map_port_name_to_mid (current_thread, MACH_TYPE_THREAD));
+// OBSOLETE
+// OBSOLETE /* Then select the thread that caused the exception */
+// OBSOLETE if (select_thread (inferior_task, mid, 0) != KERN_SUCCESS)
+// OBSOLETE error ("Could not select thread %d causing exception", mid);
+// OBSOLETE else
+// OBSOLETE warning ("Gdb selected thread %d", mid);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* If we receive an exception that is not breakpoint
+// OBSOLETE * exception, we interrupt the single step and return to
+// OBSOLETE * debugger. Trace condition is cleared.
+// OBSOLETE */
+// OBSOLETE if (MACH_PORT_VALID (singlestepped_thread_port))
+// OBSOLETE {
+// OBSOLETE if (stop_exception != EXC_BREAKPOINT)
+// OBSOLETE warning ("Single step interrupted by exception");
+// OBSOLETE else if (port == singlestepped_thread_port)
+// OBSOLETE {
+// OBSOLETE /* Single step exception occurred, remove trace bit
+// OBSOLETE * and return to gdb.
+// OBSOLETE */
+// OBSOLETE if (!MACH_PORT_VALID (current_thread))
+// OBSOLETE error ("Single stepped thread is not valid");
+// OBSOLETE
+// OBSOLETE /* Resume threads, but leave the task suspended */
+// OBSOLETE resume_all_threads (0);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE warning ("Breakpoint while single stepping?");
+// OBSOLETE
+// OBSOLETE discard_single_step (current_thread);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE (void) mach_port_deallocate (mach_task_self (), task);
+// OBSOLETE (void) mach_port_deallocate (mach_task_self (), thread);
+// OBSOLETE
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE int
+// OBSOLETE port_valid (mach_port_t port, int mask)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE mach_port_type_t type;
+// OBSOLETE
+// OBSOLETE ret = mach_port_type (mach_task_self (),
+// OBSOLETE port,
+// OBSOLETE &type);
+// OBSOLETE if (ret != KERN_SUCCESS || (type & mask) != mask)
+// OBSOLETE return 0;
+// OBSOLETE return 1;
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* @@ No vm read cache implemented yet */
+// OBSOLETE boolean_t vm_read_cache_valid = FALSE;
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Read inferior task's LEN bytes from ADDR and copy it to MYADDR
+// OBSOLETE * in gdb's address space.
+// OBSOLETE *
+// OBSOLETE * Return 0 on failure; number of bytes read otherwise.
+// OBSOLETE */
+// OBSOLETE int
+// OBSOLETE mach3_read_inferior (CORE_ADDR addr, char *myaddr, int length)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE vm_address_t low_address = (vm_address_t) trunc_page (addr);
+// OBSOLETE vm_size_t aligned_length =
+// OBSOLETE (vm_size_t) round_page (addr + length) - low_address;
+// OBSOLETE pointer_t copied_memory;
+// OBSOLETE int copy_count;
+// OBSOLETE
+// OBSOLETE /* Get memory from inferior with page aligned addresses */
+// OBSOLETE ret = vm_read (inferior_task,
+// OBSOLETE low_address,
+// OBSOLETE aligned_length,
+// OBSOLETE &copied_memory,
+// OBSOLETE ©_count);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE /* the problem is that the inferior might be killed for whatever reason
+// OBSOLETE * before we go to mach_really_wait. This is one place that ought to
+// OBSOLETE * catch many of those errors.
+// OBSOLETE * @@ A better fix would be to make all external events to GDB
+// OBSOLETE * to arrive via a SINGLE port set. (Including user input!)
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE if (!port_valid (inferior_task, MACH_PORT_TYPE_SEND))
+// OBSOLETE {
+// OBSOLETE m3_kill_inferior ();
+// OBSOLETE error ("Inferior killed (task port invalid)");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE #ifdef OSF
+// OBSOLETE extern int errno;
+// OBSOLETE /* valprint.c gives nicer format if this does not
+// OBSOLETE screw it. Eamonn seems to like this, so I enable
+// OBSOLETE it if OSF is defined...
+// OBSOLETE */
+// OBSOLETE warning ("[read inferior %x failed: %s]",
+// OBSOLETE addr, mach_error_string (ret));
+// OBSOLETE errno = 0;
+// OBSOLETE #endif
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE memcpy (myaddr, (char *) addr - low_address + copied_memory, length);
+// OBSOLETE
+// OBSOLETE ret = vm_deallocate (mach_task_self (),
+// OBSOLETE copied_memory,
+// OBSOLETE copy_count);
+// OBSOLETE CHK ("mach3_read_inferior vm_deallocate failed", ret);
+// OBSOLETE
+// OBSOLETE return length;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #define CHK_GOTO_OUT(str,ret) \
+// OBSOLETE do if (ret != KERN_SUCCESS) { errstr = #str; goto out; } while(0)
+// OBSOLETE
+// OBSOLETE struct vm_region_list
+// OBSOLETE {
+// OBSOLETE struct vm_region_list *next;
+// OBSOLETE vm_prot_t protection;
+// OBSOLETE vm_address_t start;
+// OBSOLETE vm_size_t length;
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE struct obstack region_obstack;
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Write inferior task's LEN bytes from ADDR and copy it to MYADDR
+// OBSOLETE * in gdb's address space.
+// OBSOLETE */
+// OBSOLETE int
+// OBSOLETE mach3_write_inferior (CORE_ADDR addr, char *myaddr, int length)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE vm_address_t low_address = (vm_address_t) trunc_page (addr);
+// OBSOLETE vm_size_t aligned_length =
+// OBSOLETE (vm_size_t) round_page (addr + length) - low_address;
+// OBSOLETE pointer_t copied_memory;
+// OBSOLETE int copy_count;
+// OBSOLETE int deallocate = 0;
+// OBSOLETE
+// OBSOLETE char *errstr = "Bug in mach3_write_inferior";
+// OBSOLETE
+// OBSOLETE struct vm_region_list *region_element;
+// OBSOLETE struct vm_region_list *region_head = (struct vm_region_list *) NULL;
+// OBSOLETE
+// OBSOLETE /* Get memory from inferior with page aligned addresses */
+// OBSOLETE ret = vm_read (inferior_task,
+// OBSOLETE low_address,
+// OBSOLETE aligned_length,
+// OBSOLETE &copied_memory,
+// OBSOLETE ©_count);
+// OBSOLETE CHK_GOTO_OUT ("mach3_write_inferior vm_read failed", ret);
+// OBSOLETE
+// OBSOLETE deallocate++;
+// OBSOLETE
+// OBSOLETE memcpy ((char *) addr - low_address + copied_memory, myaddr, length);
+// OBSOLETE
+// OBSOLETE obstack_init (®ion_obstack);
+// OBSOLETE
+// OBSOLETE /* Do writes atomically.
+// OBSOLETE * First check for holes and unwritable memory.
+// OBSOLETE */
+// OBSOLETE {
+// OBSOLETE vm_size_t remaining_length = aligned_length;
+// OBSOLETE vm_address_t region_address = low_address;
+// OBSOLETE
+// OBSOLETE struct vm_region_list *scan;
+// OBSOLETE
+// OBSOLETE while (region_address < low_address + aligned_length)
+// OBSOLETE {
+// OBSOLETE vm_prot_t protection;
+// OBSOLETE vm_prot_t max_protection;
+// OBSOLETE vm_inherit_t inheritance;
+// OBSOLETE boolean_t shared;
+// OBSOLETE mach_port_t object_name;
+// OBSOLETE vm_offset_t offset;
+// OBSOLETE vm_size_t region_length = remaining_length;
+// OBSOLETE vm_address_t old_address = region_address;
+// OBSOLETE
+// OBSOLETE ret = vm_region (inferior_task,
+// OBSOLETE ®ion_address,
+// OBSOLETE ®ion_length,
+// OBSOLETE &protection,
+// OBSOLETE &max_protection,
+// OBSOLETE &inheritance,
+// OBSOLETE &shared,
+// OBSOLETE &object_name,
+// OBSOLETE &offset);
+// OBSOLETE CHK_GOTO_OUT ("vm_region failed", ret);
+// OBSOLETE
+// OBSOLETE /* Check for holes in memory */
+// OBSOLETE if (old_address != region_address)
+// OBSOLETE {
+// OBSOLETE warning ("No memory at 0x%x. Nothing written",
+// OBSOLETE old_address);
+// OBSOLETE ret = KERN_SUCCESS;
+// OBSOLETE length = 0;
+// OBSOLETE goto out;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!(max_protection & VM_PROT_WRITE))
+// OBSOLETE {
+// OBSOLETE warning ("Memory at address 0x%x is unwritable. Nothing written",
+// OBSOLETE old_address);
+// OBSOLETE ret = KERN_SUCCESS;
+// OBSOLETE length = 0;
+// OBSOLETE goto out;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Chain the regions for later use */
+// OBSOLETE region_element =
+// OBSOLETE (struct vm_region_list *)
+// OBSOLETE obstack_alloc (®ion_obstack, sizeof (struct vm_region_list));
+// OBSOLETE
+// OBSOLETE region_element->protection = protection;
+// OBSOLETE region_element->start = region_address;
+// OBSOLETE region_element->length = region_length;
+// OBSOLETE
+// OBSOLETE /* Chain the regions along with protections */
+// OBSOLETE region_element->next = region_head;
+// OBSOLETE region_head = region_element;
+// OBSOLETE
+// OBSOLETE region_address += region_length;
+// OBSOLETE remaining_length = remaining_length - region_length;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* If things fail after this, we give up.
+// OBSOLETE * Somebody is messing up inferior_task's mappings.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE /* Enable writes to the chained vm regions */
+// OBSOLETE for (scan = region_head; scan; scan = scan->next)
+// OBSOLETE {
+// OBSOLETE boolean_t protection_changed = FALSE;
+// OBSOLETE
+// OBSOLETE if (!(scan->protection & VM_PROT_WRITE))
+// OBSOLETE {
+// OBSOLETE ret = vm_protect (inferior_task,
+// OBSOLETE scan->start,
+// OBSOLETE scan->length,
+// OBSOLETE FALSE,
+// OBSOLETE scan->protection | VM_PROT_WRITE);
+// OBSOLETE CHK_GOTO_OUT ("vm_protect: enable write failed", ret);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = vm_write (inferior_task,
+// OBSOLETE low_address,
+// OBSOLETE copied_memory,
+// OBSOLETE aligned_length);
+// OBSOLETE CHK_GOTO_OUT ("vm_write failed", ret);
+// OBSOLETE
+// OBSOLETE /* Set up the original region protections, if they were changed */
+// OBSOLETE for (scan = region_head; scan; scan = scan->next)
+// OBSOLETE {
+// OBSOLETE boolean_t protection_changed = FALSE;
+// OBSOLETE
+// OBSOLETE if (!(scan->protection & VM_PROT_WRITE))
+// OBSOLETE {
+// OBSOLETE ret = vm_protect (inferior_task,
+// OBSOLETE scan->start,
+// OBSOLETE scan->length,
+// OBSOLETE FALSE,
+// OBSOLETE scan->protection);
+// OBSOLETE CHK_GOTO_OUT ("vm_protect: enable write failed", ret);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE out:
+// OBSOLETE if (deallocate)
+// OBSOLETE {
+// OBSOLETE obstack_free (®ion_obstack, 0);
+// OBSOLETE
+// OBSOLETE (void) vm_deallocate (mach_task_self (),
+// OBSOLETE copied_memory,
+// OBSOLETE copy_count);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("%s %s", errstr, mach_error_string (ret));
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return length;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Return 0 on failure, number of bytes handled otherwise. TARGET is
+// OBSOLETE ignored. */
+// OBSOLETE static int
+// OBSOLETE m3_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write,
+// OBSOLETE struct target_ops *target)
+// OBSOLETE {
+// OBSOLETE int result;
+// OBSOLETE
+// OBSOLETE if (write)
+// OBSOLETE result = mach3_write_inferior (memaddr, myaddr, len);
+// OBSOLETE else
+// OBSOLETE result = mach3_read_inferior (memaddr, myaddr, len);
+// OBSOLETE
+// OBSOLETE return result;
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE translate_state (int state)
+// OBSOLETE {
+// OBSOLETE switch (state)
+// OBSOLETE {
+// OBSOLETE case TH_STATE_RUNNING:
+// OBSOLETE return ("R");
+// OBSOLETE case TH_STATE_STOPPED:
+// OBSOLETE return ("S");
+// OBSOLETE case TH_STATE_WAITING:
+// OBSOLETE return ("W");
+// OBSOLETE case TH_STATE_UNINTERRUPTIBLE:
+// OBSOLETE return ("U");
+// OBSOLETE case TH_STATE_HALTED:
+// OBSOLETE return ("H");
+// OBSOLETE default:
+// OBSOLETE return ("?");
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE translate_cstate (int state)
+// OBSOLETE {
+// OBSOLETE switch (state)
+// OBSOLETE {
+// OBSOLETE case CPROC_RUNNING:
+// OBSOLETE return "R";
+// OBSOLETE case CPROC_SWITCHING:
+// OBSOLETE return "S";
+// OBSOLETE case CPROC_BLOCKED:
+// OBSOLETE return "B";
+// OBSOLETE case CPROC_CONDWAIT:
+// OBSOLETE return "C";
+// OBSOLETE case CPROC_CONDWAIT | CPROC_SWITCHING:
+// OBSOLETE return "CS";
+// OBSOLETE default:
+// OBSOLETE return "?";
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* type == MACH_MSG_TYPE_COPY_SEND || type == MACH_MSG_TYPE_MAKE_SEND */
+// OBSOLETE
+// OBSOLETE mach_port_t /* no mach_port_name_t found in include files. */
+// OBSOLETE map_inferior_port_name (mach_port_t inferior_name, mach_msg_type_name_t type)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE mach_msg_type_name_t acquired;
+// OBSOLETE mach_port_t iport;
+// OBSOLETE
+// OBSOLETE ret = mach_port_extract_right (inferior_task,
+// OBSOLETE inferior_name,
+// OBSOLETE type,
+// OBSOLETE &iport,
+// OBSOLETE &acquired);
+// OBSOLETE CHK ("mach_port_extract_right (map_inferior_port_name)", ret);
+// OBSOLETE
+// OBSOLETE if (acquired != MACH_MSG_TYPE_PORT_SEND)
+// OBSOLETE error ("Incorrect right extracted, (map_inferior_port_name)");
+// OBSOLETE
+// OBSOLETE ret = mach_port_deallocate (mach_task_self (),
+// OBSOLETE iport);
+// OBSOLETE CHK ("Deallocating mapped port (map_inferior_port_name)", ret);
+// OBSOLETE
+// OBSOLETE return iport;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Naming convention:
+// OBSOLETE * Always return user defined name if found.
+// OBSOLETE * _K == A kernel thread with no matching CPROC
+// OBSOLETE * _C == A cproc with no current cthread
+// OBSOLETE * _t == A cthread with no user defined name
+// OBSOLETE *
+// OBSOLETE * The digits that follow the _names are the SLOT number of the
+// OBSOLETE * kernel thread if there is such a thing, otherwise just a negation
+// OBSOLETE * of the sequential number of such cprocs.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static char buf[7];
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE get_thread_name (gdb_thread_t one_cproc, int id)
+// OBSOLETE {
+// OBSOLETE if (one_cproc)
+// OBSOLETE if (one_cproc->cthread == NULL)
+// OBSOLETE {
+// OBSOLETE /* cproc not mapped to any cthread */
+// OBSOLETE sprintf (buf, "_C%d", id);
+// OBSOLETE }
+// OBSOLETE else if (!one_cproc->cthread->name)
+// OBSOLETE {
+// OBSOLETE /* cproc and cthread, but no name */
+// OBSOLETE sprintf (buf, "_t%d", id);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE return (char *) (one_cproc->cthread->name);
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE if (id < 0)
+// OBSOLETE warning ("Inconsistency in thread name id %d", id);
+// OBSOLETE
+// OBSOLETE /* Kernel thread without cproc */
+// OBSOLETE sprintf (buf, "_K%d", id);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return buf;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE fetch_thread_info (mach_port_t task, gdb_thread_t *mthreads_out)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE thread_array_t th_table;
+// OBSOLETE int th_count;
+// OBSOLETE gdb_thread_t mthreads = NULL;
+// OBSOLETE int index;
+// OBSOLETE
+// OBSOLETE ret = task_threads (task, &th_table, &th_count);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Error getting inferior's thread list:%s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE m3_kill_inferior ();
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE mthreads = (gdb_thread_t)
+// OBSOLETE obstack_alloc
+// OBSOLETE (cproc_obstack,
+// OBSOLETE th_count * sizeof (struct gdb_thread));
+// OBSOLETE
+// OBSOLETE for (index = 0; index < th_count; index++)
+// OBSOLETE {
+// OBSOLETE thread_t saved_thread = MACH_PORT_NULL;
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE if (must_suspend_thread)
+// OBSOLETE setup_thread (th_table[index], 1);
+// OBSOLETE
+// OBSOLETE if (th_table[index] != current_thread)
+// OBSOLETE {
+// OBSOLETE saved_thread = current_thread;
+// OBSOLETE
+// OBSOLETE mid = switch_to_thread (th_table[index]);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE mthreads[index].name = th_table[index];
+// OBSOLETE mthreads[index].cproc = NULL; /* map_cprocs_to_kernel_threads() */
+// OBSOLETE mthreads[index].in_emulator = FALSE;
+// OBSOLETE mthreads[index].slotid = index;
+// OBSOLETE
+// OBSOLETE mthreads[index].sp = read_register (SP_REGNUM);
+// OBSOLETE mthreads[index].fp = read_register (FP_REGNUM);
+// OBSOLETE mthreads[index].pc = read_pc ();
+// OBSOLETE
+// OBSOLETE if (MACH_PORT_VALID (saved_thread))
+// OBSOLETE mid = switch_to_thread (saved_thread);
+// OBSOLETE
+// OBSOLETE if (must_suspend_thread)
+// OBSOLETE setup_thread (th_table[index], 0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE consume_send_rights (th_table, th_count);
+// OBSOLETE ret = vm_deallocate (mach_task_self (), (vm_address_t) th_table,
+// OBSOLETE (th_count * sizeof (mach_port_t)));
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Error trying to deallocate thread list : %s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE *mthreads_out = mthreads;
+// OBSOLETE
+// OBSOLETE return th_count;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Current emulator always saves the USP on top of
+// OBSOLETE * emulator stack below struct emul_stack_top stuff.
+// OBSOLETE */
+// OBSOLETE CORE_ADDR
+// OBSOLETE fetch_usp_from_emulator_stack (CORE_ADDR sp)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR stack_pointer;
+// OBSOLETE
+// OBSOLETE sp = (sp & ~(EMULATOR_STACK_SIZE - 1)) +
+// OBSOLETE EMULATOR_STACK_SIZE - sizeof (struct emul_stack_top);
+// OBSOLETE
+// OBSOLETE if (mach3_read_inferior (sp,
+// OBSOLETE &stack_pointer,
+// OBSOLETE sizeof (CORE_ADDR)) != sizeof (CORE_ADDR))
+// OBSOLETE {
+// OBSOLETE warning ("Can't read user sp from emulator stack address 0x%x", sp);
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return stack_pointer;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #ifdef MK67
+// OBSOLETE
+// OBSOLETE /* get_emulation_vector() interface was changed after mk67 */
+// OBSOLETE #define EMUL_VECTOR_COUNT 400 /* Value does not matter too much */
+// OBSOLETE
+// OBSOLETE #endif /* MK67 */
+// OBSOLETE
+// OBSOLETE /* Check if the emulator exists at task's address space.
+// OBSOLETE */
+// OBSOLETE boolean_t
+// OBSOLETE have_emulator_p (task_t task)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE #ifndef EMUL_VECTOR_COUNT
+// OBSOLETE vm_offset_t *emulation_vector;
+// OBSOLETE int n;
+// OBSOLETE #else
+// OBSOLETE vm_offset_t emulation_vector[EMUL_VECTOR_COUNT];
+// OBSOLETE int n = EMUL_VECTOR_COUNT;
+// OBSOLETE #endif
+// OBSOLETE int i;
+// OBSOLETE int vector_start;
+// OBSOLETE
+// OBSOLETE ret = task_get_emulation_vector (task,
+// OBSOLETE &vector_start,
+// OBSOLETE #ifndef EMUL_VECTOR_COUNT
+// OBSOLETE &emulation_vector,
+// OBSOLETE #else
+// OBSOLETE emulation_vector,
+// OBSOLETE #endif
+// OBSOLETE &n);
+// OBSOLETE CHK ("task_get_emulation_vector", ret);
+// OBSOLETE xx_debug ("%d vectors from %d at 0x%08x\n",
+// OBSOLETE n, vector_start, emulation_vector);
+// OBSOLETE
+// OBSOLETE for (i = 0; i < n; i++)
+// OBSOLETE {
+// OBSOLETE vm_offset_t entry = emulation_vector[i];
+// OBSOLETE
+// OBSOLETE if (EMULATOR_BASE <= entry && entry <= EMULATOR_END)
+// OBSOLETE return TRUE;
+// OBSOLETE else if (entry)
+// OBSOLETE {
+// OBSOLETE static boolean_t informed = FALSE;
+// OBSOLETE if (!informed)
+// OBSOLETE {
+// OBSOLETE warning ("Emulation vector address 0x08%x outside emulator space",
+// OBSOLETE entry);
+// OBSOLETE informed = TRUE;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE return FALSE;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Map cprocs to kernel threads and vice versa. */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE map_cprocs_to_kernel_threads (gdb_thread_t cprocs, gdb_thread_t mthreads,
+// OBSOLETE int thread_count)
+// OBSOLETE {
+// OBSOLETE int index;
+// OBSOLETE gdb_thread_t scan;
+// OBSOLETE boolean_t all_mapped = TRUE;
+// OBSOLETE LONGEST stack_base;
+// OBSOLETE LONGEST stack_size;
+// OBSOLETE
+// OBSOLETE for (scan = cprocs; scan; scan = scan->next)
+// OBSOLETE {
+// OBSOLETE /* Default to: no kernel thread for this cproc */
+// OBSOLETE scan->reverse_map = -1;
+// OBSOLETE
+// OBSOLETE /* Check if the cproc is found by its stack */
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE {
+// OBSOLETE stack_base =
+// OBSOLETE extract_signed_integer (scan->raw_cproc + CPROC_BASE_OFFSET,
+// OBSOLETE CPROC_BASE_SIZE);
+// OBSOLETE stack_size =
+// OBSOLETE extract_signed_integer (scan->raw_cproc + CPROC_SIZE_OFFSET,
+// OBSOLETE CPROC_SIZE_SIZE);
+// OBSOLETE if ((mthreads + index)->sp > stack_base &&
+// OBSOLETE (mthreads + index)->sp <= stack_base + stack_size)
+// OBSOLETE {
+// OBSOLETE (mthreads + index)->cproc = scan;
+// OBSOLETE scan->reverse_map = index;
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE all_mapped &= (scan->reverse_map != -1);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Check for threads that are currently in the emulator.
+// OBSOLETE * If so, they have a different stack, and the still unmapped
+// OBSOLETE * cprocs may well get mapped to these threads.
+// OBSOLETE *
+// OBSOLETE * If:
+// OBSOLETE * - cproc stack does not match any kernel thread stack pointer
+// OBSOLETE * - there is at least one extra kernel thread
+// OBSOLETE * that has no cproc mapped above.
+// OBSOLETE * - some kernel thread stack pointer points to emulator space
+// OBSOLETE * then we find the user stack pointer saved in the emulator
+// OBSOLETE * stack, and try to map that to the cprocs.
+// OBSOLETE *
+// OBSOLETE * Also set in_emulator for kernel threads.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE if (emulator_present)
+// OBSOLETE {
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR emul_sp;
+// OBSOLETE CORE_ADDR usp;
+// OBSOLETE
+// OBSOLETE gdb_thread_t mthread = (mthreads + index);
+// OBSOLETE emul_sp = mthread->sp;
+// OBSOLETE
+// OBSOLETE if (mthread->cproc == NULL &&
+// OBSOLETE EMULATOR_BASE <= emul_sp && emul_sp <= EMULATOR_END)
+// OBSOLETE {
+// OBSOLETE mthread->in_emulator = emulator_present;
+// OBSOLETE
+// OBSOLETE if (!all_mapped && cprocs)
+// OBSOLETE {
+// OBSOLETE usp = fetch_usp_from_emulator_stack (emul_sp);
+// OBSOLETE
+// OBSOLETE /* @@ Could be more accurate */
+// OBSOLETE if (!usp)
+// OBSOLETE error ("Zero stack pointer read from emulator?");
+// OBSOLETE
+// OBSOLETE /* Try to match this stack pointer to the cprocs that
+// OBSOLETE * don't yet have a kernel thread.
+// OBSOLETE */
+// OBSOLETE for (scan = cprocs; scan; scan = scan->next)
+// OBSOLETE {
+// OBSOLETE
+// OBSOLETE /* Check is this unmapped CPROC stack contains
+// OBSOLETE * the user stack pointer saved in the
+// OBSOLETE * emulator.
+// OBSOLETE */
+// OBSOLETE if (scan->reverse_map == -1)
+// OBSOLETE {
+// OBSOLETE stack_base =
+// OBSOLETE extract_signed_integer
+// OBSOLETE (scan->raw_cproc + CPROC_BASE_OFFSET,
+// OBSOLETE CPROC_BASE_SIZE);
+// OBSOLETE stack_size =
+// OBSOLETE extract_signed_integer
+// OBSOLETE (scan->raw_cproc + CPROC_SIZE_OFFSET,
+// OBSOLETE CPROC_SIZE_SIZE);
+// OBSOLETE if (usp > stack_base &&
+// OBSOLETE usp <= stack_base + stack_size)
+// OBSOLETE {
+// OBSOLETE mthread->cproc = scan;
+// OBSOLETE scan->reverse_map = index;
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /*
+// OBSOLETE * Format of the thread_list command
+// OBSOLETE *
+// OBSOLETE * slot mid sel name emul ks susp cstate wired address
+// OBSOLETE */
+// OBSOLETE #define TL_FORMAT "%-2.2s %5d%c %-10.10s %1.1s%s%-5.5s %-2.2s %-5.5s "
+// OBSOLETE
+// OBSOLETE #define TL_HEADER "\n@ MID Name KState CState Where\n"
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE print_tl_address (struct ui_file *stream, CORE_ADDR pc)
+// OBSOLETE {
+// OBSOLETE if (!lookup_minimal_symbol_by_pc (pc))
+// OBSOLETE fprintf_filtered (stream, local_hex_format (), pc);
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE extern int addressprint;
+// OBSOLETE extern int asm_demangle;
+// OBSOLETE
+// OBSOLETE int store = addressprint;
+// OBSOLETE addressprint = 0;
+// OBSOLETE print_address_symbolic (pc, stream, asm_demangle, "");
+// OBSOLETE addressprint = store;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* For thread names, but also for gdb_message_port external name */
+// OBSOLETE #define MAX_NAME_LEN 50
+// OBSOLETE
+// OBSOLETE /* Returns the address of variable NAME or 0 if not found */
+// OBSOLETE CORE_ADDR
+// OBSOLETE lookup_address_of_variable (char *name)
+// OBSOLETE {
+// OBSOLETE struct symbol *sym;
+// OBSOLETE CORE_ADDR symaddr = 0;
+// OBSOLETE struct minimal_symbol *msymbol;
+// OBSOLETE
+// OBSOLETE sym = lookup_symbol (name,
+// OBSOLETE (struct block *) NULL,
+// OBSOLETE VAR_NAMESPACE,
+// OBSOLETE (int *) NULL,
+// OBSOLETE (struct symtab **) NULL);
+// OBSOLETE
+// OBSOLETE if (sym)
+// OBSOLETE symaddr = SYMBOL_VALUE (sym);
+// OBSOLETE
+// OBSOLETE if (!symaddr)
+// OBSOLETE {
+// OBSOLETE msymbol = lookup_minimal_symbol (name, NULL, NULL);
+// OBSOLETE
+// OBSOLETE if (msymbol && msymbol->type == mst_data)
+// OBSOLETE symaddr = SYMBOL_VALUE_ADDRESS (msymbol);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return symaddr;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static gdb_thread_t
+// OBSOLETE get_cprocs (void)
+// OBSOLETE {
+// OBSOLETE gdb_thread_t cproc_head;
+// OBSOLETE gdb_thread_t cproc_copy;
+// OBSOLETE CORE_ADDR their_cprocs;
+// OBSOLETE char *buf;
+// OBSOLETE char *name;
+// OBSOLETE cthread_t cthread;
+// OBSOLETE CORE_ADDR symaddr;
+// OBSOLETE
+// OBSOLETE buf = alloca (TARGET_PTR_BIT / HOST_CHAR_BIT);
+// OBSOLETE symaddr = lookup_address_of_variable ("cproc_list");
+// OBSOLETE
+// OBSOLETE if (!symaddr)
+// OBSOLETE {
+// OBSOLETE /* cproc_list is not in a file compiled with debugging
+// OBSOLETE symbols, but don't give up yet */
+// OBSOLETE
+// OBSOLETE symaddr = lookup_address_of_variable ("cprocs");
+// OBSOLETE
+// OBSOLETE if (symaddr)
+// OBSOLETE {
+// OBSOLETE static int informed = 0;
+// OBSOLETE if (!informed)
+// OBSOLETE {
+// OBSOLETE informed++;
+// OBSOLETE warning ("Your program is loaded with an old threads library.");
+// OBSOLETE warning ("GDB does not know the old form of threads");
+// OBSOLETE warning ("so things may not work.");
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Stripped or no -lthreads loaded or "cproc_list" is in wrong segment. */
+// OBSOLETE if (!symaddr)
+// OBSOLETE return NULL;
+// OBSOLETE
+// OBSOLETE /* Get the address of the first cproc in the task */
+// OBSOLETE if (!mach3_read_inferior (symaddr,
+// OBSOLETE buf,
+// OBSOLETE TARGET_PTR_BIT / HOST_CHAR_BIT))
+// OBSOLETE error ("Can't read cproc master list at address (0x%x).", symaddr);
+// OBSOLETE their_cprocs = extract_address (buf, TARGET_PTR_BIT / HOST_CHAR_BIT);
+// OBSOLETE
+// OBSOLETE /* Scan the CPROCs in the task.
+// OBSOLETE CPROCs are chained with LIST field, not NEXT field, which
+// OBSOLETE chains mutexes, condition variables and queues */
+// OBSOLETE
+// OBSOLETE cproc_head = NULL;
+// OBSOLETE
+// OBSOLETE while (their_cprocs != (CORE_ADDR) 0)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR cproc_copy_incarnation;
+// OBSOLETE cproc_copy = (gdb_thread_t) obstack_alloc (cproc_obstack,
+// OBSOLETE sizeof (struct gdb_thread));
+// OBSOLETE
+// OBSOLETE if (!mach3_read_inferior (their_cprocs,
+// OBSOLETE &cproc_copy->raw_cproc[0],
+// OBSOLETE CPROC_SIZE))
+// OBSOLETE error ("Can't read next cproc at 0x%x.", their_cprocs);
+// OBSOLETE
+// OBSOLETE their_cprocs =
+// OBSOLETE extract_address (cproc_copy->raw_cproc + CPROC_LIST_OFFSET,
+// OBSOLETE CPROC_LIST_SIZE);
+// OBSOLETE cproc_copy_incarnation =
+// OBSOLETE extract_address (cproc_copy->raw_cproc + CPROC_INCARNATION_OFFSET,
+// OBSOLETE CPROC_INCARNATION_SIZE);
+// OBSOLETE
+// OBSOLETE if (cproc_copy_incarnation == (CORE_ADDR) 0)
+// OBSOLETE cproc_copy->cthread = NULL;
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE /* This CPROC has an attached CTHREAD. Get its name */
+// OBSOLETE cthread = (cthread_t) obstack_alloc (cproc_obstack,
+// OBSOLETE sizeof (struct cthread));
+// OBSOLETE
+// OBSOLETE if (!mach3_read_inferior (cproc_copy_incarnation,
+// OBSOLETE cthread,
+// OBSOLETE sizeof (struct cthread)))
+// OBSOLETE error ("Can't read next thread at 0x%x.",
+// OBSOLETE cproc_copy_incarnation);
+// OBSOLETE
+// OBSOLETE cproc_copy->cthread = cthread;
+// OBSOLETE
+// OBSOLETE if (cthread->name)
+// OBSOLETE {
+// OBSOLETE name = (char *) obstack_alloc (cproc_obstack, MAX_NAME_LEN);
+// OBSOLETE
+// OBSOLETE if (!mach3_read_inferior (cthread->name, name, MAX_NAME_LEN))
+// OBSOLETE error ("Can't read next thread's name at 0x%x.", cthread->name);
+// OBSOLETE
+// OBSOLETE cthread->name = name;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* insert in front */
+// OBSOLETE cproc_copy->next = cproc_head;
+// OBSOLETE cproc_head = cproc_copy;
+// OBSOLETE }
+// OBSOLETE return cproc_head;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #ifndef FETCH_CPROC_STATE
+// OBSOLETE /*
+// OBSOLETE * Check if your machine does not grok the way this routine
+// OBSOLETE * fetches the FP,PC and SP of a cproc that is not
+// OBSOLETE * currently attached to any kernel thread (e.g. its cproc.context
+// OBSOLETE * field points to the place in stack where the context
+// OBSOLETE * is saved).
+// OBSOLETE *
+// OBSOLETE * If it doesn't, define your own routine.
+// OBSOLETE */
+// OBSOLETE #define FETCH_CPROC_STATE(mth) mach3_cproc_state (mth)
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE mach3_cproc_state (gdb_thread_t mthread)
+// OBSOLETE {
+// OBSOLETE int context;
+// OBSOLETE
+// OBSOLETE if (!mthread || !mthread->cproc)
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE context = extract_signed_integer
+// OBSOLETE (mthread->cproc->raw_cproc + CPROC_CONTEXT_OFFSET,
+// OBSOLETE CPROC_CONTEXT_SIZE);
+// OBSOLETE if (context == 0)
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE mthread->sp = context + MACHINE_CPROC_SP_OFFSET;
+// OBSOLETE
+// OBSOLETE if (mach3_read_inferior (context + MACHINE_CPROC_PC_OFFSET,
+// OBSOLETE &mthread->pc,
+// OBSOLETE sizeof (CORE_ADDR)) != sizeof (CORE_ADDR))
+// OBSOLETE {
+// OBSOLETE warning ("Can't read cproc pc from inferior");
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (mach3_read_inferior (context + MACHINE_CPROC_FP_OFFSET,
+// OBSOLETE &mthread->fp,
+// OBSOLETE sizeof (CORE_ADDR)) != sizeof (CORE_ADDR))
+// OBSOLETE {
+// OBSOLETE warning ("Can't read cproc fp from inferior");
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE #endif /* FETCH_CPROC_STATE */
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE thread_list_command (void)
+// OBSOLETE {
+// OBSOLETE thread_basic_info_data_t ths;
+// OBSOLETE int thread_count;
+// OBSOLETE gdb_thread_t cprocs;
+// OBSOLETE gdb_thread_t scan;
+// OBSOLETE int index;
+// OBSOLETE char *name;
+// OBSOLETE char selected;
+// OBSOLETE char *wired;
+// OBSOLETE int infoCnt;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE mach_port_t mid_or_port;
+// OBSOLETE gdb_thread_t their_threads;
+// OBSOLETE gdb_thread_t kthread;
+// OBSOLETE
+// OBSOLETE int neworder = 1;
+// OBSOLETE
+// OBSOLETE char *fmt = "There are %d kernel threads in task %d.\n";
+// OBSOLETE
+// OBSOLETE int tmid = map_port_name_to_mid (inferior_task, MACH_TYPE_TASK);
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE thread_count = fetch_thread_info (inferior_task,
+// OBSOLETE &their_threads);
+// OBSOLETE if (thread_count == -1)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE if (thread_count == 1)
+// OBSOLETE fmt = "There is %d kernel thread in task %d.\n";
+// OBSOLETE
+// OBSOLETE printf_filtered (fmt, thread_count, tmid);
+// OBSOLETE
+// OBSOLETE puts_filtered (TL_HEADER);
+// OBSOLETE
+// OBSOLETE cprocs = get_cprocs ();
+// OBSOLETE
+// OBSOLETE map_cprocs_to_kernel_threads (cprocs, their_threads, thread_count);
+// OBSOLETE
+// OBSOLETE for (scan = cprocs; scan; scan = scan->next)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE char buf[10];
+// OBSOLETE char slot[3];
+// OBSOLETE int cproc_state =
+// OBSOLETE extract_signed_integer
+// OBSOLETE (scan->raw_cproc + CPROC_STATE_OFFSET, CPROC_STATE_SIZE);
+// OBSOLETE
+// OBSOLETE selected = ' ';
+// OBSOLETE
+// OBSOLETE /* a wired cproc? */
+// OBSOLETE wired = (extract_address (scan->raw_cproc + CPROC_WIRED_OFFSET,
+// OBSOLETE CPROC_WIRED_SIZE)
+// OBSOLETE ? "wired" : "");
+// OBSOLETE
+// OBSOLETE if (scan->reverse_map != -1)
+// OBSOLETE kthread = (their_threads + scan->reverse_map);
+// OBSOLETE else
+// OBSOLETE kthread = NULL;
+// OBSOLETE
+// OBSOLETE if (kthread)
+// OBSOLETE {
+// OBSOLETE /* These cprocs have a kernel thread */
+// OBSOLETE
+// OBSOLETE mid = map_port_name_to_mid (kthread->name, MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE infoCnt = THREAD_BASIC_INFO_COUNT;
+// OBSOLETE
+// OBSOLETE ret = thread_info (kthread->name,
+// OBSOLETE THREAD_BASIC_INFO,
+// OBSOLETE (thread_info_t) & ths,
+// OBSOLETE &infoCnt);
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Unable to get basic info on thread %d : %s",
+// OBSOLETE mid,
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE continue;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Who is the first to have more than 100 threads */
+// OBSOLETE sprintf (slot, "%d", kthread->slotid % 100);
+// OBSOLETE
+// OBSOLETE if (kthread->name == current_thread)
+// OBSOLETE selected = '*';
+// OBSOLETE
+// OBSOLETE if (ths.suspend_count)
+// OBSOLETE sprintf (buf, "%d", ths.suspend_count);
+// OBSOLETE else
+// OBSOLETE buf[0] = '\000';
+// OBSOLETE
+// OBSOLETE #if 0
+// OBSOLETE if (ths.flags & TH_FLAGS_SWAPPED)
+// OBSOLETE strcat (buf, "S");
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE if (ths.flags & TH_FLAGS_IDLE)
+// OBSOLETE strcat (buf, "I");
+// OBSOLETE
+// OBSOLETE printf_filtered (TL_FORMAT,
+// OBSOLETE slot,
+// OBSOLETE mid,
+// OBSOLETE selected,
+// OBSOLETE get_thread_name (scan, kthread->slotid),
+// OBSOLETE kthread->in_emulator ? "E" : "",
+// OBSOLETE translate_state (ths.run_state),
+// OBSOLETE buf,
+// OBSOLETE translate_cstate (cproc_state),
+// OBSOLETE wired);
+// OBSOLETE print_tl_address (gdb_stdout, kthread->pc);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE /* These cprocs don't have a kernel thread.
+// OBSOLETE * find out the calling frame with
+// OBSOLETE * FETCH_CPROC_STATE.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE struct gdb_thread state;
+// OBSOLETE
+// OBSOLETE #if 0
+// OBSOLETE /* jtv -> emcmanus: why do you want this here? */
+// OBSOLETE if (scan->incarnation == NULL)
+// OBSOLETE continue; /* EMcM */
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE printf_filtered (TL_FORMAT,
+// OBSOLETE "-",
+// OBSOLETE -neworder, /* Pseudo MID */
+// OBSOLETE selected,
+// OBSOLETE get_thread_name (scan, -neworder),
+// OBSOLETE "",
+// OBSOLETE "-", /* kernel state */
+// OBSOLETE "",
+// OBSOLETE translate_cstate (cproc_state),
+// OBSOLETE "");
+// OBSOLETE state.cproc = scan;
+// OBSOLETE
+// OBSOLETE if (FETCH_CPROC_STATE (&state) == -1)
+// OBSOLETE puts_filtered ("???");
+// OBSOLETE else
+// OBSOLETE print_tl_address (gdb_stdout, state.pc);
+// OBSOLETE
+// OBSOLETE neworder++;
+// OBSOLETE }
+// OBSOLETE puts_filtered ("\n");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Scan for kernel threads without cprocs */
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE {
+// OBSOLETE if (!their_threads[index].cproc)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE char buf[10];
+// OBSOLETE char slot[3];
+// OBSOLETE
+// OBSOLETE mach_port_t name = their_threads[index].name;
+// OBSOLETE
+// OBSOLETE mid = map_port_name_to_mid (name, MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE infoCnt = THREAD_BASIC_INFO_COUNT;
+// OBSOLETE
+// OBSOLETE ret = thread_info (name,
+// OBSOLETE THREAD_BASIC_INFO,
+// OBSOLETE (thread_info_t) & ths,
+// OBSOLETE &infoCnt);
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Unable to get basic info on thread %d : %s",
+// OBSOLETE mid,
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE continue;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE sprintf (slot, "%d", index % 100);
+// OBSOLETE
+// OBSOLETE if (name == current_thread)
+// OBSOLETE selected = '*';
+// OBSOLETE else
+// OBSOLETE selected = ' ';
+// OBSOLETE
+// OBSOLETE if (ths.suspend_count)
+// OBSOLETE sprintf (buf, "%d", ths.suspend_count);
+// OBSOLETE else
+// OBSOLETE buf[0] = '\000';
+// OBSOLETE
+// OBSOLETE #if 0
+// OBSOLETE if (ths.flags & TH_FLAGS_SWAPPED)
+// OBSOLETE strcat (buf, "S");
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE if (ths.flags & TH_FLAGS_IDLE)
+// OBSOLETE strcat (buf, "I");
+// OBSOLETE
+// OBSOLETE printf_filtered (TL_FORMAT,
+// OBSOLETE slot,
+// OBSOLETE mid,
+// OBSOLETE selected,
+// OBSOLETE get_thread_name (NULL, index),
+// OBSOLETE their_threads[index].in_emulator ? "E" : "",
+// OBSOLETE translate_state (ths.run_state),
+// OBSOLETE buf,
+// OBSOLETE "", /* No cproc state */
+// OBSOLETE ""); /* Can't be wired */
+// OBSOLETE print_tl_address (gdb_stdout, their_threads[index].pc);
+// OBSOLETE puts_filtered ("\n");
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE obstack_free (cproc_obstack, 0);
+// OBSOLETE obstack_init (cproc_obstack);
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE void
+// OBSOLETE thread_select_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE thread_array_t thread_list;
+// OBSOLETE int thread_count;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int is_slot = 0;
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE if (!args)
+// OBSOLETE error_no_arg ("MID or @SLOTNUMBER to specify a thread to select");
+// OBSOLETE
+// OBSOLETE while (*args == ' ' || *args == '\t')
+// OBSOLETE args++;
+// OBSOLETE
+// OBSOLETE if (*args == '@')
+// OBSOLETE {
+// OBSOLETE is_slot++;
+// OBSOLETE args++;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE mid = atoi (args);
+// OBSOLETE
+// OBSOLETE if (mid == 0)
+// OBSOLETE if (!is_slot || *args != '0') /* Rudimentary checks */
+// OBSOLETE error ("You must select threads by MID or @SLOTNUMBER");
+// OBSOLETE
+// OBSOLETE if (select_thread (inferior_task, mid, is_slot ? 2 : 1) != KERN_SUCCESS)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE if (from_tty)
+// OBSOLETE printf_filtered ("Thread %d selected\n",
+// OBSOLETE is_slot ? map_port_name_to_mid (current_thread,
+// OBSOLETE MACH_TYPE_THREAD) : mid);
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE thread_trace (mach_port_t thread, boolean_t set)
+// OBSOLETE {
+// OBSOLETE int flavor = TRACE_FLAVOR;
+// OBSOLETE unsigned int stateCnt = TRACE_FLAVOR_SIZE;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE thread_state_data_t state;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (thread))
+// OBSOLETE {
+// OBSOLETE warning ("thread_trace: invalid thread");
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (must_suspend_thread)
+// OBSOLETE setup_thread (thread, 1);
+// OBSOLETE
+// OBSOLETE ret = thread_get_state (thread, flavor, state, &stateCnt);
+// OBSOLETE CHK ("thread_trace: error reading thread state", ret);
+// OBSOLETE
+// OBSOLETE if (set)
+// OBSOLETE {
+// OBSOLETE TRACE_SET (thread, state);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE if (!TRACE_CLEAR (thread, state))
+// OBSOLETE {
+// OBSOLETE if (must_suspend_thread)
+// OBSOLETE setup_thread (thread, 0);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = thread_set_state (thread, flavor, state, stateCnt);
+// OBSOLETE CHK ("thread_trace: error writing thread state", ret);
+// OBSOLETE if (must_suspend_thread)
+// OBSOLETE setup_thread (thread, 0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #ifdef FLUSH_INFERIOR_CACHE
+// OBSOLETE
+// OBSOLETE /* When over-writing code on some machines the I-Cache must be flushed
+// OBSOLETE explicitly, because it is not kept coherent by the lazy hardware.
+// OBSOLETE This definitely includes breakpoints, for instance, or else we
+// OBSOLETE end up looping in mysterious Bpt traps */
+// OBSOLETE
+// OBSOLETE flush_inferior_icache (CORE_ADDR pc, int amount)
+// OBSOLETE {
+// OBSOLETE vm_machine_attribute_val_t flush = MATTR_VAL_ICACHE_FLUSH;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE ret = vm_machine_attribute (inferior_task,
+// OBSOLETE pc,
+// OBSOLETE amount,
+// OBSOLETE MATTR_CACHE,
+// OBSOLETE &flush);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("Error flushing inferior's cache : %s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE }
+// OBSOLETE #endif /* FLUSH_INFERIOR_CACHE */
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE static
+// OBSOLETE suspend_all_threads (int from_tty)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE thread_array_t thread_list;
+// OBSOLETE int thread_count, index;
+// OBSOLETE int infoCnt;
+// OBSOLETE thread_basic_info_data_t th_info;
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE ret = task_threads (inferior_task, &thread_list, &thread_count);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("Could not suspend inferior threads.");
+// OBSOLETE m3_kill_inferior ();
+// OBSOLETE throw_exception (RETURN_ERROR);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE
+// OBSOLETE mid = map_port_name_to_mid (thread_list[index],
+// OBSOLETE MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE ret = thread_suspend (thread_list[index]);
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("Error trying to suspend thread %d : %s",
+// OBSOLETE mid, mach_error_string (ret));
+// OBSOLETE
+// OBSOLETE if (from_tty)
+// OBSOLETE {
+// OBSOLETE infoCnt = THREAD_BASIC_INFO_COUNT;
+// OBSOLETE ret = thread_info (thread_list[index],
+// OBSOLETE THREAD_BASIC_INFO,
+// OBSOLETE (thread_info_t) & th_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("suspend can't get thread info", ret);
+// OBSOLETE
+// OBSOLETE warning ("Thread %d suspend count is %d",
+// OBSOLETE mid, th_info.suspend_count);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE consume_send_rights (thread_list, thread_count);
+// OBSOLETE ret = vm_deallocate (mach_task_self (),
+// OBSOLETE (vm_address_t) thread_list,
+// OBSOLETE (thread_count * sizeof (int)));
+// OBSOLETE CHK ("Error trying to deallocate thread list", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE thread_suspend_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int mid;
+// OBSOLETE mach_port_t saved_thread;
+// OBSOLETE int infoCnt;
+// OBSOLETE thread_basic_info_data_t th_info;
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE if (!strcasecmp (args, "all"))
+// OBSOLETE {
+// OBSOLETE suspend_all_threads (from_tty);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE saved_thread = current_thread;
+// OBSOLETE
+// OBSOLETE mid = parse_thread_id (args, 0, 0);
+// OBSOLETE
+// OBSOLETE if (mid < 0)
+// OBSOLETE error ("You can suspend only existing kernel threads with MID or @SLOTNUMBER");
+// OBSOLETE
+// OBSOLETE if (mid == 0)
+// OBSOLETE mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
+// OBSOLETE else if (select_thread (inferior_task, mid, 0) != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE if (current_thread)
+// OBSOLETE current_thread = saved_thread;
+// OBSOLETE error ("Could not select thread %d", mid);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = thread_suspend (current_thread);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("thread_suspend failed : %s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE
+// OBSOLETE infoCnt = THREAD_BASIC_INFO_COUNT;
+// OBSOLETE ret = thread_info (current_thread,
+// OBSOLETE THREAD_BASIC_INFO,
+// OBSOLETE (thread_info_t) & th_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("suspend can't get thread info", ret);
+// OBSOLETE
+// OBSOLETE warning ("Thread %d suspend count is %d", mid, th_info.suspend_count);
+// OBSOLETE
+// OBSOLETE current_thread = saved_thread;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE resume_all_threads (int from_tty)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE thread_array_t thread_list;
+// OBSOLETE int thread_count, index;
+// OBSOLETE int mid;
+// OBSOLETE int infoCnt;
+// OBSOLETE thread_basic_info_data_t th_info;
+// OBSOLETE
+// OBSOLETE ret = task_threads (inferior_task, &thread_list, &thread_count);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE m3_kill_inferior ();
+// OBSOLETE error ("task_threads", mach_error_string (ret));
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE {
+// OBSOLETE infoCnt = THREAD_BASIC_INFO_COUNT;
+// OBSOLETE ret = thread_info (thread_list[index],
+// OBSOLETE THREAD_BASIC_INFO,
+// OBSOLETE (thread_info_t) & th_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("resume_all can't get thread info", ret);
+// OBSOLETE
+// OBSOLETE mid = map_port_name_to_mid (thread_list[index],
+// OBSOLETE MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE if (!th_info.suspend_count)
+// OBSOLETE {
+// OBSOLETE if (mid != -1 && from_tty)
+// OBSOLETE warning ("Thread %d is not suspended", mid);
+// OBSOLETE continue;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = thread_resume (thread_list[index]);
+// OBSOLETE
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("Error trying to resume thread %d : %s",
+// OBSOLETE mid, mach_error_string (ret));
+// OBSOLETE else if (mid != -1 && from_tty)
+// OBSOLETE warning ("Thread %d suspend count is %d",
+// OBSOLETE mid, --th_info.suspend_count);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE consume_send_rights (thread_list, thread_count);
+// OBSOLETE ret = vm_deallocate (mach_task_self (),
+// OBSOLETE (vm_address_t) thread_list,
+// OBSOLETE (thread_count * sizeof (int)));
+// OBSOLETE CHK ("Error trying to deallocate thread list", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE thread_resume_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE mach_port_t saved_thread;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE thread_basic_info_data_t th_info;
+// OBSOLETE int infoCnt = THREAD_BASIC_INFO_COUNT;
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE if (!strcasecmp (args, "all"))
+// OBSOLETE {
+// OBSOLETE resume_all_threads (from_tty);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE saved_thread = current_thread;
+// OBSOLETE
+// OBSOLETE mid = parse_thread_id (args, 0, 0);
+// OBSOLETE
+// OBSOLETE if (mid < 0)
+// OBSOLETE error ("You can resume only existing kernel threads with MID or @SLOTNUMBER");
+// OBSOLETE
+// OBSOLETE if (mid == 0)
+// OBSOLETE mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
+// OBSOLETE else if (select_thread (inferior_task, mid, 0) != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE if (current_thread)
+// OBSOLETE current_thread = saved_thread;
+// OBSOLETE throw_exception (RETURN_ERROR);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = thread_info (current_thread,
+// OBSOLETE THREAD_BASIC_INFO,
+// OBSOLETE (thread_info_t) & th_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("resume can't get thread info", ret);
+// OBSOLETE
+// OBSOLETE if (!th_info.suspend_count)
+// OBSOLETE {
+// OBSOLETE warning ("Thread %d is not suspended", mid);
+// OBSOLETE goto out;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = thread_resume (current_thread);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("thread_resume failed : %s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE th_info.suspend_count--;
+// OBSOLETE warning ("Thread %d suspend count is %d", mid, th_info.suspend_count);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE out:
+// OBSOLETE current_thread = saved_thread;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE thread_kill_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE int mid;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE int thread_count;
+// OBSOLETE thread_array_t thread_table;
+// OBSOLETE int index;
+// OBSOLETE mach_port_t thread_to_kill = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE if (!args)
+// OBSOLETE error_no_arg ("thread mid to kill from the inferior task");
+// OBSOLETE
+// OBSOLETE mid = parse_thread_id (args, 0, 0);
+// OBSOLETE
+// OBSOLETE if (mid < 0)
+// OBSOLETE error ("You can kill only existing kernel threads with MID or @SLOTNUMBER");
+// OBSOLETE
+// OBSOLETE if (mid)
+// OBSOLETE {
+// OBSOLETE ret = machid_mach_port (mid_server, mid_auth, mid, &thread_to_kill);
+// OBSOLETE CHK ("thread_kill_command: machid_mach_port map failed", ret);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE mid = map_port_name_to_mid (current_thread, MACH_TYPE_THREAD);
+// OBSOLETE
+// OBSOLETE /* Don't allow gdb to kill *any* thread in the system. Use mkill program for that */
+// OBSOLETE ret = task_threads (inferior_task, &thread_table, &thread_count);
+// OBSOLETE CHK ("Error getting inferior's thread list", ret);
+// OBSOLETE
+// OBSOLETE if (thread_to_kill == current_thread)
+// OBSOLETE {
+// OBSOLETE ret = thread_terminate (thread_to_kill);
+// OBSOLETE CHK ("Thread could not be terminated", ret);
+// OBSOLETE
+// OBSOLETE if (select_thread (inferior_task, 0, 1) != KERN_SUCCESS)
+// OBSOLETE warning ("Last thread was killed, use \"kill\" command to kill task");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE if (thread_table[index] == thread_to_kill)
+// OBSOLETE {
+// OBSOLETE ret = thread_terminate (thread_to_kill);
+// OBSOLETE CHK ("Thread could not be terminated", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (thread_count > 1)
+// OBSOLETE consume_send_rights (thread_table, thread_count);
+// OBSOLETE
+// OBSOLETE ret = vm_deallocate (mach_task_self (), (vm_address_t) thread_table,
+// OBSOLETE (thread_count * sizeof (mach_port_t)));
+// OBSOLETE CHK ("Error trying to deallocate thread list", ret);
+// OBSOLETE
+// OBSOLETE warning ("Thread %d killed", mid);
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE /* Task specific commands; add more if you like */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE task_resume_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE task_basic_info_data_t ta_info;
+// OBSOLETE int infoCnt = TASK_BASIC_INFO_COUNT;
+// OBSOLETE int mid = map_port_name_to_mid (inferior_task, MACH_TYPE_TASK);
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE /* Would be trivial to change, but is it desirable? */
+// OBSOLETE if (args)
+// OBSOLETE error ("Currently gdb can resume only it's inferior task");
+// OBSOLETE
+// OBSOLETE ret = task_info (inferior_task,
+// OBSOLETE TASK_BASIC_INFO,
+// OBSOLETE (task_info_t) & ta_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("task_resume_command: task_info failed", ret);
+// OBSOLETE
+// OBSOLETE if (ta_info.suspend_count == 0)
+// OBSOLETE error ("Inferior task %d is not suspended", mid);
+// OBSOLETE else if (ta_info.suspend_count == 1 &&
+// OBSOLETE from_tty &&
+// OBSOLETE !query ("Suspend count is now 1. Do you know what you are doing? "))
+// OBSOLETE error ("Task not resumed");
+// OBSOLETE
+// OBSOLETE ret = task_resume (inferior_task);
+// OBSOLETE CHK ("task_resume_command: task_resume", ret);
+// OBSOLETE
+// OBSOLETE if (ta_info.suspend_count == 1)
+// OBSOLETE {
+// OBSOLETE warning ("Inferior task %d is no longer suspended", mid);
+// OBSOLETE must_suspend_thread = 1;
+// OBSOLETE /* @@ This is not complete: Registers change all the time when not
+// OBSOLETE suspended! */
+// OBSOLETE registers_changed ();
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE warning ("Inferior task %d suspend count is now %d",
+// OBSOLETE mid, ta_info.suspend_count - 1);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE task_suspend_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE task_basic_info_data_t ta_info;
+// OBSOLETE int infoCnt = TASK_BASIC_INFO_COUNT;
+// OBSOLETE int mid = map_port_name_to_mid (inferior_task, MACH_TYPE_TASK);
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE /* Would be trivial to change, but is it desirable? */
+// OBSOLETE if (args)
+// OBSOLETE error ("Currently gdb can suspend only it's inferior task");
+// OBSOLETE
+// OBSOLETE ret = task_suspend (inferior_task);
+// OBSOLETE CHK ("task_suspend_command: task_suspend", ret);
+// OBSOLETE
+// OBSOLETE must_suspend_thread = 0;
+// OBSOLETE
+// OBSOLETE ret = task_info (inferior_task,
+// OBSOLETE TASK_BASIC_INFO,
+// OBSOLETE (task_info_t) & ta_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("task_suspend_command: task_info failed", ret);
+// OBSOLETE
+// OBSOLETE warning ("Inferior task %d suspend count is now %d",
+// OBSOLETE mid, ta_info.suspend_count);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE get_size (int bytes)
+// OBSOLETE {
+// OBSOLETE static char size[30];
+// OBSOLETE int zz = bytes / 1024;
+// OBSOLETE
+// OBSOLETE if (zz / 1024)
+// OBSOLETE sprintf (size, "%-2.1f M", ((float) bytes) / (1024.0 * 1024.0));
+// OBSOLETE else
+// OBSOLETE sprintf (size, "%d K", zz);
+// OBSOLETE
+// OBSOLETE return size;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Does this require the target task to be suspended?? I don't think so. */
+// OBSOLETE void
+// OBSOLETE task_info_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE int mid = -5;
+// OBSOLETE mach_port_t task;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE task_basic_info_data_t ta_info;
+// OBSOLETE int infoCnt = TASK_BASIC_INFO_COUNT;
+// OBSOLETE int page_size = round_page (1);
+// OBSOLETE int thread_count = 0;
+// OBSOLETE
+// OBSOLETE if (MACH_PORT_VALID (inferior_task))
+// OBSOLETE mid = map_port_name_to_mid (inferior_task,
+// OBSOLETE MACH_TYPE_TASK);
+// OBSOLETE
+// OBSOLETE task = inferior_task;
+// OBSOLETE
+// OBSOLETE if (args)
+// OBSOLETE {
+// OBSOLETE int tmid = atoi (args);
+// OBSOLETE
+// OBSOLETE if (tmid <= 0)
+// OBSOLETE error ("Invalid mid %d for task info", tmid);
+// OBSOLETE
+// OBSOLETE if (tmid != mid)
+// OBSOLETE {
+// OBSOLETE mid = tmid;
+// OBSOLETE ret = machid_mach_port (mid_server, mid_auth, tmid, &task);
+// OBSOLETE CHK ("task_info_command: machid_mach_port map failed", ret);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (mid < 0)
+// OBSOLETE error ("You have to give the task MID as an argument");
+// OBSOLETE
+// OBSOLETE ret = task_info (task,
+// OBSOLETE TASK_BASIC_INFO,
+// OBSOLETE (task_info_t) & ta_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("task_info_command: task_info failed", ret);
+// OBSOLETE
+// OBSOLETE printf_filtered ("\nTask info for task %d:\n\n", mid);
+// OBSOLETE printf_filtered (" Suspend count : %d\n", ta_info.suspend_count);
+// OBSOLETE printf_filtered (" Base priority : %d\n", ta_info.base_priority);
+// OBSOLETE printf_filtered (" Virtual size : %s\n", get_size (ta_info.virtual_size));
+// OBSOLETE printf_filtered (" Resident size : %s\n", get_size (ta_info.resident_size));
+// OBSOLETE
+// OBSOLETE {
+// OBSOLETE thread_array_t thread_list;
+// OBSOLETE
+// OBSOLETE ret = task_threads (task, &thread_list, &thread_count);
+// OBSOLETE CHK ("task_info_command: task_threads", ret);
+// OBSOLETE
+// OBSOLETE printf_filtered (" Thread count : %d\n", thread_count);
+// OBSOLETE
+// OBSOLETE consume_send_rights (thread_list, thread_count);
+// OBSOLETE ret = vm_deallocate (mach_task_self (),
+// OBSOLETE (vm_address_t) thread_list,
+// OBSOLETE (thread_count * sizeof (int)));
+// OBSOLETE CHK ("Error trying to deallocate thread list", ret);
+// OBSOLETE }
+// OBSOLETE if (have_emulator_p (task))
+// OBSOLETE printf_filtered (" Emulator at : 0x%x..0x%x\n",
+// OBSOLETE EMULATOR_BASE, EMULATOR_END);
+// OBSOLETE else
+// OBSOLETE printf_filtered (" No emulator.\n");
+// OBSOLETE
+// OBSOLETE if (thread_count && task == inferior_task)
+// OBSOLETE printf_filtered ("\nUse the \"thread list\" command to see the threads\n");
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* You may either FORWARD the exception to the inferior, or KEEP
+// OBSOLETE * it and return to GDB command level.
+// OBSOLETE *
+// OBSOLETE * exception mid [ forward | keep ]
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE exception_command (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE char *scan = args;
+// OBSOLETE int exception;
+// OBSOLETE int len;
+// OBSOLETE
+// OBSOLETE if (!args)
+// OBSOLETE error_no_arg ("exception number action");
+// OBSOLETE
+// OBSOLETE while (*scan == ' ' || *scan == '\t')
+// OBSOLETE scan++;
+// OBSOLETE
+// OBSOLETE if ('0' <= *scan && *scan <= '9')
+// OBSOLETE while ('0' <= *scan && *scan <= '9')
+// OBSOLETE scan++;
+// OBSOLETE else
+// OBSOLETE error ("exception number action");
+// OBSOLETE
+// OBSOLETE exception = atoi (args);
+// OBSOLETE if (exception <= 0 || exception > MAX_EXCEPTION)
+// OBSOLETE error ("Allowed exception numbers are in range 1..%d",
+// OBSOLETE MAX_EXCEPTION);
+// OBSOLETE
+// OBSOLETE if (*scan != ' ' && *scan != '\t')
+// OBSOLETE error ("exception number must be followed by a space");
+// OBSOLETE else
+// OBSOLETE while (*scan == ' ' || *scan == '\t')
+// OBSOLETE scan++;
+// OBSOLETE
+// OBSOLETE args = scan;
+// OBSOLETE len = 0;
+// OBSOLETE while (*scan)
+// OBSOLETE {
+// OBSOLETE len++;
+// OBSOLETE scan++;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!len)
+// OBSOLETE error ("exception number action");
+// OBSOLETE
+// OBSOLETE if (!strncasecmp (args, "forward", len))
+// OBSOLETE exception_map[exception].forward = TRUE;
+// OBSOLETE else if (!strncasecmp (args, "keep", len))
+// OBSOLETE exception_map[exception].forward = FALSE;
+// OBSOLETE else
+// OBSOLETE error ("exception action is either \"keep\" or \"forward\"");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE print_exception_info (int exception)
+// OBSOLETE {
+// OBSOLETE boolean_t forward = exception_map[exception].forward;
+// OBSOLETE
+// OBSOLETE printf_filtered ("%s\t(%d): ", exception_map[exception].name,
+// OBSOLETE exception);
+// OBSOLETE if (!forward)
+// OBSOLETE if (exception_map[exception].sigmap != SIG_UNKNOWN)
+// OBSOLETE printf_filtered ("keep and handle as signal %d\n",
+// OBSOLETE exception_map[exception].sigmap);
+// OBSOLETE else
+// OBSOLETE printf_filtered ("keep and handle as unknown signal %d\n",
+// OBSOLETE exception_map[exception].sigmap);
+// OBSOLETE else
+// OBSOLETE printf_filtered ("forward exception to inferior\n");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE exception_info (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE int exception;
+// OBSOLETE
+// OBSOLETE if (!args)
+// OBSOLETE for (exception = 1; exception <= MAX_EXCEPTION; exception++)
+// OBSOLETE print_exception_info (exception);
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE exception = atoi (args);
+// OBSOLETE
+// OBSOLETE if (exception <= 0 || exception > MAX_EXCEPTION)
+// OBSOLETE error ("Invalid exception number, values from 1 to %d allowed",
+// OBSOLETE MAX_EXCEPTION);
+// OBSOLETE print_exception_info (exception);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* Check for actions for mach exceptions.
+// OBSOLETE */
+// OBSOLETE mach3_exception_actions (WAITTYPE *w, boolean_t force_print_only, char *who)
+// OBSOLETE {
+// OBSOLETE boolean_t force_print = FALSE;
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE if (force_print_only ||
+// OBSOLETE exception_map[stop_exception].sigmap == SIG_UNKNOWN)
+// OBSOLETE force_print = TRUE;
+// OBSOLETE else
+// OBSOLETE WSETSTOP (*w, exception_map[stop_exception].sigmap);
+// OBSOLETE
+// OBSOLETE if (exception_map[stop_exception].print || force_print)
+// OBSOLETE {
+// OBSOLETE target_terminal_ours ();
+// OBSOLETE
+// OBSOLETE printf_filtered ("\n%s received %s exception : ",
+// OBSOLETE who,
+// OBSOLETE exception_map[stop_exception].name);
+// OBSOLETE
+// OBSOLETE wrap_here (" ");
+// OBSOLETE
+// OBSOLETE switch (stop_exception)
+// OBSOLETE {
+// OBSOLETE case EXC_BAD_ACCESS:
+// OBSOLETE printf_filtered ("referencing address 0x%x : %s\n",
+// OBSOLETE stop_subcode,
+// OBSOLETE mach_error_string (stop_code));
+// OBSOLETE break;
+// OBSOLETE case EXC_BAD_INSTRUCTION:
+// OBSOLETE printf_filtered
+// OBSOLETE ("illegal or undefined instruction. code %d subcode %d\n",
+// OBSOLETE stop_code, stop_subcode);
+// OBSOLETE break;
+// OBSOLETE case EXC_ARITHMETIC:
+// OBSOLETE printf_filtered ("code %d\n", stop_code);
+// OBSOLETE break;
+// OBSOLETE case EXC_EMULATION:
+// OBSOLETE printf_filtered ("code %d subcode %d\n", stop_code, stop_subcode);
+// OBSOLETE break;
+// OBSOLETE case EXC_SOFTWARE:
+// OBSOLETE printf_filtered ("%s specific, code 0x%x\n",
+// OBSOLETE stop_code < 0xffff ? "hardware" : "os emulation",
+// OBSOLETE stop_code);
+// OBSOLETE break;
+// OBSOLETE case EXC_BREAKPOINT:
+// OBSOLETE printf_filtered ("type %d (machine dependent)\n",
+// OBSOLETE stop_code);
+// OBSOLETE break;
+// OBSOLETE default:
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "Unknown exception");
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE setup_notify_port (int create_new)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (MACH_PORT_VALID (our_notify_port))
+// OBSOLETE {
+// OBSOLETE ret = mach_port_destroy (mach_task_self (), our_notify_port);
+// OBSOLETE CHK ("Could not destroy our_notify_port", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE our_notify_port = MACH_PORT_NULL;
+// OBSOLETE notify_chain = (port_chain_t) NULL;
+// OBSOLETE port_chain_destroy (port_chain_obstack);
+// OBSOLETE
+// OBSOLETE if (create_new)
+// OBSOLETE {
+// OBSOLETE ret = mach_port_allocate (mach_task_self (),
+// OBSOLETE MACH_PORT_RIGHT_RECEIVE,
+// OBSOLETE &our_notify_port);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "Creating notify port %s", mach_error_string (ret));
+// OBSOLETE
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE our_notify_port,
+// OBSOLETE inferior_wait_port_set);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "initial move member %s", mach_error_string (ret));
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Register our message port to the net name server
+// OBSOLETE *
+// OBSOLETE * Currently used only by the external stop-gdb program
+// OBSOLETE * since ^C does not work if you would like to enter
+// OBSOLETE * gdb command level while debugging your program.
+// OBSOLETE *
+// OBSOLETE * NOTE: If the message port is sometimes used for other
+// OBSOLETE * purposes also, the NAME must not be a guessable one.
+// OBSOLETE * Then, there should be a way to change it.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE char registered_name[MAX_NAME_LEN];
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE message_port_info (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE if (registered_name[0])
+// OBSOLETE printf_filtered ("gdb's message port name: '%s'\n",
+// OBSOLETE registered_name);
+// OBSOLETE else
+// OBSOLETE printf_filtered ("gdb's message port is not currently registered\n");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE gdb_register_port (char *name, mach_port_t port)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE static int already_signed = 0;
+// OBSOLETE int len;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (port) || !name || !*name)
+// OBSOLETE {
+// OBSOLETE warning ("Invalid registration request");
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!already_signed)
+// OBSOLETE {
+// OBSOLETE ret = mach_port_insert_right (mach_task_self (),
+// OBSOLETE our_message_port,
+// OBSOLETE our_message_port,
+// OBSOLETE MACH_MSG_TYPE_MAKE_SEND);
+// OBSOLETE CHK ("Failed to create a signature to our_message_port", ret);
+// OBSOLETE already_signed = 1;
+// OBSOLETE }
+// OBSOLETE else if (already_signed > 1)
+// OBSOLETE {
+// OBSOLETE ret = netname_check_out (name_server_port,
+// OBSOLETE registered_name,
+// OBSOLETE our_message_port);
+// OBSOLETE CHK ("Failed to check out gdb's message port", ret);
+// OBSOLETE registered_name[0] = '\000';
+// OBSOLETE already_signed = 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = netname_check_in (name_server_port, /* Name server port */
+// OBSOLETE name, /* Name of service */
+// OBSOLETE our_message_port, /* Signature */
+// OBSOLETE port); /* Creates a new send right */
+// OBSOLETE CHK ("Failed to check in the port", ret);
+// OBSOLETE
+// OBSOLETE len = 0;
+// OBSOLETE while (len < MAX_NAME_LEN && *(name + len))
+// OBSOLETE {
+// OBSOLETE registered_name[len] = *(name + len);
+// OBSOLETE len++;
+// OBSOLETE }
+// OBSOLETE registered_name[len] = '\000';
+// OBSOLETE already_signed = 2;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE struct cmd_list_element *cmd_thread_list;
+// OBSOLETE struct cmd_list_element *cmd_task_list;
+// OBSOLETE
+// OBSOLETE /*ARGSUSED */
+// OBSOLETE static void
+// OBSOLETE thread_command (char *arg, int from_tty)
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("\"thread\" must be followed by the name of a thread command.\n");
+// OBSOLETE help_list (cmd_thread_list, "thread ", -1, gdb_stdout);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*ARGSUSED */
+// OBSOLETE static void
+// OBSOLETE task_command (char *arg, int from_tty)
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("\"task\" must be followed by the name of a task command.\n");
+// OBSOLETE help_list (cmd_task_list, "task ", -1, gdb_stdout);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE add_mach_specific_commands (void)
+// OBSOLETE {
+// OBSOLETE /* Thread handling commands */
+// OBSOLETE
+// OBSOLETE /* FIXME: Move our thread support into the generic thread.c stuff so we
+// OBSOLETE can share that code. */
+// OBSOLETE add_prefix_cmd ("mthread", class_stack, thread_command,
+// OBSOLETE "Generic command for handling Mach threads in the debugged task.",
+// OBSOLETE &cmd_thread_list, "thread ", 0, &cmdlist);
+// OBSOLETE
+// OBSOLETE add_com_alias ("th", "mthread", class_stack, 1);
+// OBSOLETE
+// OBSOLETE add_cmd ("select", class_stack, thread_select_command,
+// OBSOLETE "Select and print MID of the selected thread",
+// OBSOLETE &cmd_thread_list);
+// OBSOLETE add_cmd ("list", class_stack, thread_list_command,
+// OBSOLETE "List info of task's threads. Selected thread is marked with '*'",
+// OBSOLETE &cmd_thread_list);
+// OBSOLETE add_cmd ("suspend", class_run, thread_suspend_command,
+// OBSOLETE "Suspend one or all of the threads in the selected task.",
+// OBSOLETE &cmd_thread_list);
+// OBSOLETE add_cmd ("resume", class_run, thread_resume_command,
+// OBSOLETE "Resume one or all of the threads in the selected task.",
+// OBSOLETE &cmd_thread_list);
+// OBSOLETE add_cmd ("kill", class_run, thread_kill_command,
+// OBSOLETE "Kill the specified thread MID from inferior task.",
+// OBSOLETE &cmd_thread_list);
+// OBSOLETE #if 0
+// OBSOLETE /* The rest of this support (condition_thread) was not merged. It probably
+// OBSOLETE should not be merged in this form, but instead added to the generic GDB
+// OBSOLETE thread support. */
+// OBSOLETE add_cmd ("break", class_breakpoint, condition_thread,
+// OBSOLETE "Breakpoint N will only be effective for thread MID or @SLOT\n\
+// OBSOLETE If MID/@SLOT is omitted allow all threads to break at breakpoint",
+// OBSOLETE &cmd_thread_list);
+// OBSOLETE #endif
+// OBSOLETE /* Thread command shorthands (for backward compatibility) */
+// OBSOLETE add_alias_cmd ("ts", "mthread select", 0, 0, &cmdlist);
+// OBSOLETE add_alias_cmd ("tl", "mthread list", 0, 0, &cmdlist);
+// OBSOLETE
+// OBSOLETE /* task handling commands */
+// OBSOLETE
+// OBSOLETE add_prefix_cmd ("task", class_stack, task_command,
+// OBSOLETE "Generic command for handling debugged task.",
+// OBSOLETE &cmd_task_list, "task ", 0, &cmdlist);
+// OBSOLETE
+// OBSOLETE add_com_alias ("ta", "task", class_stack, 1);
+// OBSOLETE
+// OBSOLETE add_cmd ("suspend", class_run, task_suspend_command,
+// OBSOLETE "Suspend the inferior task.",
+// OBSOLETE &cmd_task_list);
+// OBSOLETE add_cmd ("resume", class_run, task_resume_command,
+// OBSOLETE "Resume the inferior task.",
+// OBSOLETE &cmd_task_list);
+// OBSOLETE add_cmd ("info", no_class, task_info_command,
+// OBSOLETE "Print information about the specified task.",
+// OBSOLETE &cmd_task_list);
+// OBSOLETE
+// OBSOLETE /* Print my message port name */
+// OBSOLETE
+// OBSOLETE add_info ("message-port", message_port_info,
+// OBSOLETE "Returns the name of gdb's message port in the netnameserver");
+// OBSOLETE
+// OBSOLETE /* Exception commands */
+// OBSOLETE
+// OBSOLETE add_info ("exceptions", exception_info,
+// OBSOLETE "What debugger does when program gets various exceptions.\n\
+// OBSOLETE Specify an exception number as argument to print info on that\n\
+// OBSOLETE exception only.");
+// OBSOLETE
+// OBSOLETE add_com ("exception", class_run, exception_command,
+// OBSOLETE "Specify how to handle an exception.\n\
+// OBSOLETE Args are exception number followed by \"forward\" or \"keep\".\n\
+// OBSOLETE `Forward' means forward the exception to the program's normal exception\n\
+// OBSOLETE handler.\n\
+// OBSOLETE `Keep' means reenter debugger if this exception happens, and GDB maps\n\
+// OBSOLETE the exception to some signal (see info exception)\n\
+// OBSOLETE Normally \"keep\" is used to return to GDB on exception.");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE kern_return_t
+// OBSOLETE do_mach_notify_dead_name (mach_port_t notify, mach_port_t name)
+// OBSOLETE {
+// OBSOLETE kern_return_t kr = KERN_SUCCESS;
+// OBSOLETE
+// OBSOLETE /* Find the thing that notified */
+// OBSOLETE port_chain_t element = port_chain_member (notify_chain, name);
+// OBSOLETE
+// OBSOLETE /* Take name of from unreceived dead name notification list */
+// OBSOLETE notify_chain = port_chain_delete (notify_chain, name);
+// OBSOLETE
+// OBSOLETE if (!element)
+// OBSOLETE error ("Received a dead name notify from unchained port (0x%x)", name);
+// OBSOLETE
+// OBSOLETE switch (element->type)
+// OBSOLETE {
+// OBSOLETE
+// OBSOLETE case MACH_TYPE_THREAD:
+// OBSOLETE target_terminal_ours_for_output ();
+// OBSOLETE if (name == current_thread)
+// OBSOLETE {
+// OBSOLETE printf_filtered ("\nCurrent thread %d died", element->mid);
+// OBSOLETE current_thread = MACH_PORT_NULL;
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE printf_filtered ("\nThread %d died", element->mid);
+// OBSOLETE
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case MACH_TYPE_TASK:
+// OBSOLETE target_terminal_ours_for_output ();
+// OBSOLETE if (name != inferior_task)
+// OBSOLETE printf_filtered ("Task %d died, but it was not the selected task",
+// OBSOLETE element->mid);
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE printf_filtered ("Current task %d died", element->mid);
+// OBSOLETE
+// OBSOLETE mach_port_destroy (mach_task_self (), name);
+// OBSOLETE inferior_task = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE if (notify_chain)
+// OBSOLETE warning ("There were still unreceived dead_name_notifications???");
+// OBSOLETE
+// OBSOLETE /* Destroy the old notifications */
+// OBSOLETE setup_notify_port (0);
+// OBSOLETE
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE default:
+// OBSOLETE error ("Unregistered dead_name 0x%x notification received. Type is %d, mid is 0x%x",
+// OBSOLETE name, element->type, element->mid);
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE kern_return_t
+// OBSOLETE do_mach_notify_msg_accepted (mach_port_t notify, mach_port_t name)
+// OBSOLETE {
+// OBSOLETE warning ("do_mach_notify_msg_accepted : notify %x, name %x",
+// OBSOLETE notify, name);
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE kern_return_t
+// OBSOLETE do_mach_notify_no_senders (mach_port_t notify, mach_port_mscount_t mscount)
+// OBSOLETE {
+// OBSOLETE warning ("do_mach_notify_no_senders : notify %x, mscount %x",
+// OBSOLETE notify, mscount);
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE kern_return_t
+// OBSOLETE do_mach_notify_port_deleted (mach_port_t notify, mach_port_t name)
+// OBSOLETE {
+// OBSOLETE warning ("do_mach_notify_port_deleted : notify %x, name %x",
+// OBSOLETE notify, name);
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE kern_return_t
+// OBSOLETE do_mach_notify_port_destroyed (mach_port_t notify, mach_port_t rights)
+// OBSOLETE {
+// OBSOLETE warning ("do_mach_notify_port_destroyed : notify %x, rights %x",
+// OBSOLETE notify, rights);
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE kern_return_t
+// OBSOLETE do_mach_notify_send_once (mach_port_t notify)
+// OBSOLETE {
+// OBSOLETE #ifdef DUMP_SYSCALL
+// OBSOLETE /* MANY of these are generated. */
+// OBSOLETE warning ("do_mach_notify_send_once : notify %x",
+// OBSOLETE notify);
+// OBSOLETE #endif
+// OBSOLETE return KERN_SUCCESS;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Kills the inferior. It's gone when you call this */
+// OBSOLETE static void
+// OBSOLETE kill_inferior_fast (void)
+// OBSOLETE {
+// OBSOLETE WAITTYPE w;
+// OBSOLETE
+// OBSOLETE if (PIDGET (inferior_ptid) == 0 || PIDGET (inferior_ptid) == 1)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE /* kill() it, since the Unix server does not otherwise notice when
+// OBSOLETE * killed with task_terminate().
+// OBSOLETE */
+// OBSOLETE if (PIDGET (inferior_ptid) > 0)
+// OBSOLETE kill (PIDGET (inferior_ptid), SIGKILL);
+// OBSOLETE
+// OBSOLETE /* It's propably terminate already */
+// OBSOLETE (void) task_terminate (inferior_task);
+// OBSOLETE
+// OBSOLETE inferior_task = MACH_PORT_NULL;
+// OBSOLETE current_thread = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE wait3 (&w, WNOHANG, 0);
+// OBSOLETE
+// OBSOLETE setup_notify_port (0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_kill_inferior (void)
+// OBSOLETE {
+// OBSOLETE kill_inferior_fast ();
+// OBSOLETE target_mourn_inferior ();
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Clean up after the inferior dies. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_mourn_inferior (void)
+// OBSOLETE {
+// OBSOLETE unpush_target (&m3_ops);
+// OBSOLETE generic_mourn_inferior ();
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE /* Fork an inferior process, and start debugging it. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_create_inferior (char *exec_file, char *allargs, char **env)
+// OBSOLETE {
+// OBSOLETE fork_inferior (exec_file, allargs, env, m3_trace_me, m3_trace_him, NULL, NULL);
+// OBSOLETE /* We are at the first instruction we care about. */
+// OBSOLETE /* Pedal to the metal... */
+// OBSOLETE proceed ((CORE_ADDR) -1, 0, 0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Mark our target-struct as eligible for stray "run" and "attach"
+// OBSOLETE commands. */
+// OBSOLETE static int
+// OBSOLETE m3_can_run (void)
+// OBSOLETE {
+// OBSOLETE return 1;
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* Mach 3.0 does not need ptrace for anything
+// OBSOLETE * Make sure nobody uses it on mach.
+// OBSOLETE */
+// OBSOLETE ptrace (int a, int b, int c, int d)
+// OBSOLETE {
+// OBSOLETE error ("Lose, Lose! Somebody called ptrace\n");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Resume execution of the inferior process.
+// OBSOLETE If STEP is nonzero, single-step it.
+// OBSOLETE If SIGNAL is nonzero, give it that signal. */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE m3_resume (ptid_t ptid, int step, enum target_signal signal)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (step)
+// OBSOLETE {
+// OBSOLETE thread_basic_info_data_t th_info;
+// OBSOLETE unsigned int infoCnt = THREAD_BASIC_INFO_COUNT;
+// OBSOLETE
+// OBSOLETE /* There is no point in single stepping when current_thread
+// OBSOLETE * is dead.
+// OBSOLETE */
+// OBSOLETE if (!MACH_PORT_VALID (current_thread))
+// OBSOLETE error ("No thread selected; can not single step");
+// OBSOLETE
+// OBSOLETE /* If current_thread is suspended, tracing it would never return.
+// OBSOLETE */
+// OBSOLETE ret = thread_info (current_thread,
+// OBSOLETE THREAD_BASIC_INFO,
+// OBSOLETE (thread_info_t) & th_info,
+// OBSOLETE &infoCnt);
+// OBSOLETE CHK ("child_resume: can't get thread info", ret);
+// OBSOLETE
+// OBSOLETE if (th_info.suspend_count)
+// OBSOLETE error ("Can't trace a suspended thread. Use \"thread resume\" command to resume it");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE vm_read_cache_valid = FALSE;
+// OBSOLETE
+// OBSOLETE if (signal && PIDGET (inferior_ptid) > 0) /* Do not signal, if attached by MID */
+// OBSOLETE kill (PIDGET (inferior_ptid), target_signal_to_host (signal));
+// OBSOLETE
+// OBSOLETE if (step)
+// OBSOLETE {
+// OBSOLETE suspend_all_threads (0);
+// OBSOLETE
+// OBSOLETE setup_single_step (current_thread, TRUE);
+// OBSOLETE
+// OBSOLETE ret = thread_resume (current_thread);
+// OBSOLETE CHK ("thread_resume", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = task_resume (inferior_task);
+// OBSOLETE if (ret == KERN_FAILURE)
+// OBSOLETE warning ("Task was not suspended");
+// OBSOLETE else
+// OBSOLETE CHK ("Resuming task", ret);
+// OBSOLETE
+// OBSOLETE /* HACK HACK This is needed by the multiserver system HACK HACK */
+// OBSOLETE while ((ret = task_resume (inferior_task)) == KERN_SUCCESS)
+// OBSOLETE /* make sure it really runs */ ;
+// OBSOLETE /* HACK HACK This is needed by the multiserver system HACK HACK */
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE #ifdef ATTACH_DETACH
+// OBSOLETE
+// OBSOLETE /* Start debugging the process with the given task */
+// OBSOLETE void
+// OBSOLETE task_attach (task_t tid)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE inferior_task = tid;
+// OBSOLETE
+// OBSOLETE ret = task_suspend (inferior_task);
+// OBSOLETE CHK ("task_attach: task_suspend", ret);
+// OBSOLETE
+// OBSOLETE must_suspend_thread = 0;
+// OBSOLETE
+// OBSOLETE setup_notify_port (1);
+// OBSOLETE
+// OBSOLETE request_notify (inferior_task, MACH_NOTIFY_DEAD_NAME, MACH_TYPE_TASK);
+// OBSOLETE
+// OBSOLETE setup_exception_port ();
+// OBSOLETE
+// OBSOLETE emulator_present = have_emulator_p (inferior_task);
+// OBSOLETE
+// OBSOLETE attach_flag = 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Well, we can call error also here and leave the
+// OBSOLETE * target stack inconsistent. Sigh.
+// OBSOLETE * Fix this sometime (the only way to fail here is that
+// OBSOLETE * the task has no threads at all, which is rare, but
+// OBSOLETE * possible; or if the target task has died, which is also
+// OBSOLETE * possible, but unlikely, since it has been suspended.
+// OBSOLETE * (Someone must have killed it))
+// OBSOLETE */
+// OBSOLETE void
+// OBSOLETE attach_to_thread (void)
+// OBSOLETE {
+// OBSOLETE if (select_thread (inferior_task, 0, 1) != KERN_SUCCESS)
+// OBSOLETE error ("Could not select any threads to attach to");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE mid_attach (int mid)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE ret = machid_mach_port (mid_server, mid_auth, mid, &inferior_task);
+// OBSOLETE CHK ("mid_attach: machid_mach_port", ret);
+// OBSOLETE
+// OBSOLETE task_attach (inferior_task);
+// OBSOLETE
+// OBSOLETE return mid;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Start debugging the process whose unix process-id is PID.
+// OBSOLETE * A negative "pid" value is legal and signifies a mach_id not a unix pid.
+// OBSOLETE *
+// OBSOLETE * Prevent (possible unwanted) dangerous operations by enabled users
+// OBSOLETE * like "atta 0" or "atta foo" (equal to the previous :-) and
+// OBSOLETE * "atta pidself". Anyway, the latter is allowed by specifying a MID.
+// OBSOLETE */
+// OBSOLETE static int
+// OBSOLETE m3_do_attach (int pid)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (pid == 0)
+// OBSOLETE error ("MID=0, Debugging the master unix server does not compute");
+// OBSOLETE
+// OBSOLETE /* Foo. This assumes gdb has a unix pid */
+// OBSOLETE if (pid == getpid ())
+// OBSOLETE error ("I will debug myself only by mid. (Gdb would suspend itself!)");
+// OBSOLETE
+// OBSOLETE if (pid < 0)
+// OBSOLETE {
+// OBSOLETE mid_attach (-(pid));
+// OBSOLETE
+// OBSOLETE /* inferior_ptid will be NEGATIVE! */
+// OBSOLETE inferior_ptid = pid_to_ptid (pid);
+// OBSOLETE
+// OBSOLETE return PIDGET (inferior_ptid);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE inferior_task = task_by_pid (pid);
+// OBSOLETE if (!MACH_PORT_VALID (inferior_task))
+// OBSOLETE error ("Cannot map Unix pid %d to Mach task port", pid);
+// OBSOLETE
+// OBSOLETE task_attach (inferior_task);
+// OBSOLETE
+// OBSOLETE inferior_ptid = pid_to_ptid (pid);
+// OBSOLETE
+// OBSOLETE return PIDGET (inferior_ptid);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Attach to process PID, then initialize for debugging it
+// OBSOLETE and wait for the trace-trap that results from attaching. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_attach (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE char *exec_file;
+// OBSOLETE int pid;
+// OBSOLETE
+// OBSOLETE if (!args)
+// OBSOLETE error_no_arg ("process-id to attach");
+// OBSOLETE
+// OBSOLETE pid = atoi (args);
+// OBSOLETE
+// OBSOLETE if (pid == getpid ()) /* Trying to masturbate? */
+// OBSOLETE error ("I refuse to debug myself!");
+// OBSOLETE
+// OBSOLETE if (from_tty)
+// OBSOLETE {
+// OBSOLETE exec_file = (char *) get_exec_file (0);
+// OBSOLETE
+// OBSOLETE if (exec_file)
+// OBSOLETE printf_unfiltered ("Attaching to program `%s', %s\n", exec_file,
+// OBSOLETE target_pid_to_str (pid_to_ptid (pid)));
+// OBSOLETE else
+// OBSOLETE printf_unfiltered ("Attaching to %s\n",
+// OBSOLETE target_pid_to_str (pid_to_ptid (pid)));
+// OBSOLETE
+// OBSOLETE gdb_flush (gdb_stdout);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE m3_do_attach (pid_to_ptid (pid));
+// OBSOLETE inferior_ptid = pid_to_ptid (pid);
+// OBSOLETE push_target (&m3_ops);
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE void
+// OBSOLETE deallocate_inferior_ports (void)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE thread_array_t thread_list;
+// OBSOLETE int thread_count, index;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (inferior_task))
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE ret = task_threads (inferior_task, &thread_list, &thread_count);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE warning ("deallocate_inferior_ports: task_threads",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Get rid of send rights to task threads */
+// OBSOLETE for (index = 0; index < thread_count; index++)
+// OBSOLETE {
+// OBSOLETE int rights;
+// OBSOLETE ret = mach_port_get_refs (mach_task_self (),
+// OBSOLETE thread_list[index],
+// OBSOLETE MACH_PORT_RIGHT_SEND,
+// OBSOLETE &rights);
+// OBSOLETE CHK ("deallocate_inferior_ports: get refs", ret);
+// OBSOLETE
+// OBSOLETE if (rights > 0)
+// OBSOLETE {
+// OBSOLETE ret = mach_port_mod_refs (mach_task_self (),
+// OBSOLETE thread_list[index],
+// OBSOLETE MACH_PORT_RIGHT_SEND,
+// OBSOLETE -rights);
+// OBSOLETE CHK ("deallocate_inferior_ports: mod refs", ret);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = mach_port_mod_refs (mach_task_self (),
+// OBSOLETE inferior_exception_port,
+// OBSOLETE MACH_PORT_RIGHT_RECEIVE,
+// OBSOLETE -1);
+// OBSOLETE CHK ("deallocate_inferior_ports: cannot get rid of exception port", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_deallocate (mach_task_self (),
+// OBSOLETE inferior_task);
+// OBSOLETE CHK ("deallocate_task_port: deallocating inferior_task", ret);
+// OBSOLETE
+// OBSOLETE current_thread = MACH_PORT_NULL;
+// OBSOLETE inferior_task = MACH_PORT_NULL;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Stop debugging the process whose number is PID
+// OBSOLETE and continue it with signal number SIGNAL.
+// OBSOLETE SIGNAL = 0 means just continue it. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_do_detach (int signal)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE MACH_ERROR_NO_INFERIOR;
+// OBSOLETE
+// OBSOLETE if (current_thread != MACH_PORT_NULL)
+// OBSOLETE {
+// OBSOLETE /* Store the gdb's view of the thread we are deselecting
+// OBSOLETE * before we detach.
+// OBSOLETE * @@ I am really not sure if this is ever needeed.
+// OBSOLETE */
+// OBSOLETE target_prepare_to_store ();
+// OBSOLETE target_store_registers (-1);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE ret = task_set_special_port (inferior_task,
+// OBSOLETE TASK_EXCEPTION_PORT,
+// OBSOLETE inferior_old_exception_port);
+// OBSOLETE CHK ("task_set_special_port", ret);
+// OBSOLETE
+// OBSOLETE /* Discard all requested notifications */
+// OBSOLETE setup_notify_port (0);
+// OBSOLETE
+// OBSOLETE if (remove_breakpoints ())
+// OBSOLETE warning ("Could not remove breakpoints when detaching");
+// OBSOLETE
+// OBSOLETE if (signal && PIDGET (inferior_ptid) > 0)
+// OBSOLETE kill (PIDGET (inferior_ptid), signal);
+// OBSOLETE
+// OBSOLETE /* the task might be dead by now */
+// OBSOLETE (void) task_resume (inferior_task);
+// OBSOLETE
+// OBSOLETE deallocate_inferior_ports ();
+// OBSOLETE
+// OBSOLETE attach_flag = 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Take a program previously attached to and detaches it.
+// OBSOLETE The program resumes execution and will no longer stop
+// OBSOLETE on signals, etc. We'd better not have left any breakpoints
+// OBSOLETE in the program or it'll die when it hits one. For this
+// OBSOLETE to work, it may be necessary for the process to have been
+// OBSOLETE previously attached. It *might* work if the program was
+// OBSOLETE started via fork. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_detach (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE int siggnal = 0;
+// OBSOLETE
+// OBSOLETE if (from_tty)
+// OBSOLETE {
+// OBSOLETE char *exec_file = get_exec_file (0);
+// OBSOLETE if (exec_file == 0)
+// OBSOLETE exec_file = "";
+// OBSOLETE printf_unfiltered ("Detaching from program: %s %s\n",
+// OBSOLETE exec_file, target_pid_to_str (inferior_ptid));
+// OBSOLETE gdb_flush (gdb_stdout);
+// OBSOLETE }
+// OBSOLETE if (args)
+// OBSOLETE siggnal = atoi (args);
+// OBSOLETE
+// OBSOLETE m3_do_detach (siggnal);
+// OBSOLETE inferior_ptid = null_ptid;
+// OBSOLETE unpush_target (&m3_ops); /* Pop out of handling an inferior */
+// OBSOLETE }
+// OBSOLETE #endif /* ATTACH_DETACH */
+// OBSOLETE
+// OBSOLETE /* Get ready to modify the registers array. On machines which store
+// OBSOLETE individual registers, this doesn't need to do anything. On machines
+// OBSOLETE which store all the registers in one fell swoop, this makes sure
+// OBSOLETE that registers contains all the registers from the program being
+// OBSOLETE debugged. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_prepare_to_store (void)
+// OBSOLETE {
+// OBSOLETE #ifdef CHILD_PREPARE_TO_STORE
+// OBSOLETE CHILD_PREPARE_TO_STORE ();
+// OBSOLETE #endif
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Print status information about what we're accessing. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_files_info (struct target_ops *ignore)
+// OBSOLETE {
+// OBSOLETE /* FIXME: should print MID and all that crap. */
+// OBSOLETE printf_unfiltered ("\tUsing the running image of %s %s.\n",
+// OBSOLETE attach_flag ? "attached" : "child", target_pid_to_str (inferior_ptid));
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_open (char *arg, int from_tty)
+// OBSOLETE {
+// OBSOLETE error ("Use the \"run\" command to start a Unix child process.");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #ifdef DUMP_SYSCALL
+// OBSOLETE #define STR(x) #x
+// OBSOLETE
+// OBSOLETE char *bsd1_names[] =
+// OBSOLETE {
+// OBSOLETE "execve",
+// OBSOLETE "fork",
+// OBSOLETE "take_signal",
+// OBSOLETE "sigreturn",
+// OBSOLETE "getrusage",
+// OBSOLETE "chdir",
+// OBSOLETE "chroot",
+// OBSOLETE "open",
+// OBSOLETE "creat",
+// OBSOLETE "mknod",
+// OBSOLETE "link",
+// OBSOLETE "symlink",
+// OBSOLETE "unlink",
+// OBSOLETE "access",
+// OBSOLETE "stat",
+// OBSOLETE "readlink",
+// OBSOLETE "chmod",
+// OBSOLETE "chown",
+// OBSOLETE "utimes",
+// OBSOLETE "truncate",
+// OBSOLETE "rename",
+// OBSOLETE "mkdir",
+// OBSOLETE "rmdir",
+// OBSOLETE "xutimes",
+// OBSOLETE "mount",
+// OBSOLETE "umount",
+// OBSOLETE "acct",
+// OBSOLETE "setquota",
+// OBSOLETE "write_short",
+// OBSOLETE "write_long",
+// OBSOLETE "send_short",
+// OBSOLETE "send_long",
+// OBSOLETE "sendto_short",
+// OBSOLETE "sendto_long",
+// OBSOLETE "select",
+// OBSOLETE "task_by_pid",
+// OBSOLETE "recvfrom_short",
+// OBSOLETE "recvfrom_long",
+// OBSOLETE "setgroups",
+// OBSOLETE "setrlimit",
+// OBSOLETE "sigvec",
+// OBSOLETE "sigstack",
+// OBSOLETE "settimeofday",
+// OBSOLETE "adjtime",
+// OBSOLETE "setitimer",
+// OBSOLETE "sethostname",
+// OBSOLETE "bind",
+// OBSOLETE "accept",
+// OBSOLETE "connect",
+// OBSOLETE "setsockopt",
+// OBSOLETE "getsockopt",
+// OBSOLETE "getsockname",
+// OBSOLETE "getpeername",
+// OBSOLETE "init_process",
+// OBSOLETE "table_set",
+// OBSOLETE "table_get",
+// OBSOLETE "pioctl",
+// OBSOLETE "emulator_error",
+// OBSOLETE "readwrite",
+// OBSOLETE "share_wakeup",
+// OBSOLETE 0,
+// OBSOLETE "maprw_request_it",
+// OBSOLETE "maprw_release_it",
+// OBSOLETE "maprw_remap",
+// OBSOLETE "pid_by_task",
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE int bsd1_nnames = sizeof (bsd1_names) / sizeof (bsd1_names[0]);
+// OBSOLETE
+// OBSOLETE char *
+// OBSOLETE name_str (int name, char *buf)
+// OBSOLETE {
+// OBSOLETE switch (name)
+// OBSOLETE {
+// OBSOLETE case MACH_MSG_TYPE_BOOLEAN:
+// OBSOLETE return "boolean";
+// OBSOLETE case MACH_MSG_TYPE_INTEGER_16:
+// OBSOLETE return "short";
+// OBSOLETE case MACH_MSG_TYPE_INTEGER_32:
+// OBSOLETE return "long";
+// OBSOLETE case MACH_MSG_TYPE_CHAR:
+// OBSOLETE return "char";
+// OBSOLETE case MACH_MSG_TYPE_BYTE:
+// OBSOLETE return "byte";
+// OBSOLETE case MACH_MSG_TYPE_REAL:
+// OBSOLETE return "real";
+// OBSOLETE case MACH_MSG_TYPE_STRING:
+// OBSOLETE return "string";
+// OBSOLETE default:
+// OBSOLETE sprintf (buf, "%d", name);
+// OBSOLETE return buf;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE char *
+// OBSOLETE id_str (int id, char *buf)
+// OBSOLETE {
+// OBSOLETE char *p;
+// OBSOLETE if (id >= 101000 && id < 101000 + bsd1_nnames)
+// OBSOLETE {
+// OBSOLETE if (p = bsd1_names[id - 101000])
+// OBSOLETE return p;
+// OBSOLETE }
+// OBSOLETE if (id == 102000)
+// OBSOLETE return "psignal_retry";
+// OBSOLETE if (id == 100000)
+// OBSOLETE return "syscall";
+// OBSOLETE sprintf (buf, "%d", id);
+// OBSOLETE return buf;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE print_msg (mach_msg_header_t *mp)
+// OBSOLETE {
+// OBSOLETE char *fmt_x = "%20s : 0x%08x\n";
+// OBSOLETE char *fmt_d = "%20s : %10d\n";
+// OBSOLETE char *fmt_s = "%20s : %s\n";
+// OBSOLETE char buf[100];
+// OBSOLETE
+// OBSOLETE puts_filtered ("\n");
+// OBSOLETE #define pr(fmt,h,x) printf_filtered(fmt,STR(x),(h).x)
+// OBSOLETE pr (fmt_x, (*mp), msgh_bits);
+// OBSOLETE pr (fmt_d, (*mp), msgh_size);
+// OBSOLETE pr (fmt_x, (*mp), msgh_remote_port);
+// OBSOLETE pr (fmt_x, (*mp), msgh_local_port);
+// OBSOLETE pr (fmt_d, (*mp), msgh_kind);
+// OBSOLETE printf_filtered (fmt_s, STR (msgh_id), id_str (mp->msgh_id, buf));
+// OBSOLETE
+// OBSOLETE if (debug_level > 1)
+// OBSOLETE {
+// OBSOLETE char *p, *ep, *dp;
+// OBSOLETE int plen;
+// OBSOLETE p = (char *) mp;
+// OBSOLETE ep = p + mp->msgh_size;
+// OBSOLETE p += sizeof (*mp);
+// OBSOLETE for (; p < ep; p += plen)
+// OBSOLETE {
+// OBSOLETE mach_msg_type_t *tp;
+// OBSOLETE mach_msg_type_long_t *tlp;
+// OBSOLETE int name, size, number;
+// OBSOLETE tp = (mach_msg_type_t *) p;
+// OBSOLETE if (tp->msgt_longform)
+// OBSOLETE {
+// OBSOLETE tlp = (mach_msg_type_long_t *) tp;
+// OBSOLETE name = tlp->msgtl_name;
+// OBSOLETE size = tlp->msgtl_size;
+// OBSOLETE number = tlp->msgtl_number;
+// OBSOLETE plen = sizeof (*tlp);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE name = tp->msgt_name;
+// OBSOLETE size = tp->msgt_size;
+// OBSOLETE number = tp->msgt_number;
+// OBSOLETE plen = sizeof (*tp);
+// OBSOLETE }
+// OBSOLETE printf_filtered ("name=%-16s size=%2d number=%7d inline=%d long=%d deal=%d\n",
+// OBSOLETE name_str (name, buf), size, number, tp->msgt_inline,
+// OBSOLETE tp->msgt_longform, tp->msgt_deallocate);
+// OBSOLETE dp = p + plen;
+// OBSOLETE if (tp->msgt_inline)
+// OBSOLETE {
+// OBSOLETE int l;
+// OBSOLETE l = size * number / 8;
+// OBSOLETE l = (l + sizeof (long) - 1) & ~((sizeof (long)) - 1);
+// OBSOLETE plen += l;
+// OBSOLETE print_data (dp, size, number);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE plen += sizeof (int *);
+// OBSOLETE }
+// OBSOLETE printf_filtered ("plen=%d\n", plen);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE print_data (char *p, int size, int number)
+// OBSOLETE {
+// OBSOLETE int *ip;
+// OBSOLETE short *sp;
+// OBSOLETE int i;
+// OBSOLETE
+// OBSOLETE switch (size)
+// OBSOLETE {
+// OBSOLETE case 8:
+// OBSOLETE for (i = 0; i < number; i++)
+// OBSOLETE {
+// OBSOLETE printf_filtered (" %02x", p[i]);
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE case 16:
+// OBSOLETE sp = (short *) p;
+// OBSOLETE for (i = 0; i < number; i++)
+// OBSOLETE {
+// OBSOLETE printf_filtered (" %04x", sp[i]);
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE case 32:
+// OBSOLETE ip = (int *) p;
+// OBSOLETE for (i = 0; i < number; i++)
+// OBSOLETE {
+// OBSOLETE printf_filtered (" %08x", ip[i]);
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE puts_filtered ("\n");
+// OBSOLETE }
+// OBSOLETE #endif /* DUMP_SYSCALL */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE m3_stop (void)
+// OBSOLETE {
+// OBSOLETE error ("to_stop target function not implemented");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE m3_pid_to_exec_file (int pid)
+// OBSOLETE {
+// OBSOLETE error ("to_pid_to_exec_file target function not implemented");
+// OBSOLETE return NULL; /* To keep all compilers happy. */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE init_m3_ops (void)
+// OBSOLETE {
+// OBSOLETE m3_ops.to_shortname = "mach";
+// OBSOLETE m3_ops.to_longname = "Mach child process";
+// OBSOLETE m3_ops.to_doc = "Mach child process (started by the \"run\" command).";
+// OBSOLETE m3_ops.to_open = m3_open;
+// OBSOLETE m3_ops.to_attach = m3_attach;
+// OBSOLETE m3_ops.to_detach = m3_detach;
+// OBSOLETE m3_ops.to_resume = m3_resume;
+// OBSOLETE m3_ops.to_wait = mach_really_wait;
+// OBSOLETE m3_ops.to_fetch_registers = fetch_inferior_registers;
+// OBSOLETE m3_ops.to_store_registers = store_inferior_registers;
+// OBSOLETE m3_ops.to_prepare_to_store = m3_prepare_to_store;
+// OBSOLETE m3_ops.to_xfer_memory = m3_xfer_memory;
+// OBSOLETE m3_ops.to_files_info = m3_files_info;
+// OBSOLETE m3_ops.to_insert_breakpoint = memory_insert_breakpoint;
+// OBSOLETE m3_ops.to_remove_breakpoint = memory_remove_breakpoint;
+// OBSOLETE m3_ops.to_terminal_init = terminal_init_inferior;
+// OBSOLETE m3_ops.to_terminal_inferior = terminal_inferior;
+// OBSOLETE m3_ops.to_terminal_ours_for_output = terminal_ours_for_output;
+// OBSOLETE m3_ops.to_terminal_save_ours = terminal_save_ours;
+// OBSOLETE m3_ops.to_terminal_ours = terminal_ours;
+// OBSOLETE m3_ops.to_terminal_info = child_terminal_info;
+// OBSOLETE m3_ops.to_kill = m3_kill_inferior;
+// OBSOLETE m3_ops.to_create_inferior = m3_create_inferior;
+// OBSOLETE m3_ops.to_mourn_inferior = m3_mourn_inferior;
+// OBSOLETE m3_ops.to_can_run = m3_can_run;
+// OBSOLETE m3_ops.to_stop = m3_stop;
+// OBSOLETE m3_ops.to_pid_to_exec_file = m3_pid_to_exec_file;
+// OBSOLETE m3_ops.to_stratum = process_stratum;
+// OBSOLETE m3_ops.to_has_all_memory = 1;
+// OBSOLETE m3_ops.to_has_memory = 1;
+// OBSOLETE m3_ops.to_has_stack = 1;
+// OBSOLETE m3_ops.to_has_registers = 1;
+// OBSOLETE m3_ops.to_has_execution = 1;
+// OBSOLETE m3_ops.to_magic = OPS_MAGIC;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE _initialize_m3_nat (void)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE init_m3_ops ();
+// OBSOLETE add_target (&m3_ops);
+// OBSOLETE
+// OBSOLETE ret = mach_port_allocate (mach_task_self (),
+// OBSOLETE MACH_PORT_RIGHT_PORT_SET,
+// OBSOLETE &inferior_wait_port_set);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "initial port set %s", mach_error_string (ret));
+// OBSOLETE
+// OBSOLETE /* mach_really_wait now waits for this */
+// OBSOLETE currently_waiting_for = inferior_wait_port_set;
+// OBSOLETE
+// OBSOLETE ret = netname_look_up (name_server_port, hostname, "MachID", &mid_server);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE {
+// OBSOLETE mid_server = MACH_PORT_NULL;
+// OBSOLETE
+// OBSOLETE warning ("initialize machid: netname_lookup_up(MachID) : %s",
+// OBSOLETE mach_error_string (ret));
+// OBSOLETE warning ("Some (most?) features disabled...");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE mid_auth = mach_privileged_host_port ();
+// OBSOLETE if (mid_auth == MACH_PORT_NULL)
+// OBSOLETE mid_auth = mach_task_self ();
+// OBSOLETE
+// OBSOLETE obstack_init (port_chain_obstack);
+// OBSOLETE
+// OBSOLETE ret = mach_port_allocate (mach_task_self (),
+// OBSOLETE MACH_PORT_RIGHT_RECEIVE,
+// OBSOLETE &thread_exception_port);
+// OBSOLETE CHK ("Creating thread_exception_port for single stepping", ret);
+// OBSOLETE
+// OBSOLETE ret = mach_port_insert_right (mach_task_self (),
+// OBSOLETE thread_exception_port,
+// OBSOLETE thread_exception_port,
+// OBSOLETE MACH_MSG_TYPE_MAKE_SEND);
+// OBSOLETE CHK ("Inserting send right to thread_exception_port", ret);
+// OBSOLETE
+// OBSOLETE /* Allocate message port */
+// OBSOLETE ret = mach_port_allocate (mach_task_self (),
+// OBSOLETE MACH_PORT_RIGHT_RECEIVE,
+// OBSOLETE &our_message_port);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("Creating message port %s", mach_error_string (ret));
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE char buf[MAX_NAME_LEN];
+// OBSOLETE ret = mach_port_move_member (mach_task_self (),
+// OBSOLETE our_message_port,
+// OBSOLETE inferior_wait_port_set);
+// OBSOLETE if (ret != KERN_SUCCESS)
+// OBSOLETE warning ("message move member %s", mach_error_string (ret));
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE /* @@@@ No way to change message port name currently */
+// OBSOLETE /* Foo. This assumes gdb has a unix pid */
+// OBSOLETE sprintf (buf, "gdb-%d", getpid ());
+// OBSOLETE gdb_register_port (buf, our_message_port);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Heap for thread commands */
+// OBSOLETE obstack_init (cproc_obstack);
+// OBSOLETE
+// OBSOLETE add_mach_specific_commands ();
+// OBSOLETE }
set_gdbarch_deprecated_frame_saved_pc (gdbarch, m68hc11_frame_saved_pc);
set_gdbarch_frame_args_address (gdbarch, m68hc11_frame_args_address);
set_gdbarch_frame_locals_address (gdbarch, m68hc11_frame_locals_address);
- set_gdbarch_saved_pc_after_call (gdbarch, m68hc11_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, m68hc11_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
set_gdbarch_deprecated_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
set_gdbarch_function_start_offset (gdbarch, 0);
set_gdbarch_skip_prologue (gdbarch, m68k_skip_prologue);
- set_gdbarch_saved_pc_after_call (gdbarch, m68k_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, m68k_saved_pc_after_call);
set_gdbarch_breakpoint_from_pc (gdbarch, m68k_local_breakpoint_from_pc);
/* Stack grows down. */
help_list (maintenanceprintlist, "maintenance print ", -1, gdb_stdout);
}
+/* The "maintenance list" command is defined as a prefix, with
+ allow_unknown 0. Therefore, its own definition is called only for
+ "maintenance list" with no args. */
+
+/* ARGSUSED */
+static void
+maintenance_list_command (char *arg, int from_tty)
+{
+ printf_unfiltered ("\"maintenance list\" must be followed by the name of a list command.\n");
+ help_list (maintenancelistlist, "maintenance list ", -1, gdb_stdout);
+}
+
/* The "maintenance translate-address" command converts a section and address
to a symbol. This can be called in two ways:
maintenance translate-address <secname> <addr>
&maintenanceprintlist, "maintenance print ", 0,
&maintenancelist);
+ add_prefix_cmd ("list", class_maintenance, maintenance_list_command,
+ "Maintenance command for listing GDB internal state.",
+ &maintenancelistlist, "maintenance list ", 0,
+ &maintenancelist);
+
add_prefix_cmd ("set", class_maintenance, maintenance_set_cmd, "\
Set GDB internal variables used by the GDB maintainer.\n\
Configure variables internal to GDB that aid in GDB's maintenance",
"Print dump of current object file definitions.",
&maintenanceprintlist);
+ add_cmd ("symtabs", class_maintenance, maintenance_list_symtabs,
+ "List the full symbol tables for all object files.\n\
+This does not include information about individual symbols, blocks, or\n\
+linetables --- just the symbol table structures themselves.\n\
+With an argument REGEXP, list the symbol tables whose names that match that.",
+ &maintenancelistlist);
+
+ add_cmd ("psymtabs", class_maintenance, maintenance_list_psymtabs,
+ "List the partial symbol tables for all object files.\n\
+This does not include information about individual partial symbols,\n\
+just the symbol table structures themselves.",
+ &maintenancelistlist);
+
add_cmd ("statistics", class_maintenance, maintenance_print_statistics,
"Print statistics about internal gdb state.",
&maintenanceprintlist);
set_gdbarch_call_dummy_words (gdbarch, call_dummy_words);
set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
- set_gdbarch_saved_pc_after_call (gdbarch, mcore_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mcore_saved_pc_after_call);
set_gdbarch_function_start_offset (gdbarch, 0);
set_gdbarch_decr_pc_after_break (gdbarch, 0);
set_gdbarch_breakpoint_from_pc (gdbarch, mcore_breakpoint_from_pc);
for (i = 0; i < mcount; i++)
{
+ /* If a symbol's name starts with _Z and was successfully
+ demangled, then we can assume we've found a GNU v3 symbol.
+ For now we set the C++ ABI globally; if the user is
+ mixing ABIs then the user will need to "set cp-abi"
+ manually. */
const char *name = SYMBOL_LINKAGE_NAME (&objfile->msymbols[i]);
- if (name[0] == '_' && name[1] == 'Z')
+ if (name[0] == '_' && name[1] == 'Z'
+ && SYMBOL_DEMANGLED_NAME (&objfile->msymbols[i]) != NULL)
{
set_cp_abi_as_auto_default ("gnu-v3");
break;
static CORE_ADDR
mips_read_sp (void)
{
- return ADDR_BITS_REMOVE (read_register (SP_REGNUM));
+ return read_signed_register (SP_REGNUM);
}
/* Should the upper word of 64-bit addresses be zeroed? */
CORE_ADDR pc, tmp;
pc = ((fromleaf)
- ? SAVED_PC_AFTER_CALL (get_next_frame (prev))
+ ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev))
: get_next_frame (prev)
? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev))
: read_pc ());
if (start_pc < fence)
{
/* It's not clear to me why we reach this point when
- stop_soon_quietly, but with this test, at least we
+ stop_soon, but with this test, at least we
don't print out warnings for every child forked (eg, on
decstation). 22apr93 rich@cygnus.com. */
- if (!stop_soon_quietly)
+ if (stop_soon == NO_STOP_QUIETLY)
{
static int blurb_printed = 0;
get_frame_pointer (struct frame_info *frame,
mips_extra_func_info_t proc_desc)
{
- return ADDR_BITS_REMOVE (read_next_frame_reg (frame,
- PROC_FRAME_REG (proc_desc)) +
- PROC_FRAME_OFFSET (proc_desc) -
- PROC_FRAME_ADJUST (proc_desc));
+ return (read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc))
+ + PROC_FRAME_OFFSET (proc_desc)
+ - PROC_FRAME_ADJUST (proc_desc));
}
static mips_extra_func_info_t cached_proc_desc;
}
static void
-mips_push_register (CORE_ADDR * sp, int regno)
-{
- char *buffer = alloca (MAX_REGISTER_RAW_SIZE);
- int regsize;
- int offset;
- if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
- {
- regsize = MIPS_SAVED_REGSIZE;
- offset = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
- : 0);
- }
- else
- {
- regsize = REGISTER_RAW_SIZE (regno);
- offset = 0;
- }
- *sp -= regsize;
- deprecated_read_register_gen (regno, buffer);
- write_memory (*sp, buffer + offset, regsize);
-}
-
-/* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
-#define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
-
-static void
-mips_push_dummy_frame (void)
-{
- int ireg;
- struct linked_proc_info *link = (struct linked_proc_info *)
- xmalloc (sizeof (struct linked_proc_info));
- mips_extra_func_info_t proc_desc = &link->info;
- CORE_ADDR sp = ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM));
- CORE_ADDR old_sp = sp;
- link->next = linked_proc_desc_table;
- linked_proc_desc_table = link;
-
-/* FIXME! are these correct ? */
-#define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
-#define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
-#define FLOAT_REG_SAVE_MASK MASK(0,19)
-#define FLOAT_SINGLE_REG_SAVE_MASK \
- ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
- /*
- * The registers we must save are all those not preserved across
- * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
- * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
- * and FP Control/Status registers.
- *
- *
- * Dummy frame layout:
- * (high memory)
- * Saved PC
- * Saved MMHI, MMLO, FPC_CSR
- * Saved R31
- * Saved R28
- * ...
- * Saved R1
- * Saved D18 (i.e. F19, F18)
- * ...
- * Saved D0 (i.e. F1, F0)
- * Argument build area and stack arguments written via mips_push_arguments
- * (low memory)
- */
-
- /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
- PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
- PROC_FRAME_OFFSET (proc_desc) = 0;
- PROC_FRAME_ADJUST (proc_desc) = 0;
- mips_push_register (&sp, PC_REGNUM);
- mips_push_register (&sp, HI_REGNUM);
- mips_push_register (&sp, LO_REGNUM);
- mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
-
- /* Save general CPU registers */
- PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
- /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
- PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
- for (ireg = 32; --ireg >= 0;)
- if (PROC_REG_MASK (proc_desc) & (1 << ireg))
- mips_push_register (&sp, ireg);
-
- /* Save floating point registers starting with high order word */
- PROC_FREG_MASK (proc_desc) =
- MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
- : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
- /* PROC_FREG_OFFSET is the offset of the first saved *double* register
- from FP. */
- PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
- for (ireg = 32; --ireg >= 0;)
- if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
- mips_push_register (&sp, ireg + FP0_REGNUM);
-
- /* Update the frame pointer for the call dummy and the stack pointer.
- Set the procedure's starting and ending addresses to point to the
- call dummy address at the entry point. */
- write_register (PUSH_FP_REGNUM, old_sp);
- write_register (SP_REGNUM, sp);
- PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
- PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
- SET_PROC_DESC_IS_DUMMY (proc_desc);
- PROC_PC_REG (proc_desc) = RA_REGNUM;
-}
-
-static void
mips_pop_frame (void)
{
register int regnum;
struct frame_info *frame = get_current_frame ();
CORE_ADDR new_sp = get_frame_base (frame);
- mips_extra_func_info_t proc_desc = get_frame_extra_info (frame)->proc_desc;
+ mips_extra_func_info_t proc_desc;
if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 0, 0))
{
return;
}
+ proc_desc = get_frame_extra_info (frame)->proc_desc;
write_register (PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame));
if (get_frame_saved_regs (frame) == NULL)
DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
}
static void
-mips_print_register (int regnum, int all)
-{
- char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
-
- /* Get the data in raw format. */
- if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
- {
- printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
- return;
- }
-
- /* If we have a actual 32-bit floating point register (or we are in
- 32-bit compatibility mode), and the register is even-numbered,
- also print it as a double (spanning two registers). */
- if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
- && (REGISTER_RAW_SIZE (regnum) == 4
- || mips2_fp_compat ())
- && !((regnum - FP0_REGNUM) & 1))
- {
- char *dbuffer = alloca (2 * MAX_REGISTER_RAW_SIZE);
-
- mips_read_fp_register_double (regnum, dbuffer);
-
- printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
- val_print (mips_double_register_type (), dbuffer, 0, 0,
- gdb_stdout, 0, 1, 0, Val_pretty_default);
- printf_filtered ("); ");
- }
- fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
-
- /* The problem with printing numeric register names (r26, etc.) is that
- the user can't use them on input. Probably the best solution is to
- fix it so that either the numeric or the funky (a2, etc.) names
- are accepted on input. */
- if (regnum < MIPS_NUMREGS)
- printf_filtered ("(r%d): ", regnum);
- else
- printf_filtered (": ");
-
- /* If virtual format is floating, print it that way. */
- if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
- if (REGISTER_RAW_SIZE (regnum) == 8 && !mips2_fp_compat ())
- {
- /* We have a meaningful 64-bit value in this register. Show
- it as a 32-bit float and a 64-bit double. */
- int offset = 4 * (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG);
-
- printf_filtered (" (float) ");
- val_print (mips_float_register_type (), raw_buffer + offset, 0, 0,
- gdb_stdout, 0, 1, 0, Val_pretty_default);
- printf_filtered (", (double) ");
- val_print (mips_double_register_type (), raw_buffer, 0, 0,
- gdb_stdout, 0, 1, 0, Val_pretty_default);
- }
- else
- val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
- gdb_stdout, 0, 1, 0, Val_pretty_default);
- /* Else print as integer in hex. */
- else
- {
- int offset;
-
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
- else
- offset = 0;
-
- print_scalar_formatted (raw_buffer + offset,
- REGISTER_VIRTUAL_TYPE (regnum),
- 'x', 0, gdb_stdout);
- }
-}
-
-/* Replacement for generic do_registers_info.
- Print regs in pretty columns. */
-
-static int
-do_fp_register_row (int regnum)
+mips_print_fp_register (int regnum)
{ /* do values for FP (float) regs */
char *raw_buffer;
double doub, flt1, flt2; /* doubles extracted from raw hex data */
- int inv1, inv2, inv3;
+ int inv1, inv2, namelen;
raw_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
+ printf_filtered ("%s:", REGISTER_NAME (regnum));
+ printf_filtered ("%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), "");
+
if (REGISTER_RAW_SIZE (regnum) == 4 || mips2_fp_compat ())
{
- /* 4-byte registers: we can fit two registers per row. */
- /* Also print every pair of 4-byte regs as an 8-byte double. */
+ /* 4-byte registers: Print hex and floating. Also print even
+ numbered registers as doubles. */
mips_read_fp_register_single (regnum, raw_buffer);
flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
- mips_read_fp_register_single (regnum + 1, raw_buffer);
- flt2 = unpack_double (mips_float_register_type (), raw_buffer, &inv2);
-
- mips_read_fp_register_double (regnum, raw_buffer);
- doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
+ print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
+ gdb_stdout);
- printf_filtered (" %-5s", REGISTER_NAME (regnum));
+ printf_filtered (" flt: ");
if (inv1)
- printf_filtered (": <invalid float>");
+ printf_filtered (" <invalid float> ");
else
printf_filtered ("%-17.9g", flt1);
- printf_filtered (" %-5s", REGISTER_NAME (regnum + 1));
- if (inv2)
- printf_filtered (": <invalid float>");
- else
- printf_filtered ("%-17.9g", flt2);
-
- printf_filtered (" dbl: ");
- if (inv3)
- printf_filtered ("<invalid double>");
- else
- printf_filtered ("%-24.17g", doub);
- printf_filtered ("\n");
+ if (regnum % 2 == 0)
+ {
+ mips_read_fp_register_double (regnum, raw_buffer);
+ doub = unpack_double (mips_double_register_type (), raw_buffer,
+ &inv2);
- /* may want to do hex display here (future enhancement) */
- regnum += 2;
+ printf_filtered (" dbl: ");
+ if (inv2)
+ printf_filtered ("<invalid double>");
+ else
+ printf_filtered ("%-24.17g", doub);
+ }
}
else
{
- /* Eight byte registers: print each one as float AND as double. */
+ /* Eight byte registers: print each one as hex, float and double. */
mips_read_fp_register_single (regnum, raw_buffer);
flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
mips_read_fp_register_double (regnum, raw_buffer);
- doub = unpack_double (mips_double_register_type (), raw_buffer, &inv3);
+ doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
+
- printf_filtered (" %-5s: ", REGISTER_NAME (regnum));
+ print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
+ gdb_stdout);
+
+ printf_filtered (" flt: ");
if (inv1)
printf_filtered ("<invalid float>");
else
- printf_filtered ("flt: %-17.9g", flt1);
+ printf_filtered ("%-17.9g", flt1);
printf_filtered (" dbl: ");
- if (inv3)
+ if (inv2)
printf_filtered ("<invalid double>");
else
printf_filtered ("%-24.17g", doub);
+ }
+}
- printf_filtered ("\n");
- /* may want to do hex display here (future enhancement) */
- regnum++;
+static void
+mips_print_register (int regnum, int all)
+{
+ char *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE);
+ int offset;
+
+ if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
+ {
+ mips_print_fp_register (regnum);
+ return;
}
- return regnum;
+
+ /* Get the data in raw format. */
+ if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
+ {
+ printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
+ return;
+ }
+
+ fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
+
+ /* The problem with printing numeric register names (r26, etc.) is that
+ the user can't use them on input. Probably the best solution is to
+ fix it so that either the numeric or the funky (a2, etc.) names
+ are accepted on input. */
+ if (regnum < MIPS_NUMREGS)
+ printf_filtered ("(r%d): ", regnum);
+ else
+ printf_filtered (": ");
+
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
+ else
+ offset = 0;
+
+ print_scalar_formatted (raw_buffer + offset,
+ REGISTER_VIRTUAL_TYPE (regnum),
+ 'x', 0, gdb_stdout);
+}
+
+/* Replacement for generic do_registers_info.
+ Print regs in pretty columns. */
+
+static int
+do_fp_register_row (int regnum)
+{
+ printf_filtered (" ");
+ mips_print_fp_register (regnum);
+ printf_filtered ("\n");
+ return regnum + 1;
}
+
/* Print a row's worth of GP (int) registers, with name labels above */
static int
if (wanted_abi != MIPS_ABI_UNKNOWN)
mips_abi = wanted_abi;
+ /* We have to set tm_print_insn_info before looking for a
+ pre-existing architecture, otherwise we may return before we get
+ a chance to set it up. */
+ if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64)
+ {
+ /* Set up the disassembler info, so that we get the right
+ register names from libopcodes. */
+ if (mips_abi == MIPS_ABI_N32)
+ tm_print_insn_info.disassembler_options = "gpr-names=n32";
+ else
+ tm_print_insn_info.disassembler_options = "gpr-names=64";
+ tm_print_insn_info.flavour = bfd_target_elf_flavour;
+ tm_print_insn_info.arch = bfd_arch_mips;
+ if (info.bfd_arch_info != NULL
+ && info.bfd_arch_info->arch == bfd_arch_mips
+ && info.bfd_arch_info->mach)
+ tm_print_insn_info.mach = info.bfd_arch_info->mach;
+ else
+ tm_print_insn_info.mach = bfd_mach_mips8000;
+ }
+ else
+ /* This string is not recognized explicitly by the disassembler,
+ but it tells the disassembler to not try to guess the ABI from
+ the bfd elf headers, such that, if the user overrides the ABI
+ of a program linked as NewABI, the disassembly will follow the
+ register naming conventions specified by the user. */
+ tm_print_insn_info.disassembler_options = "gpr-names=32";
+
if (gdbarch_debug)
{
fprintf_unfiltered (gdb_stdlog,
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
-
- /* Set up the disassembler info, so that we get the right
- register names from libopcodes. */
- tm_print_insn_info.flavour = bfd_target_elf_flavour;
- tm_print_insn_info.arch = bfd_arch_mips;
- if (info.bfd_arch_info != NULL
- && info.bfd_arch_info->arch == bfd_arch_mips
- && info.bfd_arch_info->mach)
- tm_print_insn_info.mach = info.bfd_arch_info->mach;
- else
- tm_print_insn_info.mach = bfd_mach_mips8000;
-
set_gdbarch_use_struct_convention (gdbarch,
mips_n32n64_use_struct_convention);
set_gdbarch_reg_struct_has_addr (gdbarch,
set_gdbarch_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
-
- /* Set up the disassembler info, so that we get the right
- register names from libopcodes. */
- tm_print_insn_info.flavour = bfd_target_elf_flavour;
- tm_print_insn_info.arch = bfd_arch_mips;
- if (info.bfd_arch_info != NULL
- && info.bfd_arch_info->arch == bfd_arch_mips
- && info.bfd_arch_info->mach)
- tm_print_insn_info.mach = info.bfd_arch_info->mach;
- else
- tm_print_insn_info.mach = bfd_mach_mips8000;
-
set_gdbarch_use_struct_convention (gdbarch,
mips_n32n64_use_struct_convention);
set_gdbarch_reg_struct_has_addr (gdbarch,
set_gdbarch_decr_pc_after_break (gdbarch, 0);
set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
- set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
"mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
GDB_TARGET_IS_MIPS64);
fprintf_unfiltered (file,
- "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
- GEN_REG_SAVE_MASK);
- fprintf_unfiltered (file,
"mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT));
fprintf_unfiltered (file,
"mips_dump_tdep: PS_REGNUM = %d\n",
PS_REGNUM);
fprintf_unfiltered (file,
- "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
- PUSH_FP_REGNUM);
- fprintf_unfiltered (file,
"mips_dump_tdep: RA_REGNUM = %d\n",
RA_REGNUM);
fprintf_unfiltered (file,
#ifndef MIPS_TDEP_H
#define MIPS_TDEP_H
+struct gdbarch;
+
/* All the possible MIPS ABIs. */
enum mips_abi
{
-/* Definitions to make GDB run on a mips box under Mach 3.0
- Copyright 1992, 1993, 1998, 2000, 2001 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* Mach specific routines for little endian mips (e.g. pmax)
- * running Mach 3.0
- *
- * Author: Jukka Virtanen <jtv@hut.fi>
- */
-
-#include "defs.h"
-#include "inferior.h"
-#include "regcache.h"
-
-#include <stdio.h>
-
-#include <mach.h>
-#include <mach/message.h>
-#include <mach/exception.h>
-#include <mach_error.h>
-
-/* Find offsets to thread states at compile time.
- * If your compiler does not grok this, check the hand coded
- * offsets and use them.
- */
-
-#if 1
-
-#define REG_OFFSET(reg) (int)(&((struct mips_thread_state *)0)->reg)
-#define CREG_OFFSET(reg) (int)(&((struct mips_float_state *)0)->reg)
-#define EREG_OFFSET(reg) (int)(&((struct mips_exc_state *)0)->reg)
-
-/* at reg_offset[i] is the offset to the mips_thread_state
- * location where the gdb registers[i] is stored.
- *
- * -1 means mach does not save it anywhere.
- */
-static int reg_offset[] =
-{
- /* zero at v0 v1 */
- -1, REG_OFFSET (r1), REG_OFFSET (r2), REG_OFFSET (r3),
-
- /* a0 a1 a2 a3 */
- REG_OFFSET (r4), REG_OFFSET (r5), REG_OFFSET (r6), REG_OFFSET (r7),
-
- /* t0 t1 t2 t3 */
- REG_OFFSET (r8), REG_OFFSET (r9), REG_OFFSET (r10), REG_OFFSET (r11),
-
- /* t4 t5 t6 t7 */
- REG_OFFSET (r12), REG_OFFSET (r13), REG_OFFSET (r14), REG_OFFSET (r15),
-
- /* s0 s1 s2 s3 */
- REG_OFFSET (r16), REG_OFFSET (r17), REG_OFFSET (r18), REG_OFFSET (r19),
-
- /* s4 s5 s6 s7 */
- REG_OFFSET (r20), REG_OFFSET (r21), REG_OFFSET (r22), REG_OFFSET (r23),
-
- /* t8 t9 k0 k1 */
- REG_OFFSET (r24), REG_OFFSET (r25), REG_OFFSET (r26), REG_OFFSET (r27),
-
- /* gp sp s8(30) == fp(72) ra */
- REG_OFFSET (r28), REG_OFFSET (r29), REG_OFFSET (r30), REG_OFFSET (r31),
-
- /* sr(32) PS_REGNUM */
- EREG_OFFSET (coproc_state),
-
- /* lo(33) hi(34) */
- REG_OFFSET (mdlo), REG_OFFSET (mdhi),
-
- /* bad(35) cause(36) pc(37) */
- EREG_OFFSET (address), EREG_OFFSET (cause), REG_OFFSET (pc),
-
- /* f0(38) f1(39) f2(40) f3(41) */
- CREG_OFFSET (r0), CREG_OFFSET (r1), CREG_OFFSET (r2), CREG_OFFSET (r3),
- CREG_OFFSET (r4), CREG_OFFSET (r5), CREG_OFFSET (r6), CREG_OFFSET (r7),
- CREG_OFFSET (r8), CREG_OFFSET (r9), CREG_OFFSET (r10), CREG_OFFSET (r11),
- CREG_OFFSET (r12), CREG_OFFSET (r13), CREG_OFFSET (r14), CREG_OFFSET (r15),
- CREG_OFFSET (r16), CREG_OFFSET (r17), CREG_OFFSET (r18), CREG_OFFSET (r19),
- CREG_OFFSET (r20), CREG_OFFSET (r21), CREG_OFFSET (r22), CREG_OFFSET (r23),
- CREG_OFFSET (r24), CREG_OFFSET (r25), CREG_OFFSET (r26), CREG_OFFSET (r27),
- CREG_OFFSET (r28), CREG_OFFSET (r29), CREG_OFFSET (r30), CREG_OFFSET (r31),
-
- /* fsr(70) fir(71) fp(72) == s8(30) */
- CREG_OFFSET (csr), CREG_OFFSET (esr), REG_OFFSET (r30)
-};
-#else
-/* If the compiler does not grok the above defines */
-static int reg_offset[] =
-{
-/* mach_thread_state offsets: */
- -1, 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56,
- 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120,
-/*sr, lo, hi,addr,cause,pc */
- 8, 124, 128, 4, 0, 132,
-/* mach_float_state offsets: */
- 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
- 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124,
-/*fsr,fir */
- 128, 132,
-/* FP_REGNUM pseudo maps to s8==r30 in mach_thread_state */
- 116
-};
-#endif
-
-/* Fetch COUNT contiguous registers from thread STATE starting from REGNUM
- * Caller knows that the regs handled in one transaction are of same size.
- */
-#define FETCH_REGS(state, regnum, count) \
- memcpy (&deprecated_registers[REGISTER_BYTE (regnum)], \
- (char *)state+reg_offset[ regnum ], \
- count*REGISTER_SIZE)
-
-/* Store COUNT contiguous registers to thread STATE starting from REGNUM */
-#define STORE_REGS(state, regnum, count) \
- memcpy ((char *)state+reg_offset[ regnum ], \
- &deprecated_registers[REGISTER_BYTE (regnum)], \
- count*REGISTER_SIZE)
-
-#define REGS_ALL -1
-#define REGS_NORMAL 1
-#define REGS_EXC 2
-#define REGS_COP1 4
-
-/* Hardware regs that matches FP_REGNUM */
-#define MACH_FP_REGNUM 30
-
-/* Fech thread's registers. if regno == -1, fetch all regs */
-void
-fetch_inferior_registers (int regno)
-{
- kern_return_t ret;
-
- thread_state_data_t state;
- struct mips_exc_state exc_state;
-
- int stateCnt = MIPS_THREAD_STATE_COUNT;
-
- int which_regs = 0; /* A bit mask */
-
- if (!MACH_PORT_VALID (current_thread))
- error ("fetch inferior registers: Invalid thread");
-
- if (regno < -1 || regno >= NUM_REGS)
- error ("invalid register %d supplied to fetch_inferior_registers", regno);
-
- if (regno == -1)
- which_regs = REGS_ALL;
- else if (regno == ZERO_REGNUM)
- {
- int zero = 0;
- supply_register (ZERO_REGNUM, &zero);
- return;
- }
- else if ((ZERO_REGNUM < regno && regno < PS_REGNUM)
- || regno == FP_REGNUM
- || regno == LO_REGNUM
- || regno == HI_REGNUM
- || regno == PC_REGNUM)
- which_regs = REGS_NORMAL;
- else if (FP0_REGNUM <= regno && regno <= FCRIR_REGNUM)
- which_regs = REGS_COP1 | REGS_EXC;
- else
- which_regs = REGS_EXC;
-
- /* fetch regs saved to mips_thread_state */
- if (which_regs & REGS_NORMAL)
- {
- ret = thread_get_state (current_thread,
- MIPS_THREAD_STATE,
- state,
- &stateCnt);
- CHK ("fetch inferior registers: thread_get_state", ret);
-
- if (which_regs == REGS_NORMAL)
- {
- /* Fetch also FP_REGNUM if fetching MACH_FP_REGNUM and vice versa */
- if (regno == MACH_FP_REGNUM || regno == FP_REGNUM)
- {
- supply_register (FP_REGNUM,
- (char *) state + reg_offset[MACH_FP_REGNUM]);
- supply_register (MACH_FP_REGNUM,
- (char *) state + reg_offset[MACH_FP_REGNUM]);
- }
- else
- supply_register (regno,
- (char *) state + reg_offset[regno]);
- return;
- }
-
- /* ZERO_REGNUM is always zero */
- *(int *) deprecated_registers = 0;
-
- /* Copy thread saved regs 1..31 to gdb's reg value array
- * Luckily, they are contiquous
- */
- FETCH_REGS (state, 1, 31);
-
- /* Copy mdlo and mdhi */
- FETCH_REGS (state, LO_REGNUM, 2);
-
- /* Copy PC */
- FETCH_REGS (state, PC_REGNUM, 1);
-
- /* Mach 3.0 saves FP to MACH_FP_REGNUM.
- * For some reason gdb wants to assign a pseudo register for it.
- */
- FETCH_REGS (state, FP_REGNUM, 1);
- }
-
- /* Read exc state. Also read if need to fetch floats */
- if (which_regs & REGS_EXC)
- {
- stateCnt = MIPS_EXC_STATE_COUNT;
- ret = thread_get_state (current_thread,
- MIPS_EXC_STATE,
- (thread_state_t) & exc_state,
- &stateCnt);
- CHK ("fetch inferior regs (exc): thread_get_state", ret);
-
- /* We need to fetch exc_state to see if the floating
- * state is valid for the thread.
- */
-
- /* cproc_state: Which coprocessors the thread uses */
- supply_register (PS_REGNUM,
- (char *) &exc_state + reg_offset[PS_REGNUM]);
-
- if (which_regs == REGS_EXC || which_regs == REGS_ALL)
- {
- supply_register (BADVADDR_REGNUM,
- (char *) &exc_state + reg_offset[BADVADDR_REGNUM]);
-
- supply_register (CAUSE_REGNUM,
- (char *) &exc_state + reg_offset[CAUSE_REGNUM]);
- if (which_regs == REGS_EXC)
- return;
- }
- }
-
-
- if (which_regs & REGS_COP1)
- {
- /* If the thread does not have saved COPROC1, set regs to zero */
-
- if (!(exc_state.coproc_state & MIPS_STATUS_USE_COP1))
- bzero (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM)],
- sizeof (struct mips_float_state));
- else
- {
- stateCnt = MIPS_FLOAT_STATE_COUNT;
- ret = thread_get_state (current_thread,
- MIPS_FLOAT_STATE,
- state,
- &stateCnt);
- CHK ("fetch inferior regs (floats): thread_get_state", ret);
-
- if (regno != -1)
- {
- supply_register (regno,
- (char *) state + reg_offset[regno]);
- return;
- }
-
- FETCH_REGS (state, FP0_REGNUM, 34);
- }
- }
-
- /* All registers are valid, if not returned yet */
- deprecated_registers_fetched ();
-}
-
-/* Store gdb's view of registers to the thread.
- * All registers are always valid when entering here.
- * @@ ahem, maybe that is too strict, we could validate the necessary ones
- * here.
- *
- * Hmm. It seems that gdb set $reg=value command first reads everything,
- * then sets the reg and then stores everything. -> we must make sure
- * that the immutable registers are not changed by reading them first.
- */
-
-void
-store_inferior_registers (register int regno)
-{
- thread_state_data_t state;
- kern_return_t ret;
-
- if (!MACH_PORT_VALID (current_thread))
- error ("store inferior registers: Invalid thread");
-
- /* Check for read only regs.
- * @@ If some of these is can be changed, fix this
- */
- if (regno == ZERO_REGNUM ||
- regno == PS_REGNUM ||
- regno == BADVADDR_REGNUM ||
- regno == CAUSE_REGNUM ||
- regno == FCRIR_REGNUM)
- {
- message ("You can not alter read-only register `%s'",
- REGISTER_NAME (regno));
- fetch_inferior_registers (regno);
- return;
- }
-
- if (regno == -1)
- {
- /* Don't allow these to change */
-
- /* ZERO_REGNUM */
- *(int *) deprecated_registers = 0;
-
- fetch_inferior_registers (PS_REGNUM);
- fetch_inferior_registers (BADVADDR_REGNUM);
- fetch_inferior_registers (CAUSE_REGNUM);
- fetch_inferior_registers (FCRIR_REGNUM);
- }
-
- if (regno == -1 || (ZERO_REGNUM < regno && regno <= PC_REGNUM))
- {
-#if 1
- /* Mach 3.0 saves thread's FP to MACH_FP_REGNUM.
- * GDB wants assigns a pseudo register FP_REGNUM for frame pointer.
- *
- * @@@ Here I assume (!) that gdb's FP has the value that
- * should go to threads frame pointer. If not true, this
- * fails badly!!!!!
- */
- memcpy (&deprecated_registers[REGISTER_BYTE (MACH_FP_REGNUM)],
- &deprecated_registers[REGISTER_BYTE (FP_REGNUM)],
- REGISTER_RAW_SIZE (FP_REGNUM));
-#endif
-
- /* Save gdb's regs 1..31 to thread saved regs 1..31
- * Luckily, they are contiquous
- */
- STORE_REGS (state, 1, 31);
-
- /* Save mdlo, mdhi */
- STORE_REGS (state, LO_REGNUM, 2);
-
- /* Save PC */
- STORE_REGS (state, PC_REGNUM, 1);
-
- ret = thread_set_state (current_thread,
- MIPS_THREAD_STATE,
- state,
- MIPS_FLOAT_STATE_COUNT);
- CHK ("store inferior regs : thread_set_state", ret);
- }
-
- if (regno == -1 || regno >= FP0_REGNUM)
- {
- /* If thread has floating state, save it */
- if (read_register (PS_REGNUM) & MIPS_STATUS_USE_COP1)
- {
- /* Do NOT save FCRIR_REGNUM */
- STORE_REGS (state, FP0_REGNUM, 33);
-
- ret = thread_set_state (current_thread,
- MIPS_FLOAT_STATE,
- state,
- MIPS_FLOAT_STATE_COUNT);
- CHK ("store inferior registers (floats): thread_set_state", ret);
- }
- else if (regno != -1)
- message
- ("Thread does not use floating point unit, floating regs not saved");
- }
-}
+// OBSOLETE /* Definitions to make GDB run on a mips box under Mach 3.0
+// OBSOLETE Copyright 1992, 1993, 1998, 2000, 2001 Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /* Mach specific routines for little endian mips (e.g. pmax)
+// OBSOLETE * running Mach 3.0
+// OBSOLETE *
+// OBSOLETE * Author: Jukka Virtanen <jtv@hut.fi>
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE #include "defs.h"
+// OBSOLETE #include "inferior.h"
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE #include <stdio.h>
+// OBSOLETE
+// OBSOLETE #include <mach.h>
+// OBSOLETE #include <mach/message.h>
+// OBSOLETE #include <mach/exception.h>
+// OBSOLETE #include <mach_error.h>
+// OBSOLETE
+// OBSOLETE /* Find offsets to thread states at compile time.
+// OBSOLETE * If your compiler does not grok this, check the hand coded
+// OBSOLETE * offsets and use them.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE #if 1
+// OBSOLETE
+// OBSOLETE #define REG_OFFSET(reg) (int)(&((struct mips_thread_state *)0)->reg)
+// OBSOLETE #define CREG_OFFSET(reg) (int)(&((struct mips_float_state *)0)->reg)
+// OBSOLETE #define EREG_OFFSET(reg) (int)(&((struct mips_exc_state *)0)->reg)
+// OBSOLETE
+// OBSOLETE /* at reg_offset[i] is the offset to the mips_thread_state
+// OBSOLETE * location where the gdb registers[i] is stored.
+// OBSOLETE *
+// OBSOLETE * -1 means mach does not save it anywhere.
+// OBSOLETE */
+// OBSOLETE static int reg_offset[] =
+// OBSOLETE {
+// OBSOLETE /* zero at v0 v1 */
+// OBSOLETE -1, REG_OFFSET (r1), REG_OFFSET (r2), REG_OFFSET (r3),
+// OBSOLETE
+// OBSOLETE /* a0 a1 a2 a3 */
+// OBSOLETE REG_OFFSET (r4), REG_OFFSET (r5), REG_OFFSET (r6), REG_OFFSET (r7),
+// OBSOLETE
+// OBSOLETE /* t0 t1 t2 t3 */
+// OBSOLETE REG_OFFSET (r8), REG_OFFSET (r9), REG_OFFSET (r10), REG_OFFSET (r11),
+// OBSOLETE
+// OBSOLETE /* t4 t5 t6 t7 */
+// OBSOLETE REG_OFFSET (r12), REG_OFFSET (r13), REG_OFFSET (r14), REG_OFFSET (r15),
+// OBSOLETE
+// OBSOLETE /* s0 s1 s2 s3 */
+// OBSOLETE REG_OFFSET (r16), REG_OFFSET (r17), REG_OFFSET (r18), REG_OFFSET (r19),
+// OBSOLETE
+// OBSOLETE /* s4 s5 s6 s7 */
+// OBSOLETE REG_OFFSET (r20), REG_OFFSET (r21), REG_OFFSET (r22), REG_OFFSET (r23),
+// OBSOLETE
+// OBSOLETE /* t8 t9 k0 k1 */
+// OBSOLETE REG_OFFSET (r24), REG_OFFSET (r25), REG_OFFSET (r26), REG_OFFSET (r27),
+// OBSOLETE
+// OBSOLETE /* gp sp s8(30) == fp(72) ra */
+// OBSOLETE REG_OFFSET (r28), REG_OFFSET (r29), REG_OFFSET (r30), REG_OFFSET (r31),
+// OBSOLETE
+// OBSOLETE /* sr(32) PS_REGNUM */
+// OBSOLETE EREG_OFFSET (coproc_state),
+// OBSOLETE
+// OBSOLETE /* lo(33) hi(34) */
+// OBSOLETE REG_OFFSET (mdlo), REG_OFFSET (mdhi),
+// OBSOLETE
+// OBSOLETE /* bad(35) cause(36) pc(37) */
+// OBSOLETE EREG_OFFSET (address), EREG_OFFSET (cause), REG_OFFSET (pc),
+// OBSOLETE
+// OBSOLETE /* f0(38) f1(39) f2(40) f3(41) */
+// OBSOLETE CREG_OFFSET (r0), CREG_OFFSET (r1), CREG_OFFSET (r2), CREG_OFFSET (r3),
+// OBSOLETE CREG_OFFSET (r4), CREG_OFFSET (r5), CREG_OFFSET (r6), CREG_OFFSET (r7),
+// OBSOLETE CREG_OFFSET (r8), CREG_OFFSET (r9), CREG_OFFSET (r10), CREG_OFFSET (r11),
+// OBSOLETE CREG_OFFSET (r12), CREG_OFFSET (r13), CREG_OFFSET (r14), CREG_OFFSET (r15),
+// OBSOLETE CREG_OFFSET (r16), CREG_OFFSET (r17), CREG_OFFSET (r18), CREG_OFFSET (r19),
+// OBSOLETE CREG_OFFSET (r20), CREG_OFFSET (r21), CREG_OFFSET (r22), CREG_OFFSET (r23),
+// OBSOLETE CREG_OFFSET (r24), CREG_OFFSET (r25), CREG_OFFSET (r26), CREG_OFFSET (r27),
+// OBSOLETE CREG_OFFSET (r28), CREG_OFFSET (r29), CREG_OFFSET (r30), CREG_OFFSET (r31),
+// OBSOLETE
+// OBSOLETE /* fsr(70) fir(71) fp(72) == s8(30) */
+// OBSOLETE CREG_OFFSET (csr), CREG_OFFSET (esr), REG_OFFSET (r30)
+// OBSOLETE };
+// OBSOLETE #else
+// OBSOLETE /* If the compiler does not grok the above defines */
+// OBSOLETE static int reg_offset[] =
+// OBSOLETE {
+// OBSOLETE /* mach_thread_state offsets: */
+// OBSOLETE -1, 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56,
+// OBSOLETE 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120,
+// OBSOLETE /*sr, lo, hi,addr,cause,pc */
+// OBSOLETE 8, 124, 128, 4, 0, 132,
+// OBSOLETE /* mach_float_state offsets: */
+// OBSOLETE 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
+// OBSOLETE 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124,
+// OBSOLETE /*fsr,fir */
+// OBSOLETE 128, 132,
+// OBSOLETE /* FP_REGNUM pseudo maps to s8==r30 in mach_thread_state */
+// OBSOLETE 116
+// OBSOLETE };
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* Fetch COUNT contiguous registers from thread STATE starting from REGNUM
+// OBSOLETE * Caller knows that the regs handled in one transaction are of same size.
+// OBSOLETE */
+// OBSOLETE #define FETCH_REGS(state, regnum, count) \
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (regnum)], \
+// OBSOLETE (char *)state+reg_offset[ regnum ], \
+// OBSOLETE count*REGISTER_SIZE)
+// OBSOLETE
+// OBSOLETE /* Store COUNT contiguous registers to thread STATE starting from REGNUM */
+// OBSOLETE #define STORE_REGS(state, regnum, count) \
+// OBSOLETE memcpy ((char *)state+reg_offset[ regnum ], \
+// OBSOLETE &deprecated_registers[REGISTER_BYTE (regnum)], \
+// OBSOLETE count*REGISTER_SIZE)
+// OBSOLETE
+// OBSOLETE #define REGS_ALL -1
+// OBSOLETE #define REGS_NORMAL 1
+// OBSOLETE #define REGS_EXC 2
+// OBSOLETE #define REGS_COP1 4
+// OBSOLETE
+// OBSOLETE /* Hardware regs that matches FP_REGNUM */
+// OBSOLETE #define MACH_FP_REGNUM 30
+// OBSOLETE
+// OBSOLETE /* Fech thread's registers. if regno == -1, fetch all regs */
+// OBSOLETE void
+// OBSOLETE fetch_inferior_registers (int regno)
+// OBSOLETE {
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE thread_state_data_t state;
+// OBSOLETE struct mips_exc_state exc_state;
+// OBSOLETE
+// OBSOLETE int stateCnt = MIPS_THREAD_STATE_COUNT;
+// OBSOLETE
+// OBSOLETE int which_regs = 0; /* A bit mask */
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (current_thread))
+// OBSOLETE error ("fetch inferior registers: Invalid thread");
+// OBSOLETE
+// OBSOLETE if (regno < -1 || regno >= NUM_REGS)
+// OBSOLETE error ("invalid register %d supplied to fetch_inferior_registers", regno);
+// OBSOLETE
+// OBSOLETE if (regno == -1)
+// OBSOLETE which_regs = REGS_ALL;
+// OBSOLETE else if (regno == ZERO_REGNUM)
+// OBSOLETE {
+// OBSOLETE int zero = 0;
+// OBSOLETE supply_register (ZERO_REGNUM, &zero);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE else if ((ZERO_REGNUM < regno && regno < PS_REGNUM)
+// OBSOLETE || regno == FP_REGNUM
+// OBSOLETE || regno == LO_REGNUM
+// OBSOLETE || regno == HI_REGNUM
+// OBSOLETE || regno == PC_REGNUM)
+// OBSOLETE which_regs = REGS_NORMAL;
+// OBSOLETE else if (FP0_REGNUM <= regno && regno <= FCRIR_REGNUM)
+// OBSOLETE which_regs = REGS_COP1 | REGS_EXC;
+// OBSOLETE else
+// OBSOLETE which_regs = REGS_EXC;
+// OBSOLETE
+// OBSOLETE /* fetch regs saved to mips_thread_state */
+// OBSOLETE if (which_regs & REGS_NORMAL)
+// OBSOLETE {
+// OBSOLETE ret = thread_get_state (current_thread,
+// OBSOLETE MIPS_THREAD_STATE,
+// OBSOLETE state,
+// OBSOLETE &stateCnt);
+// OBSOLETE CHK ("fetch inferior registers: thread_get_state", ret);
+// OBSOLETE
+// OBSOLETE if (which_regs == REGS_NORMAL)
+// OBSOLETE {
+// OBSOLETE /* Fetch also FP_REGNUM if fetching MACH_FP_REGNUM and vice versa */
+// OBSOLETE if (regno == MACH_FP_REGNUM || regno == FP_REGNUM)
+// OBSOLETE {
+// OBSOLETE supply_register (FP_REGNUM,
+// OBSOLETE (char *) state + reg_offset[MACH_FP_REGNUM]);
+// OBSOLETE supply_register (MACH_FP_REGNUM,
+// OBSOLETE (char *) state + reg_offset[MACH_FP_REGNUM]);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE supply_register (regno,
+// OBSOLETE (char *) state + reg_offset[regno]);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* ZERO_REGNUM is always zero */
+// OBSOLETE *(int *) deprecated_registers = 0;
+// OBSOLETE
+// OBSOLETE /* Copy thread saved regs 1..31 to gdb's reg value array
+// OBSOLETE * Luckily, they are contiquous
+// OBSOLETE */
+// OBSOLETE FETCH_REGS (state, 1, 31);
+// OBSOLETE
+// OBSOLETE /* Copy mdlo and mdhi */
+// OBSOLETE FETCH_REGS (state, LO_REGNUM, 2);
+// OBSOLETE
+// OBSOLETE /* Copy PC */
+// OBSOLETE FETCH_REGS (state, PC_REGNUM, 1);
+// OBSOLETE
+// OBSOLETE /* Mach 3.0 saves FP to MACH_FP_REGNUM.
+// OBSOLETE * For some reason gdb wants to assign a pseudo register for it.
+// OBSOLETE */
+// OBSOLETE FETCH_REGS (state, FP_REGNUM, 1);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Read exc state. Also read if need to fetch floats */
+// OBSOLETE if (which_regs & REGS_EXC)
+// OBSOLETE {
+// OBSOLETE stateCnt = MIPS_EXC_STATE_COUNT;
+// OBSOLETE ret = thread_get_state (current_thread,
+// OBSOLETE MIPS_EXC_STATE,
+// OBSOLETE (thread_state_t) & exc_state,
+// OBSOLETE &stateCnt);
+// OBSOLETE CHK ("fetch inferior regs (exc): thread_get_state", ret);
+// OBSOLETE
+// OBSOLETE /* We need to fetch exc_state to see if the floating
+// OBSOLETE * state is valid for the thread.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE /* cproc_state: Which coprocessors the thread uses */
+// OBSOLETE supply_register (PS_REGNUM,
+// OBSOLETE (char *) &exc_state + reg_offset[PS_REGNUM]);
+// OBSOLETE
+// OBSOLETE if (which_regs == REGS_EXC || which_regs == REGS_ALL)
+// OBSOLETE {
+// OBSOLETE supply_register (BADVADDR_REGNUM,
+// OBSOLETE (char *) &exc_state + reg_offset[BADVADDR_REGNUM]);
+// OBSOLETE
+// OBSOLETE supply_register (CAUSE_REGNUM,
+// OBSOLETE (char *) &exc_state + reg_offset[CAUSE_REGNUM]);
+// OBSOLETE if (which_regs == REGS_EXC)
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE if (which_regs & REGS_COP1)
+// OBSOLETE {
+// OBSOLETE /* If the thread does not have saved COPROC1, set regs to zero */
+// OBSOLETE
+// OBSOLETE if (!(exc_state.coproc_state & MIPS_STATUS_USE_COP1))
+// OBSOLETE bzero (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM)],
+// OBSOLETE sizeof (struct mips_float_state));
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE stateCnt = MIPS_FLOAT_STATE_COUNT;
+// OBSOLETE ret = thread_get_state (current_thread,
+// OBSOLETE MIPS_FLOAT_STATE,
+// OBSOLETE state,
+// OBSOLETE &stateCnt);
+// OBSOLETE CHK ("fetch inferior regs (floats): thread_get_state", ret);
+// OBSOLETE
+// OBSOLETE if (regno != -1)
+// OBSOLETE {
+// OBSOLETE supply_register (regno,
+// OBSOLETE (char *) state + reg_offset[regno]);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE FETCH_REGS (state, FP0_REGNUM, 34);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* All registers are valid, if not returned yet */
+// OBSOLETE deprecated_registers_fetched ();
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Store gdb's view of registers to the thread.
+// OBSOLETE * All registers are always valid when entering here.
+// OBSOLETE * @@ ahem, maybe that is too strict, we could validate the necessary ones
+// OBSOLETE * here.
+// OBSOLETE *
+// OBSOLETE * Hmm. It seems that gdb set $reg=value command first reads everything,
+// OBSOLETE * then sets the reg and then stores everything. -> we must make sure
+// OBSOLETE * that the immutable registers are not changed by reading them first.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE store_inferior_registers (register int regno)
+// OBSOLETE {
+// OBSOLETE thread_state_data_t state;
+// OBSOLETE kern_return_t ret;
+// OBSOLETE
+// OBSOLETE if (!MACH_PORT_VALID (current_thread))
+// OBSOLETE error ("store inferior registers: Invalid thread");
+// OBSOLETE
+// OBSOLETE /* Check for read only regs.
+// OBSOLETE * @@ If some of these is can be changed, fix this
+// OBSOLETE */
+// OBSOLETE if (regno == ZERO_REGNUM ||
+// OBSOLETE regno == PS_REGNUM ||
+// OBSOLETE regno == BADVADDR_REGNUM ||
+// OBSOLETE regno == CAUSE_REGNUM ||
+// OBSOLETE regno == FCRIR_REGNUM)
+// OBSOLETE {
+// OBSOLETE message ("You can not alter read-only register `%s'",
+// OBSOLETE REGISTER_NAME (regno));
+// OBSOLETE fetch_inferior_registers (regno);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (regno == -1)
+// OBSOLETE {
+// OBSOLETE /* Don't allow these to change */
+// OBSOLETE
+// OBSOLETE /* ZERO_REGNUM */
+// OBSOLETE *(int *) deprecated_registers = 0;
+// OBSOLETE
+// OBSOLETE fetch_inferior_registers (PS_REGNUM);
+// OBSOLETE fetch_inferior_registers (BADVADDR_REGNUM);
+// OBSOLETE fetch_inferior_registers (CAUSE_REGNUM);
+// OBSOLETE fetch_inferior_registers (FCRIR_REGNUM);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (regno == -1 || (ZERO_REGNUM < regno && regno <= PC_REGNUM))
+// OBSOLETE {
+// OBSOLETE #if 1
+// OBSOLETE /* Mach 3.0 saves thread's FP to MACH_FP_REGNUM.
+// OBSOLETE * GDB wants assigns a pseudo register FP_REGNUM for frame pointer.
+// OBSOLETE *
+// OBSOLETE * @@@ Here I assume (!) that gdb's FP has the value that
+// OBSOLETE * should go to threads frame pointer. If not true, this
+// OBSOLETE * fails badly!!!!!
+// OBSOLETE */
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (MACH_FP_REGNUM)],
+// OBSOLETE &deprecated_registers[REGISTER_BYTE (FP_REGNUM)],
+// OBSOLETE REGISTER_RAW_SIZE (FP_REGNUM));
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE /* Save gdb's regs 1..31 to thread saved regs 1..31
+// OBSOLETE * Luckily, they are contiquous
+// OBSOLETE */
+// OBSOLETE STORE_REGS (state, 1, 31);
+// OBSOLETE
+// OBSOLETE /* Save mdlo, mdhi */
+// OBSOLETE STORE_REGS (state, LO_REGNUM, 2);
+// OBSOLETE
+// OBSOLETE /* Save PC */
+// OBSOLETE STORE_REGS (state, PC_REGNUM, 1);
+// OBSOLETE
+// OBSOLETE ret = thread_set_state (current_thread,
+// OBSOLETE MIPS_THREAD_STATE,
+// OBSOLETE state,
+// OBSOLETE MIPS_FLOAT_STATE_COUNT);
+// OBSOLETE CHK ("store inferior regs : thread_set_state", ret);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (regno == -1 || regno >= FP0_REGNUM)
+// OBSOLETE {
+// OBSOLETE /* If thread has floating state, save it */
+// OBSOLETE if (read_register (PS_REGNUM) & MIPS_STATUS_USE_COP1)
+// OBSOLETE {
+// OBSOLETE /* Do NOT save FCRIR_REGNUM */
+// OBSOLETE STORE_REGS (state, FP0_REGNUM, 33);
+// OBSOLETE
+// OBSOLETE ret = thread_set_state (current_thread,
+// OBSOLETE MIPS_FLOAT_STATE,
+// OBSOLETE state,
+// OBSOLETE MIPS_FLOAT_STATE_COUNT);
+// OBSOLETE CHK ("store inferior registers (floats): thread_set_state", ret);
+// OBSOLETE }
+// OBSOLETE else if (regno != -1)
+// OBSOLETE message
+// OBSOLETE ("Thread does not use floating point unit, floating regs not saved");
+// OBSOLETE }
+// OBSOLETE }
/* Stack unwinding. */
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
- set_gdbarch_saved_pc_after_call (gdbarch, mn10300_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mn10300_saved_pc_after_call);
set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mn10300_init_extra_frame_info);
set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_noop);
set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mn10300_frame_init_saved_regs);
#ifndef MONITOR_H
#define MONITOR_H
+struct target_waitstatus;
struct serial;
/* This structure describes the strings necessary to give small command
if (enter_addr > 0)
{
pc = ((enter_addr == 1)
- ? SAVED_PC_AFTER_CALL (fi)
+ ? DEPRECATED_SAVED_PC_AFTER_CALL (fi)
: DEPRECATED_FRAME_SAVED_PC (fi));
insn = read_memory_integer (pc, 2);
addr_mode = (insn >> 11) & 0x1f;
/* Frame and stack info */
set_gdbarch_skip_prologue (gdbarch, umax_skip_prologue);
- set_gdbarch_saved_pc_after_call (gdbarch, ns32k_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, ns32k_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, umax_frame_num_args);
set_gdbarch_frameless_function_invocation (gdbarch,
enter_addr = ns32k_get_enter_addr (fi->pc);
if (enter_addr = 0)
return (-1);
- argp = enter_addr == 1 ? SAVED_PC_AFTER_CALL (fi) : DEPRECATED_FRAME_SAVED_PC (fi);
+ argp = (enter_addr == 1
+ ? DEPRECATED_SAVED_PC_AFTER_CALL (fi)
+ : DEPRECATED_FRAME_SAVED_PC (fi));
for (i = 0; i < 16; i++)
{
/*
if (!target_has_execution)
return 0; /* Can't call into inferior to create NSString. */
- if (!(sym = lookup_struct_typedef("NSString", 0, 1)) &&
- !(sym = lookup_struct_typedef("NXString", 0, 1)))
+ sym = lookup_struct_typedef("NSString", 0, 1);
+ if (sym == NULL)
+ sym = lookup_struct_typedef("NXString", 0, 1);
+ if (sym == NULL)
type = lookup_pointer_type(builtin_type_void);
else
type = lookup_pointer_type(SYMBOL_TYPE (sym));
int in_quotes = 0;
int need_comma = 0;
extern int inspect_it;
- extern int repeat_count_threshold;
- extern int print_max;
/* If the string was not truncated due to `set print elements', and
the last byte of it is a null, we don't print that, in
}
if (regexp != NULL)
- if (0 != (val = re_comp (myregexp)))
- error ("Invalid regexp (%s): %s", val, regexp);
+ {
+ val = re_comp (myregexp);
+ if (val != 0)
+ error ("Invalid regexp (%s): %s", val, regexp);
+ }
/* First time thru is JUST to get max length and count. */
ALL_MSYMBOLS (objfile, msymbol)
}
if (regexp != NULL)
- if (0 != (val = re_comp (myregexp)))
- error ("Invalid regexp (%s): %s", val, regexp);
+ {
+ val = re_comp (myregexp);
+ if (val != 0)
+ error ("Invalid regexp (%s): %s", val, regexp);
+ }
/* First time thru is JUST to get max length and count. */
ALL_MSYMBOLS (objfile, msymbol)
unsigned int i;
find_objc_msgsend ();
- if (new_pc != NULL) { *new_pc = 0; }
+ if (new_pc != NULL)
+ {
+ *new_pc = 0;
+ }
for (i = 0; i < nmethcalls; i++)
if ((pc >= methcalls[i].begin) && (pc < methcalls[i].end))
#ifndef OCD_H
#define OCD_H
+struct mem_attrib;
+struct target_ops;
+
/* Wiggler serial protocol definitions */
#define DLE 020 /* Quote char */
if ((get_frame_type (fi) == SIGTRAMP_FRAME))
{
CORE_ADDR regs_addr =
- read_memory_integer (fi->frame + PPC_LINUX_REGS_PTR_OFFSET, 4);
+ read_memory_integer (get_frame_base (fi)
+ + PPC_LINUX_REGS_PTR_OFFSET, 4);
/* return the NIP in the regs array */
return read_memory_integer (regs_addr + 4 * PPC_LINUX_PT_NIP, 4);
}
- else if (fi->next && (get_frame_type (fi->next) == SIGTRAMP_FRAME))
+ else if (get_next_frame (fi)
+ && (get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME))
{
CORE_ADDR regs_addr =
- read_memory_integer (fi->next->frame + PPC_LINUX_REGS_PTR_OFFSET, 4);
+ read_memory_integer (get_frame_base (get_next_frame (fi))
+ + PPC_LINUX_REGS_PTR_OFFSET, 4);
/* return LNK in the regs array */
return read_memory_integer (regs_addr + 4 * PPC_LINUX_PT_LNK, 4);
}
{
rs6000_init_extra_frame_info (fromleaf, fi);
- if (fi->next != 0)
+ if (get_next_frame (fi) != 0)
{
/* We're called from get_prev_frame_info; check to see if
this is a signal frame by looking to see if the pc points
at trampoline code */
- if (ppc_linux_at_sigtramp_return_path (fi->pc))
+ if (ppc_linux_at_sigtramp_return_path (get_frame_pc (fi)))
deprecated_set_frame_type (fi, SIGTRAMP_FRAME);
else
/* FIXME: cagney/2002-11-10: Is this double bogus? What
{
/* We'll find the wrong thing if we let
rs6000_frameless_function_invocation () search for a signal trampoline */
- if (ppc_linux_at_sigtramp_return_path (fi->pc))
+ if (ppc_linux_at_sigtramp_return_path (get_frame_pc (fi)))
return 0;
else
return rs6000_frameless_function_invocation (fi);
{
CORE_ADDR regs_addr;
int i;
- if (fi->saved_regs)
+ if (get_frame_saved_regs (fi))
return;
frame_saved_regs_zalloc (fi);
regs_addr =
- read_memory_integer (fi->frame + PPC_LINUX_REGS_PTR_OFFSET, 4);
- fi->saved_regs[PC_REGNUM] = regs_addr + 4 * PPC_LINUX_PT_NIP;
- fi->saved_regs[gdbarch_tdep (current_gdbarch)->ppc_ps_regnum] =
+ read_memory_integer (get_frame_base (fi)
+ + PPC_LINUX_REGS_PTR_OFFSET, 4);
+ get_frame_saved_regs (fi)[PC_REGNUM] = regs_addr + 4 * PPC_LINUX_PT_NIP;
+ get_frame_saved_regs (fi)[gdbarch_tdep (current_gdbarch)->ppc_ps_regnum] =
regs_addr + 4 * PPC_LINUX_PT_MSR;
- fi->saved_regs[gdbarch_tdep (current_gdbarch)->ppc_cr_regnum] =
+ get_frame_saved_regs (fi)[gdbarch_tdep (current_gdbarch)->ppc_cr_regnum] =
regs_addr + 4 * PPC_LINUX_PT_CCR;
- fi->saved_regs[gdbarch_tdep (current_gdbarch)->ppc_lr_regnum] =
+ get_frame_saved_regs (fi)[gdbarch_tdep (current_gdbarch)->ppc_lr_regnum] =
regs_addr + 4 * PPC_LINUX_PT_LNK;
- fi->saved_regs[gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum] =
+ get_frame_saved_regs (fi)[gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum] =
regs_addr + 4 * PPC_LINUX_PT_CTR;
- fi->saved_regs[gdbarch_tdep (current_gdbarch)->ppc_xer_regnum] =
+ get_frame_saved_regs (fi)[gdbarch_tdep (current_gdbarch)->ppc_xer_regnum] =
regs_addr + 4 * PPC_LINUX_PT_XER;
- fi->saved_regs[gdbarch_tdep (current_gdbarch)->ppc_mq_regnum] =
+ get_frame_saved_regs (fi)[gdbarch_tdep (current_gdbarch)->ppc_mq_regnum] =
regs_addr + 4 * PPC_LINUX_PT_MQ;
for (i = 0; i < 32; i++)
- fi->saved_regs[gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + i] =
+ get_frame_saved_regs (fi)[gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + i] =
regs_addr + 4 * PPC_LINUX_PT_R0 + 4 * i;
for (i = 0; i < 32; i++)
- fi->saved_regs[FP0_REGNUM + i] = regs_addr + 4 * PPC_LINUX_PT_FPR0 + 8 * i;
+ get_frame_saved_regs (fi)[FP0_REGNUM + i] = regs_addr + 4 * PPC_LINUX_PT_FPR0 + 8 * i;
}
else
rs6000_frame_init_saved_regs (fi);
{
/* Kernel properly constructs the frame chain for the handler */
if ((get_frame_type (thisframe) == SIGTRAMP_FRAME))
- return read_memory_integer ((thisframe)->frame, 4);
+ return read_memory_integer (get_frame_base (thisframe), 4);
else
return rs6000_frame_chain (thisframe);
}
#ifndef PPC_TDEP_H
#define PPC_TDEP_H
+struct gdbarch;
struct frame_info;
struct value;
return 1;
vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
- raw_p = regnum < gdbarch_num_regs (gdbarch);
+ /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
+ (gdbarch), as not all architectures are multi-arch. */
+ raw_p = regnum < NUM_REGS;
if (group == float_reggroup)
return float_p;
if (group == vector_reggroup)
#ifndef REMOTE_UTILS_H
#define REMOTE_UTILS_H
+struct target_ops;
+
#include "target.h"
struct serial;
extern void vx_read_register ();
extern void vx_write_register ();
extern void symbol_file_command ();
-extern int stop_soon_quietly; /* for wait_for_inferior */
+extern enum stop_kind stop_soon; /* for wait_for_inferior */
static int net_step ();
static int net_ptrace_clnt_call (); /* Forward decl */
/* Install inferior's terminal modes. */
target_terminal_inferior ();
- stop_soon_quietly = 1;
+ stop_soon = STOP_QUIETLY;
wait_for_inferior (); /* Get the task spawn event */
- stop_soon_quietly = 0;
+ stop_soon = NO_STOP_QUIETLY;
/* insert_step_breakpoint (); FIXME, do we need this? */
proceed (-1, TARGET_SIGNAL_DEFAULT, 0);
int status;
int quit_count = 0;
- extern int escape_count; /* global shared by readsocket */
- extern int echo_check; /* ditto */
-
escape_count = 0;
echo_check = -1;
CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset;
for (i = fdatap->saved_gpr; i < 32; i++)
{
- get_frame_saved_regs (fi)[i] = gpr_addr;
+ get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = gpr_addr;
gpr_addr += wordsize;
}
}
{
if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n))
{
- double val = extract_floating (from, REGISTER_RAW_SIZE (n));
- store_floating (to, TYPE_LENGTH (type), val);
+ double val = deprecated_extract_floating (from, REGISTER_RAW_SIZE (n));
+ deprecated_store_floating (to, TYPE_LENGTH (type), val);
}
else
memcpy (to, from, REGISTER_RAW_SIZE (n));
{
if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n))
{
- double val = extract_floating (from, TYPE_LENGTH (type));
- store_floating (to, REGISTER_RAW_SIZE (n), val);
+ double val = deprecated_extract_floating (from, TYPE_LENGTH (type));
+ deprecated_store_floating (to, REGISTER_RAW_SIZE (n), val);
}
else
memcpy (to, from, REGISTER_RAW_SIZE (n));
set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
- set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+ if (sysv_abi)
+ set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
+ else
+ set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
set_gdbarch_char_signed (gdbarch, 0);
set_gdbarch_fix_call_dummy (gdbarch, rs6000_fix_call_dummy);
}
set_gdbarch_frame_args_address (gdbarch, rs6000_frame_args_address);
set_gdbarch_frame_locals_address (gdbarch, rs6000_frame_args_address);
- set_gdbarch_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call);
/* We can't tell how many args there are
now that the C compiler delays popping them. */
#include <asm/ptrace.h>
#include <sys/ptrace.h>
#include <asm/processor.h>
+#include <asm/types.h>
#include <sys/procfs.h>
#include <sys/user.h>
#include <value.h>
}
+static CORE_ADDR
+s390_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+ /* Both the 32- and 64-bit ABI's say that the stack pointer should
+ always be aligned on an eight-byte boundary. */
+ return (addr & -8);
+}
+
+
static int
s390_use_struct_convention (int gcc_p, struct type *value_type)
{
/* DEPRECATED_FRAME_CHAIN takes a frame's nominal address and
produces the frame's chain-pointer. */
set_gdbarch_deprecated_frame_chain (gdbarch, s390_frame_chain);
- set_gdbarch_saved_pc_after_call (gdbarch, s390_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, s390_saved_pc_after_call);
set_gdbarch_register_byte (gdbarch, s390_register_byte);
set_gdbarch_pc_regnum (gdbarch, S390_PC_REGNUM);
set_gdbarch_sp_regnum (gdbarch, S390_SP_REGNUM);
/* Parameters for inferior function calls. */
set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_at_entry_point);
+ set_gdbarch_frame_align (gdbarch, s390_frame_align);
set_gdbarch_deprecated_push_arguments (gdbarch, s390_push_arguments);
set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
+ set_gdbarch_deprecated_push_return_address (gdbarch,
+ s390_push_return_address);
set_gdbarch_sizeof_call_dummy_words (gdbarch,
sizeof (s390_call_dummy_words));
set_gdbarch_call_dummy_words (gdbarch, s390_call_dummy_words);
#ifndef SER_UNIX_H
#define SER_UNIX_H
+struct serial;
+struct ui_file;
+
/* Generic UNIX/FD functions */
extern int ser_unix_nop_flush_output (struct serial *scb);
#ifndef SERIAL_H
#define SERIAL_H
+struct ui_file;
+
/* For most routines, if a failure is indicated, then errno should be
examined. */
floatformat_to_doublest (&floatformat_ieee_double_big,
(char *) regbuf + REGISTER_BYTE (return_register),
&val);
- store_floating (valbuf, len, val);
+ deprecated_store_floating (valbuf, len, val);
}
else if (len <= 4)
{
else
floatformat_to_doublest (&floatformat_ieee_double_big,
(char *) regbuf + offset, &val);
- store_floating (valbuf, len, val);
+ deprecated_store_floating (valbuf, len, val);
}
}
else
{
DOUBLEST val;
floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
- store_floating (to, TYPE_LENGTH (type), val);
+ deprecated_store_floating (to, TYPE_LENGTH (type), val);
}
else
error ("sh_register_convert_to_virtual called with non DR register number");
{
DOUBLEST val;
floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
- store_floating(to, TYPE_LENGTH(type), val);
+ deprecated_store_floating(to, TYPE_LENGTH(type), val);
}
else
error("sh_register_convert_to_virtual called with non DR register number");
if (regnum >= tdep->DR0_REGNUM
&& regnum <= tdep->DR_LAST_REGNUM)
{
- DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
+ DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
}
else
|| (regnum >= tdep->DR0_C_REGNUM
&& regnum <= tdep->DR_LAST_C_REGNUM))
{
- DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
+ DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
}
else
set_gdbarch_frame_args_skip (gdbarch, 0);
set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
- set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
set_gdbarch_believe_pcc_promotion (gdbarch, 1);
out what we need to know about them. */
clear_proceed_status ();
- stop_soon_quietly = 1;
+ stop_soon = STOP_QUIETLY;
stop_signal = TARGET_SIGNAL_0;
do
{
But we are stopped in the startup code and we might not have symbols
for the startup code, so heuristic_proc_start could be called
and will put out an annoying warning.
- Delaying the resetting of stop_soon_quietly until after symbol loading
+ Delaying the resetting of stop_soon until after symbol loading
suppresses the warning. */
solib_add ((char *) 0, 0, (struct target_ops *) 0, auto_solib_add);
- stop_soon_quietly = 0;
+ stop_soon = NO_STOP_QUIETLY;
re_enable_breakpoints_in_shlibs ();
}
out what we need to know about them. */
clear_proceed_status ();
- stop_soon_quietly = 1;
+ stop_soon = STOP_QUIETLY;
stop_signal = TARGET_SIGNAL_0;
do
{
But we are stopped in the runtime loader and we do not have symbols
for the runtime loader. So heuristic_proc_start will be called
and will put out an annoying warning.
- Delaying the resetting of stop_soon_quietly until after symbol loading
+ Delaying the resetting of stop_soon until after symbol loading
suppresses the warning. */
solib_add ((char *) 0, 0, (struct target_ops *) 0, auto_solib_add);
- stop_soon_quietly = 0;
+ stop_soon = NO_STOP_QUIETLY;
/* Enable breakpoints disabled (unnecessarily) by clear_solib(). */
re_enable_breakpoints_in_shlibs ();
out what we need to know about them. */
clear_proceed_status ();
- stop_soon_quietly = 1;
+ stop_soon = STOP_QUIETLY;
stop_signal = TARGET_SIGNAL_0;
do
{
wait_for_inferior ();
}
while (stop_signal != TARGET_SIGNAL_TRAP);
- stop_soon_quietly = 0;
+ stop_soon = NO_STOP_QUIETLY;
/* We are now either at the "mapping complete" breakpoint (or somewhere
else, a condition we aren't prepared to deal with anyway), so adjust
static struct link_map_offsets *svr4_fetch_link_map_offsets (void);
static struct link_map_offsets *legacy_fetch_link_map_offsets (void);
+static int svr4_have_link_map_offsets (void);
/* fetch_link_map_offsets_gdbarch_data is a handle used to obtain the
architecture specific link map offsets fetching function. */
/* Check to see if we have a currently valid address, and if so, avoid
doing all this work again and just return the cached address. If
we have no cached address, try to locate it in the dynamic info
- section for ELF executables. */
+ section for ELF executables. There's no point in doing any of this
+ though if we don't have some link map offsets to work with. */
- if (debug_base == 0)
+ if (debug_base == 0 && svr4_have_link_map_offsets ())
{
if (exec_bfd != NULL
&& bfd_get_flavour (exec_bfd) == bfd_target_elf_flavour)
/* Relocate the main executable if necessary. */
svr4_relocate_main_executable ();
+ if (!svr4_have_link_map_offsets ())
+ {
+ warning ("no shared library support for this OS / ABI");
+ return;
+
+ }
+
if (!enable_break ())
{
warning ("shared library handler failed to enable breakpoint");
out what we need to know about them. */
clear_proceed_status ();
- stop_soon_quietly = 1;
+ stop_soon = STOP_QUIETLY;
stop_signal = TARGET_SIGNAL_0;
do
{
wait_for_inferior ();
}
while (stop_signal != TARGET_SIGNAL_TRAP);
- stop_soon_quietly = 0;
+ stop_soon = NO_STOP_QUIETLY;
#endif /* defined(_SCO_DS) */
}
return (flmo ());
}
+/* Return 1 if a link map offset fetcher has been defined, 0 otherwise. */
+static int
+svr4_have_link_map_offsets (void)
+{
+ struct link_map_offsets *(*flmo)(void) =
+ gdbarch_data (current_gdbarch, fetch_link_map_offsets_gdbarch_data);
+ if (flmo == NULL
+ || (flmo == legacy_fetch_link_map_offsets
+ && legacy_svr4_fetch_link_map_offsets_hook == NULL))
+ return 0;
+ else
+ return 1;
+}
+
/* set_solib_svr4_fetch_link_map_offsets() is intended to be called by
a <arch>_gdbarch_init() function. It is used to establish an
architecture specific link_map_offsets fetcher for the architecture
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct objfile;
+
/* Critical offsets and sizes which describe struct r_debug and
struct link_map on SVR4-like targets. All offsets and sizes are
in bytes unless otherwise specified. */
#ifndef SOURCE_H
#define SOURCE_H
+struct symtab;
+
/* Open a source file given a symtab S. Returns a file descriptor or
negative number for error. */
extern int open_source_file (struct symtab *s);
/* Does the target have Floating Point registers? */
-#if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
-#define SPARC_HAS_FPU 0
-#else
-#define SPARC_HAS_FPU 1
+#if 0
+// OBSOLETE #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
+// OBSOLETE #define SPARC_HAS_FPU 0
+// OBSOLETE #else
+// OBSOLETE #define SPARC_HAS_FPU 1
+// OBSOLETE #endif
#endif
+#define SPARC_HAS_FPU 1
/* Number of bytes devoted to Floating Point registers: */
#if (GDB_TARGET_IS_SPARC64)
struct gdbarch_tdep
{
- int has_fpu;
+#if 0
+ // OBSOLETE int has_fpu;
+#endif
int fp_register_bytes;
int y_regnum;
int fp_max_regnum;
int deferred_stores = 0; /* Accumulated stores we want to do eventually. */
-/* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
- where instructions are big-endian and data are little-endian.
- This flag is set when we detect that the target is of this type. */
-
-int bi_endian = 0;
+#if 0
+// OBSOLETE /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
+// OBSOLETE where instructions are big-endian and data are little-endian.
+// OBSOLETE This flag is set when we detect that the target is of this type. */
+// OBSOLETE
+// OBSOLETE int bi_endian = 0;
+#endif
/* Fetch a single instruction. Even on bi-endian machines
about the chain value. If it really is zero, we detect it later
in sparc_init_prev_frame.
- Note: kevinb/2003-02-18: The constant 1 used to be returned
- here, but, after some recent changes to frame_chain_valid(),
- this value is no longer suitable for causing frame_chain_valid()
- to "not worry about the chain value." The constant ~0 (i.e,
- 0xfff...) causes the failing test in frame_chain_valid() to
- succeed thus preserving the "not worry" property. I had considered
- using something like ``get_frame_base (frame) + 1''. However, I think
- a constant value is better, because when debugging this problem,
- I knew that something funny was going on as soon as I saw the
- constant 1 being used as the frame chain elsewhere in GDB. */
+ Note: kevinb/2003-02-18: The constant 1 used to be returned here,
+ but, after some recent changes to legacy_frame_chain_valid(),
+ this value is no longer suitable for causing
+ legacy_frame_chain_valid() to "not worry about the chain value."
+ The constant ~0 (i.e, 0xfff...) causes the failing test in
+ legacy_frame_chain_valid() to succeed thus preserving the "not
+ worry" property. I had considered using something like
+ ``get_frame_base (frame) + 1''. However, I think a constant
+ value is better, because when debugging this problem, I knew that
+ something funny was going on as soon as I saw the constant 1
+ being used as the frame chain elsewhere in GDB. */
return ~ (CORE_ADDR) 0;
}
regnum, all);
}
-static void
-sparclet_print_registers_info (struct gdbarch *gdbarch,
- struct ui_file *file,
- struct frame_info *frame,
- int regnum, int print_all)
-{
- sparc_print_registers (gdbarch, file, frame, regnum, print_all, NULL);
-}
-
-void
-sparclet_do_registers_info (int regnum, int all)
-{
- sparclet_print_registers_info (current_gdbarch, gdb_stdout,
- deprecated_selected_frame, regnum, all);
-}
+#if 0
+// OBSOLETE static void
+// OBSOLETE sparclet_print_registers_info (struct gdbarch *gdbarch,
+// OBSOLETE struct ui_file *file,
+// OBSOLETE struct frame_info *frame,
+// OBSOLETE int regnum, int print_all)
+// OBSOLETE {
+// OBSOLETE sparc_print_registers (gdbarch, file, frame, regnum, print_all, NULL);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE sparclet_do_registers_info (int regnum, int all)
+// OBSOLETE {
+// OBSOLETE sparclet_print_registers_info (current_gdbarch, gdb_stdout,
+// OBSOLETE deprecated_selected_frame, regnum, all);
+// OBSOLETE }
+#endif
\f
int
TYPE_LENGTH (type));
}
-extern void
-sparclet_store_return_value (struct type *type, char *valbuf)
-{
- /* Other values are returned in register %o0. */
- deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), valbuf,
- TYPE_LENGTH (type));
-}
+#if 0
+// OBSOLETE extern void
+// OBSOLETE sparclet_store_return_value (struct type *type, char *valbuf)
+// OBSOLETE {
+// OBSOLETE /* Other values are returned in register %o0. */
+// OBSOLETE deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), valbuf,
+// OBSOLETE TYPE_LENGTH (type));
+// OBSOLETE }
+#endif
#ifndef CALL_DUMMY_CALL_OFFSET
}
}
- /* If this is a bi-endian target, GDB has written the call dummy
- in little-endian order. We must byte-swap it back to big-endian. */
- if (bi_endian)
- {
- for (i = 0; i < CALL_DUMMY_LENGTH; i += 4)
- {
- char tmp = dummy[i];
- dummy[i] = dummy[i + 3];
- dummy[i + 3] = tmp;
- tmp = dummy[i + 1];
- dummy[i + 1] = dummy[i + 2];
- dummy[i + 2] = tmp;
- }
- }
+#if 0
+// OBSOLETE /* If this is a bi-endian target, GDB has written the call dummy
+// OBSOLETE in little-endian order. We must byte-swap it back to big-endian. */
+// OBSOLETE if (bi_endian)
+// OBSOLETE {
+// OBSOLETE for (i = 0; i < CALL_DUMMY_LENGTH; i += 4)
+// OBSOLETE {
+// OBSOLETE char tmp = dummy[i];
+// OBSOLETE dummy[i] = dummy[i + 3];
+// OBSOLETE dummy[i + 3] = tmp;
+// OBSOLETE tmp = dummy[i + 1];
+// OBSOLETE dummy[i + 1] = dummy[i + 2];
+// OBSOLETE dummy[i + 2] = tmp;
+// OBSOLETE }
+// OBSOLETE }
+#endif
}
-/* Set target byte order based on machine type. */
-
-static int
-sparc_target_architecture_hook (const bfd_arch_info_type *ap)
-{
- int i, j;
-
- if (ap->mach == bfd_mach_sparc_sparclite_le)
- {
- target_byte_order = BFD_ENDIAN_LITTLE;
- bi_endian = 1;
- }
- else
- bi_endian = 0;
- return 1;
-}
-\f
+#if 0
+// OBSOLETE /* Set target byte order based on machine type. */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE sparc_target_architecture_hook (const bfd_arch_info_type *ap)
+// OBSOLETE {
+// OBSOLETE int i, j;
+// OBSOLETE
+// OBSOLETE if (ap->mach == bfd_mach_sparc_sparclite_le)
+// OBSOLETE {
+// OBSOLETE target_byte_order = BFD_ENDIAN_LITTLE;
+// OBSOLETE bi_endian = 1;
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE bi_endian = 0;
+// OBSOLETE return 1;
+// OBSOLETE }
+#endif
/*
* Module "constructor" function.
tm_print_insn = gdb_print_insn_sparc;
tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */
- target_architecture_hook = sparc_target_architecture_hook;
+ /* OBSOLETE target_architecture_hook = sparc_target_architecture_hook; */
}
/* Compensate for stack bias. Note that we currently don't handle
sp64_extract_return_value (type, regbuf, valbuf, 0);
}
-extern void
-sparclet_extract_return_value (struct type *type,
- char *regbuf,
- char *valbuf)
-{
- regbuf += REGISTER_RAW_SIZE (O0_REGNUM) * 8;
- if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (O0_REGNUM))
- regbuf += REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH (type);
-
- memcpy ((void *) valbuf, regbuf, TYPE_LENGTH (type));
-}
-
+#if 0
+// OBSOLETE extern void
+// OBSOLETE sparclet_extract_return_value (struct type *type,
+// OBSOLETE char *regbuf,
+// OBSOLETE char *valbuf)
+// OBSOLETE {
+// OBSOLETE regbuf += REGISTER_RAW_SIZE (O0_REGNUM) * 8;
+// OBSOLETE if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (O0_REGNUM))
+// OBSOLETE regbuf += REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH (type);
+// OBSOLETE
+// OBSOLETE memcpy ((void *) valbuf, regbuf, TYPE_LENGTH (type));
+// OBSOLETE }
+#endif
extern CORE_ADDR
sparc32_stack_align (CORE_ADDR addr)
return register_names[regno];
}
-static const char *
-sparclite_register_name (int regno)
-{
- static char *register_names[] =
- { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
-
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
- "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
-
- "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
- "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
- };
-
- if (regno < 0 ||
- regno >= (sizeof (register_names) / sizeof (register_names[0])))
- return NULL;
- else
- return register_names[regno];
-}
-
-static const char *
-sparclet_register_name (int regno)
-{
- static char *register_names[] =
- { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
-
- "", "", "", "", "", "", "", "", /* no floating point registers */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
-
- "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
- "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
-
- /* ASR15 ASR19 (don't display them) */
- "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
- /* None of the rest get displayed */
#if 0
- "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
- "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
- "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
- "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
- "apsr"
-#endif /* 0 */
- };
+// OBSOLETE static const char *
+// OBSOLETE sparclite_register_name (int regno)
+// OBSOLETE {
+// OBSOLETE static char *register_names[] =
+// OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+// OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+// OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+// OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+// OBSOLETE
+// OBSOLETE "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+// OBSOLETE "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+// OBSOLETE "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+// OBSOLETE "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+// OBSOLETE
+// OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
+// OBSOLETE "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE if (regno < 0 ||
+// OBSOLETE regno >= (sizeof (register_names) / sizeof (register_names[0])))
+// OBSOLETE return NULL;
+// OBSOLETE else
+// OBSOLETE return register_names[regno];
+// OBSOLETE }
+#endif
- if (regno < 0 ||
- regno >= (sizeof (register_names) / sizeof (register_names[0])))
- return NULL;
- else
- return register_names[regno];
-}
+#if 0
+// OBSOLETE static const char *
+// OBSOLETE sparclet_register_name (int regno)
+// OBSOLETE {
+// OBSOLETE static char *register_names[] =
+// OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+// OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+// OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+// OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+// OBSOLETE
+// OBSOLETE "", "", "", "", "", "", "", "", /* no floating point registers */
+// OBSOLETE "", "", "", "", "", "", "", "",
+// OBSOLETE "", "", "", "", "", "", "", "",
+// OBSOLETE "", "", "", "", "", "", "", "",
+// OBSOLETE
+// OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
+// OBSOLETE "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
+// OBSOLETE
+// OBSOLETE /* ASR15 ASR19 (don't display them) */
+// OBSOLETE "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
+// OBSOLETE /* None of the rest get displayed */
+// OBSOLETE #if 0
+// OBSOLETE "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
+// OBSOLETE "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
+// OBSOLETE "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
+// OBSOLETE "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
+// OBSOLETE "apsr"
+// OBSOLETE #endif /* 0 */
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE if (regno < 0 ||
+// OBSOLETE regno >= (sizeof (register_names) / sizeof (register_names[0])))
+// OBSOLETE return NULL;
+// OBSOLETE else
+// OBSOLETE return register_names[regno];
+// OBSOLETE }
+#endif
CORE_ADDR
sparc_push_return_address (CORE_ADDR pc_unused, CORE_ADDR sp)
generic_register_convertible_not);
set_gdbarch_reg_struct_has_addr (gdbarch, sparc_reg_struct_has_addr);
set_gdbarch_return_value_on_stack (gdbarch, sparc_return_value_on_stack);
- set_gdbarch_saved_pc_after_call (gdbarch, sparc_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sparc_saved_pc_after_call);
set_gdbarch_prologue_frameless_p (gdbarch, sparc_prologue_frameless_p);
set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
set_gdbarch_skip_prologue (gdbarch, sparc_skip_prologue);
switch (info.bfd_arch_info->mach)
{
case bfd_mach_sparc:
- case bfd_mach_sparc_sparclet:
- case bfd_mach_sparc_sparclite:
+#if 0
+ // OBSOLETE case bfd_mach_sparc_sparclet:
+ // OBSOLETE case bfd_mach_sparc_sparclite:
+#endif
case bfd_mach_sparc_v8plus:
case bfd_mach_sparc_v8plusa:
- case bfd_mach_sparc_sparclite_le:
+#if 0
+ // OBSOLETE case bfd_mach_sparc_sparclite_le:
+#endif
/* 32-bit machine types: */
#ifdef SPARC32_CALL_DUMMY_ON_STACK
set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4);
set_gdbarch_register_name (gdbarch, sparc32_register_name);
set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
- tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#if 0
+ // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#endif
tdep->fp_register_bytes = 32 * 4;
tdep->print_insn_mach = bfd_mach_sparc;
break;
- case bfd_mach_sparc_sparclet:
- set_gdbarch_deprecated_extract_return_value (gdbarch, sparclet_extract_return_value);
- set_gdbarch_num_regs (gdbarch, 32 + 32 + 8 + 8 + 8);
- set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
- set_gdbarch_register_name (gdbarch, sparclet_register_name);
- set_gdbarch_deprecated_store_return_value (gdbarch, sparclet_store_return_value);
- tdep->has_fpu = 0; /* (all but sparclet and sparclite) */
- tdep->fp_register_bytes = 0;
- tdep->print_insn_mach = bfd_mach_sparc_sparclet;
- break;
- case bfd_mach_sparc_sparclite:
- set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value);
- set_gdbarch_num_regs (gdbarch, 80);
- set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4);
- set_gdbarch_register_name (gdbarch, sparclite_register_name);
- set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
- tdep->has_fpu = 0; /* (all but sparclet and sparclite) */
- tdep->fp_register_bytes = 0;
- tdep->print_insn_mach = bfd_mach_sparc_sparclite;
- break;
+#if 0
+ // OBSOLETE case bfd_mach_sparc_sparclet:
+ // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparclet_extract_return_value);
+ // OBSOLETE set_gdbarch_num_regs (gdbarch, 32 + 32 + 8 + 8 + 8);
+ // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
+ // OBSOLETE set_gdbarch_register_name (gdbarch, sparclet_register_name);
+ // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparclet_store_return_value);
+ // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */
+ // OBSOLETE tdep->fp_register_bytes = 0;
+ // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclet;
+ // OBSOLETE break;
+#endif
+#if 0
+ // OBSOLETE case bfd_mach_sparc_sparclite:
+ // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value);
+ // OBSOLETE set_gdbarch_num_regs (gdbarch, 80);
+ // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4);
+ // OBSOLETE set_gdbarch_register_name (gdbarch, sparclite_register_name);
+ // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
+ // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */
+ // OBSOLETE tdep->fp_register_bytes = 0;
+ // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclite;
+ // OBSOLETE break;
+#endif
case bfd_mach_sparc_v8plus:
set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value);
set_gdbarch_num_regs (gdbarch, 72);
set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
tdep->print_insn_mach = bfd_mach_sparc;
tdep->fp_register_bytes = 32 * 4;
- tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#if 0
+ // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#endif
break;
case bfd_mach_sparc_v8plusa:
set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value);
set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4);
set_gdbarch_register_name (gdbarch, sparc32_register_name);
set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
- tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#if 0
+ // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#endif
tdep->fp_register_bytes = 32 * 4;
tdep->print_insn_mach = bfd_mach_sparc;
break;
- case bfd_mach_sparc_sparclite_le:
- set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value);
- set_gdbarch_num_regs (gdbarch, 80);
- set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4);
- set_gdbarch_register_name (gdbarch, sparclite_register_name);
- set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
- tdep->has_fpu = 0; /* (all but sparclet and sparclite) */
- tdep->fp_register_bytes = 0;
- tdep->print_insn_mach = bfd_mach_sparc_sparclite;
- break;
+#if 0
+// OBSOLETE case bfd_mach_sparc_sparclite_le:
+// OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value);
+// OBSOLETE set_gdbarch_num_regs (gdbarch, 80);
+// OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4);
+// OBSOLETE set_gdbarch_register_name (gdbarch, sparclite_register_name);
+// OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
+// OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */
+// OBSOLETE tdep->fp_register_bytes = 0;
+// OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclite;
+// OBSOLETE break;
+#endif
case bfd_mach_sparc_v9:
set_gdbarch_deprecated_extract_return_value (gdbarch, sparc64_extract_return_value);
set_gdbarch_num_regs (gdbarch, 125);
set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8);
set_gdbarch_register_name (gdbarch, sparc64_register_name);
set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
- tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#if 0
+ // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#endif
tdep->fp_register_bytes = 64 * 4;
tdep->print_insn_mach = bfd_mach_sparc_v9a;
break;
set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8);
set_gdbarch_register_name (gdbarch, sparc64_register_name);
set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value);
- tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#if 0
+ // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */
+#endif
tdep->fp_register_bytes = 64 * 4;
tdep->print_insn_mach = bfd_mach_sparc_v9a;
break;
if (tdep == NULL)
return;
- fprintf_unfiltered (file, "sparc_dump_tdep: has_fpu = %d\n",
- tdep->has_fpu);
+#if 0
+ // OBSOLETE fprintf_unfiltered (file, "sparc_dump_tdep: has_fpu = %d\n",
+ // OBSOLETE tdep->has_fpu);
+#endif
fprintf_unfiltered (file, "sparc_dump_tdep: fp_register_bytes = %d\n",
tdep->fp_register_bytes);
fprintf_unfiltered (file, "sparc_dump_tdep: y_regnum = %d\n",
-/****************************************************************************
-
- THIS SOFTWARE IS NOT COPYRIGHTED
-
- HP offers the following for use in the public domain. HP makes no
- warranty with regard to the software or it's performance and the
- user accepts the software "AS IS" with all faults.
-
- HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
- TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-
-****************************************************************************/
-
-/****************************************************************************
- * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
- *
- * Module name: remcom.c $
- * Revision: 1.34 $
- * Date: 91/03/09 12:29:49 $
- * Contributor: Lake Stevens Instrument Division$
- *
- * Description: low level support for gdb debugger. $
- *
- * Considerations: only works on target hardware $
- *
- * Written by: Glenn Engel $
- * ModuleState: Experimental $
- *
- * NOTES: See Below $
- *
- * Modified for SPARC by Stu Grossman, Cygnus Support.
- * Based on sparc-stub.c, it's modified for SPARClite Debug Unit hardware
- * breakpoint support to create sparclite-stub.c, by Kung Hsu, Cygnus Support.
- *
- * This code has been extensively tested on the Fujitsu SPARClite demo board.
- *
- * To enable debugger support, two things need to happen. One, a
- * call to set_debug_traps() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint(). Breakpoint()
- * simulates a breakpoint by executing a trap #1.
- *
- *************
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- * P set the value of a single CPU register OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- ****************************************************************************/
-
-#include <string.h>
-#include <signal.h>
-#include <sparclite.h>
-
-/************************************************************************
- *
- * external low-level support routines
- */
-
-extern void putDebugChar (int c); /* write a single character */
-extern int getDebugChar (void); /* read and return a single char */
-
-/************************************************************************/
-/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
-/* at least NUMREGBYTES*2 are needed for register packets */
-#define BUFMAX 2048
-
-static int initialized = 0; /* !0 means we've been initialized */
-
-extern void breakinst ();
-static void set_mem_fault_trap (int enable);
-static void get_in_break_mode (void);
-
-static const char hexchars[]="0123456789abcdef";
-
-#define NUMREGS 80
-
-/* Number of bytes of registers. */
-#define NUMREGBYTES (NUMREGS * 4)
-enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
- O0, O1, O2, O3, O4, O5, SP, O7,
- L0, L1, L2, L3, L4, L5, L6, L7,
- I0, I1, I2, I3, I4, I5, FP, I7,
-
- F0, F1, F2, F3, F4, F5, F6, F7,
- F8, F9, F10, F11, F12, F13, F14, F15,
- F16, F17, F18, F19, F20, F21, F22, F23,
- F24, F25, F26, F27, F28, F29, F30, F31,
- Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR,
- DIA1, DIA2, DDA1, DDA2, DDV1, DDV2, DCR, DSR };
-
-/*************************** ASSEMBLY CODE MACROS *************************/
-/* */
-
-extern void trap_low();
-
-/* Create private copies of common functions used by the stub. This prevents
- nasty interactions between app code and the stub (for instance if user steps
- into strlen, etc..) */
-
-static char *
-strcpy (char *dst, const char *src)
-{
- char *retval = dst;
-
- while ((*dst++ = *src++) != '\000');
-
- return retval;
-}
-
-static void *
-memcpy (void *vdst, const void *vsrc, int n)
-{
- char *dst = vdst;
- const char *src = vsrc;
- char *retval = dst;
-
- while (n-- > 0)
- *dst++ = *src++;
-
- return retval;
-}
-
-asm("
- .reserve trapstack, 1000 * 4, \"bss\", 8
-
- .data
- .align 4
-
-in_trap_handler:
- .word 0
-
- .text
- .align 4
-
-! This function is called when any SPARC trap (except window overflow or
-! underflow) occurs. It makes sure that the invalid register window is still
-! available before jumping into C code. It will also restore the world if you
-! return from handle_exception.
-!
-! On entry, trap_low expects l1 and l2 to contain pc and npc respectivly.
-! Register usage throughout the routine is as follows:
-!
-! l0 - psr
-! l1 - pc
-! l2 - npc
-! l3 - wim
-! l4 - scratch and y reg
-! l5 - scratch and tbr
-! l6 - unused
-! l7 - unused
-
- .globl _trap_low
-_trap_low:
- mov %psr, %l0
- mov %wim, %l3
-
- srl %l3, %l0, %l4 ! wim >> cwp
- cmp %l4, 1
- bne window_fine ! Branch if not in the invalid window
- nop
-
-! Handle window overflow
-
- mov %g1, %l4 ! Save g1, we use it to hold the wim
- srl %l3, 1, %g1 ! Rotate wim right
- tst %g1
- bg good_wim ! Branch if new wim is non-zero
- nop
-
-! At this point, we need to bring a 1 into the high order bit of the wim.
-! Since we don't want to make any assumptions about the number of register
-! windows, we figure it out dynamically so as to setup the wim correctly.
-
- not %g1 ! Fill g1 with ones
- mov %g1, %wim ! Fill the wim with ones
- nop
- nop
- nop
- mov %wim, %g1 ! Read back the wim
- inc %g1 ! Now g1 has 1 just to left of wim
- srl %g1, 1, %g1 ! Now put 1 at top of wim
- mov %g0, %wim ! Clear wim so that subsequent save
- nop ! won't trap
- nop
- nop
-
-good_wim:
- save %g0, %g0, %g0 ! Slip into next window
- mov %g1, %wim ! Install the new wim
-
- std %l0, [%sp + 0 * 4] ! save L & I registers
- std %l2, [%sp + 2 * 4]
- std %l4, [%sp + 4 * 4]
- std %l6, [%sp + 6 * 4]
-
- std %i0, [%sp + 8 * 4]
- std %i2, [%sp + 10 * 4]
- std %i4, [%sp + 12 * 4]
- std %i6, [%sp + 14 * 4]
-
- restore ! Go back to trap window.
- mov %l4, %g1 ! Restore %g1
-
-window_fine:
- sethi %hi(in_trap_handler), %l4
- ld [%lo(in_trap_handler) + %l4], %l5
- tst %l5
- bg recursive_trap
- inc %l5
-
- set trapstack+1000*4, %sp ! Switch to trap stack
-
-recursive_trap:
- st %l5, [%lo(in_trap_handler) + %l4]
- sub %sp,(16+1+6+1+80)*4,%sp ! Make room for input & locals
- ! + hidden arg + arg spill
- ! + doubleword alignment
- ! + registers[72] local var
-
- std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
- std %g2, [%sp + (24 + 2) * 4]
- std %g4, [%sp + (24 + 4) * 4]
- std %g6, [%sp + (24 + 6) * 4]
-
- std %i0, [%sp + (24 + 8) * 4] ! registers[Ox]
- std %i2, [%sp + (24 + 10) * 4]
- std %i4, [%sp + (24 + 12) * 4]
- std %i6, [%sp + (24 + 14) * 4]
-
- mov %y, %l4
- mov %tbr, %l5
- st %l4, [%sp + (24 + 64) * 4] ! Y
- st %l0, [%sp + (24 + 65) * 4] ! PSR
- st %l3, [%sp + (24 + 66) * 4] ! WIM
- st %l5, [%sp + (24 + 67) * 4] ! TBR
- st %l1, [%sp + (24 + 68) * 4] ! PC
- st %l2, [%sp + (24 + 69) * 4] ! NPC
-
- or %l0, 0xf20, %l4
- mov %l4, %psr ! Turn on traps, disable interrupts
-
- set 0x1000, %l1
- btst %l1, %l0 ! FP enabled?
- be no_fpstore
- nop
-
-! Must save fsr first, to flush the FQ. This may cause a deferred fp trap, so
-! traps must be enabled to allow the trap handler to clean things up.
-
- st %fsr, [%sp + (24 + 70) * 4]
-
- std %f0, [%sp + (24 + 32) * 4]
- std %f2, [%sp + (24 + 34) * 4]
- std %f4, [%sp + (24 + 36) * 4]
- std %f6, [%sp + (24 + 38) * 4]
- std %f8, [%sp + (24 + 40) * 4]
- std %f10, [%sp + (24 + 42) * 4]
- std %f12, [%sp + (24 + 44) * 4]
- std %f14, [%sp + (24 + 46) * 4]
- std %f16, [%sp + (24 + 48) * 4]
- std %f18, [%sp + (24 + 50) * 4]
- std %f20, [%sp + (24 + 52) * 4]
- std %f22, [%sp + (24 + 54) * 4]
- std %f24, [%sp + (24 + 56) * 4]
- std %f26, [%sp + (24 + 58) * 4]
- std %f28, [%sp + (24 + 60) * 4]
- std %f30, [%sp + (24 + 62) * 4]
-no_fpstore:
-
- call _handle_exception
- add %sp, 24 * 4, %o0 ! Pass address of registers
-
-! Reload all of the registers that aren't on the stack
-
- ld [%sp + (24 + 1) * 4], %g1 ! registers[Gx]
- ldd [%sp + (24 + 2) * 4], %g2
- ldd [%sp + (24 + 4) * 4], %g4
- ldd [%sp + (24 + 6) * 4], %g6
-
- ldd [%sp + (24 + 8) * 4], %i0 ! registers[Ox]
- ldd [%sp + (24 + 10) * 4], %i2
- ldd [%sp + (24 + 12) * 4], %i4
- ldd [%sp + (24 + 14) * 4], %i6
-
-
- ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
- ldd [%sp + (24 + 68) * 4], %l2 ! PC & NPC
-
- set 0x1000, %l5
- btst %l5, %l1 ! FP enabled?
- be no_fpreload
- nop
-
- ldd [%sp + (24 + 32) * 4], %f0
- ldd [%sp + (24 + 34) * 4], %f2
- ldd [%sp + (24 + 36) * 4], %f4
- ldd [%sp + (24 + 38) * 4], %f6
- ldd [%sp + (24 + 40) * 4], %f8
- ldd [%sp + (24 + 42) * 4], %f10
- ldd [%sp + (24 + 44) * 4], %f12
- ldd [%sp + (24 + 46) * 4], %f14
- ldd [%sp + (24 + 48) * 4], %f16
- ldd [%sp + (24 + 50) * 4], %f18
- ldd [%sp + (24 + 52) * 4], %f20
- ldd [%sp + (24 + 54) * 4], %f22
- ldd [%sp + (24 + 56) * 4], %f24
- ldd [%sp + (24 + 58) * 4], %f26
- ldd [%sp + (24 + 60) * 4], %f28
- ldd [%sp + (24 + 62) * 4], %f30
-
- ld [%sp + (24 + 70) * 4], %fsr
-no_fpreload:
-
- restore ! Ensure that previous window is valid
- save %g0, %g0, %g0 ! by causing a window_underflow trap
-
- mov %l0, %y
- mov %l1, %psr ! Make sure that traps are disabled
- ! for rett
- sethi %hi(in_trap_handler), %l4
- ld [%lo(in_trap_handler) + %l4], %l5
- dec %l5
- st %l5, [%lo(in_trap_handler) + %l4]
-
- jmpl %l2, %g0 ! Restore old PC
- rett %l3 ! Restore old nPC
-");
-
-/* Convert ch from a hex digit to an int */
-
-static int
-hex (unsigned char ch)
-{
- if (ch >= 'a' && ch <= 'f')
- return ch-'a'+10;
- if (ch >= '0' && ch <= '9')
- return ch-'0';
- if (ch >= 'A' && ch <= 'F')
- return ch-'A'+10;
- return -1;
-}
-
-static char remcomInBuffer[BUFMAX];
-static char remcomOutBuffer[BUFMAX];
-
-/* scan for the sequence $<data>#<checksum> */
-
-unsigned char *
-getpacket (void)
-{
- unsigned char *buffer = &remcomInBuffer[0];
- unsigned char checksum;
- unsigned char xmitcsum;
- int count;
- char ch;
-
- while (1)
- {
- /* wait around for the start character, ignore all other characters */
- while ((ch = getDebugChar ()) != '$')
- ;
-
-retry:
- checksum = 0;
- xmitcsum = -1;
- count = 0;
-
- /* now, read until a # or end of buffer is found */
- while (count < BUFMAX)
- {
- ch = getDebugChar ();
- if (ch == '$')
- goto retry;
- if (ch == '#')
- break;
- checksum = checksum + ch;
- buffer[count] = ch;
- count = count + 1;
- }
- buffer[count] = 0;
-
- if (ch == '#')
- {
- ch = getDebugChar ();
- xmitcsum = hex (ch) << 4;
- ch = getDebugChar ();
- xmitcsum += hex (ch);
-
- if (checksum != xmitcsum)
- {
- putDebugChar ('-'); /* failed checksum */
- }
- else
- {
- putDebugChar ('+'); /* successful transfer */
-
- /* if a sequence char is present, reply the sequence ID */
- if (buffer[2] == ':')
- {
- putDebugChar (buffer[0]);
- putDebugChar (buffer[1]);
-
- return &buffer[3];
- }
-
- return &buffer[0];
- }
- }
- }
-}
-
-/* send the packet in buffer. */
-
-static void
-putpacket (unsigned char *buffer)
-{
- unsigned char checksum;
- int count;
- unsigned char ch;
-
- /* $<packet info>#<checksum>. */
- do
- {
- putDebugChar('$');
- checksum = 0;
- count = 0;
-
- while (ch = buffer[count])
- {
- putDebugChar (ch);
- checksum += ch;
- count += 1;
- }
-
- putDebugChar('#');
- putDebugChar(hexchars[checksum >> 4]);
- putDebugChar(hexchars[checksum & 0xf]);
-
- }
- while (getDebugChar() != '+');
-}
-
-/* Indicate to caller of mem2hex or hex2mem that there has been an
- error. */
-static volatile int mem_err = 0;
-
-/* Convert the memory pointed to by mem into hex, placing result in buf.
- * Return a pointer to the last char put in buf (null), in case of mem fault,
- * return 0.
- * If MAY_FAULT is non-zero, then we will handle memory faults by returning
- * a 0, else treat a fault like any other fault in the stub.
- */
-
-static unsigned char *
-mem2hex (unsigned char *mem, unsigned char *buf, int count, int may_fault)
-{
- unsigned char ch;
-
- set_mem_fault_trap(may_fault);
-
- while (count-- > 0)
- {
- ch = *mem++;
- if (mem_err)
- return 0;
- *buf++ = hexchars[ch >> 4];
- *buf++ = hexchars[ch & 0xf];
- }
-
- *buf = 0;
-
- set_mem_fault_trap(0);
-
- return buf;
-}
-
-/* convert the hex array pointed to by buf into binary to be placed in mem
- * return a pointer to the character AFTER the last byte written */
-
-static char *
-hex2mem (unsigned char *buf, unsigned char *mem, int count, int may_fault)
-{
- int i;
- unsigned char ch;
-
- set_mem_fault_trap(may_fault);
-
- for (i=0; i<count; i++)
- {
- ch = hex(*buf++) << 4;
- ch |= hex(*buf++);
- *mem++ = ch;
- if (mem_err)
- return 0;
- }
-
- set_mem_fault_trap(0);
-
- return mem;
-}
-
-/* This table contains the mapping between SPARC hardware trap types, and
- signals, which are primarily what GDB understands. It also indicates
- which hardware traps we need to commandeer when initializing the stub. */
-
-static struct hard_trap_info
-{
- unsigned char tt; /* Trap type code for SPARClite */
- unsigned char signo; /* Signal that we map this trap into */
-} hard_trap_info[] = {
- {0x01, SIGSEGV}, /* instruction access error */
- {0x02, SIGILL}, /* privileged instruction */
- {0x03, SIGILL}, /* illegal instruction */
- {0x04, SIGEMT}, /* fp disabled */
- {0x07, SIGBUS}, /* mem address not aligned */
- {0x09, SIGSEGV}, /* data access exception */
- {0x0a, SIGEMT}, /* tag overflow */
- {0x20, SIGBUS}, /* r register access error */
- {0x21, SIGBUS}, /* instruction access error */
- {0x24, SIGEMT}, /* cp disabled */
- {0x29, SIGBUS}, /* data access error */
- {0x2a, SIGFPE}, /* divide by zero */
- {0x2b, SIGBUS}, /* data store error */
- {0x80+1, SIGTRAP}, /* ta 1 - normal breakpoint instruction */
- {0xff, SIGTRAP}, /* hardware breakpoint */
- {0, 0} /* Must be last */
-};
-
-/* Set up exception handlers for tracing and breakpoints */
-
-void
-set_debug_traps (void)
-{
- struct hard_trap_info *ht;
-
-/* Only setup fp traps if the FP is disabled. */
-
- for (ht = hard_trap_info;
- ht->tt != 0 && ht->signo != 0;
- ht++)
- if (ht->tt != 4 || ! (read_psr () & 0x1000))
- exceptionHandler(ht->tt, trap_low);
-
- initialized = 1;
-}
-
-asm ("
-! Trap handler for memory errors. This just sets mem_err to be non-zero. It
-! assumes that %l1 is non-zero. This should be safe, as it is doubtful that
-! 0 would ever contain code that could mem fault. This routine will skip
-! past the faulting instruction after setting mem_err.
-
- .text
- .align 4
-
-_fltr_set_mem_err:
- sethi %hi(_mem_err), %l0
- st %l1, [%l0 + %lo(_mem_err)]
- jmpl %l2, %g0
- rett %l2+4
-");
-
-static void
-set_mem_fault_trap (int enable)
-{
- extern void fltr_set_mem_err();
- mem_err = 0;
-
- if (enable)
- exceptionHandler(9, fltr_set_mem_err);
- else
- exceptionHandler(9, trap_low);
-}
-
-asm ("
- .text
- .align 4
-
-_dummy_hw_breakpoint:
- jmpl %l2, %g0
- rett %l2+4
- nop
- nop
-");
-
-static void
-get_in_break_mode (void)
-{
- extern void dummy_hw_breakpoint();
-
- exceptionHandler (255, dummy_hw_breakpoint);
-
- asm ("ta 255");
-
- exceptionHandler (255, trap_low);
-}
-
-/* Convert the SPARC hardware trap type code to a unix signal number. */
-
-static int
-computeSignal (int tt)
-{
- struct hard_trap_info *ht;
-
- for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
- if (ht->tt == tt)
- return ht->signo;
-
- return SIGHUP; /* default for things we don't know about */
-}
-
-/*
- * While we find nice hex chars, build an int.
- * Return number of chars processed.
- */
-
-static int
-hexToInt(char **ptr, int *intValue)
-{
- int numChars = 0;
- int hexValue;
-
- *intValue = 0;
-
- while (**ptr)
- {
- hexValue = hex(**ptr);
- if (hexValue < 0)
- break;
-
- *intValue = (*intValue << 4) | hexValue;
- numChars ++;
-
- (*ptr)++;
- }
-
- return (numChars);
-}
-
-/*
- * This function does all command procesing for interfacing to gdb. It
- * returns 1 if you should skip the instruction at the trap address, 0
- * otherwise.
- */
-
-static void
-handle_exception (unsigned long *registers)
-{
- int tt; /* Trap type */
- int sigval;
- int addr;
- int length;
- char *ptr;
- unsigned long *sp;
- unsigned long dsr;
-
-/* First, we must force all of the windows to be spilled out */
-
- asm(" save %sp, -64, %sp
- save %sp, -64, %sp
- save %sp, -64, %sp
- save %sp, -64, %sp
- save %sp, -64, %sp
- save %sp, -64, %sp
- save %sp, -64, %sp
- save %sp, -64, %sp
- restore
- restore
- restore
- restore
- restore
- restore
- restore
- restore
-");
-
- get_in_break_mode (); /* Enable DSU register writes */
-
- registers[DIA1] = read_asi (1, 0xff00);
- registers[DIA2] = read_asi (1, 0xff04);
- registers[DDA1] = read_asi (1, 0xff08);
- registers[DDA2] = read_asi (1, 0xff0c);
- registers[DDV1] = read_asi (1, 0xff10);
- registers[DDV2] = read_asi (1, 0xff14);
- registers[DCR] = read_asi (1, 0xff18);
- registers[DSR] = read_asi (1, 0xff1c);
-
- if (registers[PC] == (unsigned long)breakinst)
- {
- registers[PC] = registers[NPC];
- registers[NPC] += 4;
- }
- sp = (unsigned long *)registers[SP];
-
- dsr = (unsigned long)registers[DSR];
- if (dsr & 0x3c)
- tt = 255;
- else
- tt = (registers[TBR] >> 4) & 0xff;
-
- /* reply to host that an exception has occurred */
- sigval = computeSignal(tt);
- ptr = remcomOutBuffer;
-
- *ptr++ = 'T';
- *ptr++ = hexchars[sigval >> 4];
- *ptr++ = hexchars[sigval & 0xf];
-
- *ptr++ = hexchars[PC >> 4];
- *ptr++ = hexchars[PC & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)®isters[PC], ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = hexchars[FP >> 4];
- *ptr++ = hexchars[FP & 0xf];
- *ptr++ = ':';
- ptr = mem2hex(sp + 8 + 6, ptr, 4, 0); /* FP */
- *ptr++ = ';';
-
- *ptr++ = hexchars[SP >> 4];
- *ptr++ = hexchars[SP & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)&sp, ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = hexchars[NPC >> 4];
- *ptr++ = hexchars[NPC & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)®isters[NPC], ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = hexchars[O7 >> 4];
- *ptr++ = hexchars[O7 & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)®isters[O7], ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = 0;
-
- putpacket(remcomOutBuffer);
-
- while (1)
- {
- remcomOutBuffer[0] = 0;
-
- ptr = getpacket();
- switch (*ptr++)
- {
- case '?':
- remcomOutBuffer[0] = 'S';
- remcomOutBuffer[1] = hexchars[sigval >> 4];
- remcomOutBuffer[2] = hexchars[sigval & 0xf];
- remcomOutBuffer[3] = 0;
- break;
-
- case 'd':
- /* toggle debug flag */
- break;
-
- case 'g': /* return the value of the CPU registers */
- memcpy (®isters[L0], sp, 16 * 4); /* Copy L & I regs from stack */
- mem2hex ((char *)registers, remcomOutBuffer, NUMREGBYTES, 0);
- break;
-
- case 'G': /* Set the value of all registers */
- case 'P': /* Set the value of one register */
- {
- unsigned long *newsp, psr;
-
- psr = registers[PSR];
-
- if (ptr[-1] == 'P')
- {
- int regno;
-
- if (hexToInt (&ptr, ®no)
- && *ptr++ == '=')
- if (regno >= L0 && regno <= I7)
- hex2mem (ptr, sp + regno - L0, 4, 0);
- else
- hex2mem (ptr, (char *)®isters[regno], 4, 0);
- else
- {
- strcpy (remcomOutBuffer, "E01");
- break;
- }
- }
- else
- {
- hex2mem (ptr, (char *)registers, NUMREGBYTES, 0);
- memcpy (sp, ®isters[L0], 16 * 4); /* Copy L & I regs to stack */
- }
-
- /* See if the stack pointer has moved. If so, then copy the saved
- locals and ins to the new location. This keeps the window
- overflow and underflow routines happy. */
-
- newsp = (unsigned long *)registers[SP];
- if (sp != newsp)
- sp = memcpy(newsp, sp, 16 * 4);
-
- /* Don't allow CWP to be modified. */
-
- if (psr != registers[PSR])
- registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f);
-
- strcpy(remcomOutBuffer,"OK");
- }
- break;
-
- case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
- /* Try to read %x,%x. */
-
- if (hexToInt(&ptr, &addr)
- && *ptr++ == ','
- && hexToInt(&ptr, &length))
- {
- if (mem2hex((char *)addr, remcomOutBuffer, length, 1))
- break;
-
- strcpy (remcomOutBuffer, "E03");
- }
- else
- strcpy(remcomOutBuffer,"E01");
- break;
-
- case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
- /* Try to read '%x,%x:'. */
-
- if (hexToInt(&ptr, &addr)
- && *ptr++ == ','
- && hexToInt(&ptr, &length)
- && *ptr++ == ':')
- {
- if (hex2mem(ptr, (char *)addr, length, 1))
- strcpy(remcomOutBuffer, "OK");
- else
- strcpy(remcomOutBuffer, "E03");
- }
- else
- strcpy(remcomOutBuffer, "E02");
- break;
-
- case 'c': /* cAA..AA Continue at address AA..AA(optional) */
- /* try to read optional parameter, pc unchanged if no parm */
- if (hexToInt(&ptr, &addr))
- {
- registers[PC] = addr;
- registers[NPC] = addr + 4;
- }
-
-/* Need to flush the instruction cache here, as we may have deposited a
- breakpoint, and the icache probably has no way of knowing that a data ref to
- some location may have changed something that is in the instruction cache.
- */
-
- flush_i_cache ();
-
- if (!(registers[DSR] & 0x1) /* DSU enabled? */
- && !(registers[DCR] & 0x200)) /* Are we in break state? */
- { /* Yes, set the DSU regs */
- write_asi (1, 0xff00, registers[DIA1]);
- write_asi (1, 0xff04, registers[DIA2]);
- write_asi (1, 0xff08, registers[DDA1]);
- write_asi (1, 0xff0c, registers[DDA2]);
- write_asi (1, 0xff10, registers[DDV1]);
- write_asi (1, 0xff14, registers[DDV2]);
- write_asi (1, 0xff1c, registers[DSR]);
- write_asi (1, 0xff18, registers[DCR] | 0x200); /* Clear break */
- }
-
- return;
-
- /* kill the program */
- case 'k' : /* do nothing */
- break;
-#if 0
- case 't': /* Test feature */
- asm (" std %f30,[%sp]");
- break;
-#endif
- case 'r': /* Reset */
- asm ("call 0
- nop ");
- break;
- } /* switch */
-
- /* reply to the request */
- putpacket(remcomOutBuffer);
- }
-}
-
-/* This function will generate a breakpoint exception. It is used at the
- beginning of a program to sync up with a debugger and can be used
- otherwise as a quick means to stop program execution and "break" into
- the debugger. */
-
-void
-breakpoint (void)
-{
- if (!initialized)
- return;
-
- asm(" .globl _breakinst
-
- _breakinst: ta 1
- ");
-}
+// OBSOLETE /****************************************************************************
+// OBSOLETE
+// OBSOLETE THIS SOFTWARE IS NOT COPYRIGHTED
+// OBSOLETE
+// OBSOLETE HP offers the following for use in the public domain. HP makes no
+// OBSOLETE warranty with regard to the software or it's performance and the
+// OBSOLETE user accepts the software "AS IS" with all faults.
+// OBSOLETE
+// OBSOLETE HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
+// OBSOLETE TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OBSOLETE OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+// OBSOLETE
+// OBSOLETE ****************************************************************************/
+// OBSOLETE
+// OBSOLETE /****************************************************************************
+// OBSOLETE * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
+// OBSOLETE *
+// OBSOLETE * Module name: remcom.c $
+// OBSOLETE * Revision: 1.34 $
+// OBSOLETE * Date: 91/03/09 12:29:49 $
+// OBSOLETE * Contributor: Lake Stevens Instrument Division$
+// OBSOLETE *
+// OBSOLETE * Description: low level support for gdb debugger. $
+// OBSOLETE *
+// OBSOLETE * Considerations: only works on target hardware $
+// OBSOLETE *
+// OBSOLETE * Written by: Glenn Engel $
+// OBSOLETE * ModuleState: Experimental $
+// OBSOLETE *
+// OBSOLETE * NOTES: See Below $
+// OBSOLETE *
+// OBSOLETE * Modified for SPARC by Stu Grossman, Cygnus Support.
+// OBSOLETE * Based on sparc-stub.c, it's modified for SPARClite Debug Unit hardware
+// OBSOLETE * breakpoint support to create sparclite-stub.c, by Kung Hsu, Cygnus Support.
+// OBSOLETE *
+// OBSOLETE * This code has been extensively tested on the Fujitsu SPARClite demo board.
+// OBSOLETE *
+// OBSOLETE * To enable debugger support, two things need to happen. One, a
+// OBSOLETE * call to set_debug_traps() is necessary in order to allow any breakpoints
+// OBSOLETE * or error conditions to be properly intercepted and reported to gdb.
+// OBSOLETE * Two, a breakpoint needs to be generated to begin communication. This
+// OBSOLETE * is most easily accomplished by a call to breakpoint(). Breakpoint()
+// OBSOLETE * simulates a breakpoint by executing a trap #1.
+// OBSOLETE *
+// OBSOLETE *************
+// OBSOLETE *
+// OBSOLETE * The following gdb commands are supported:
+// OBSOLETE *
+// OBSOLETE * command function Return value
+// OBSOLETE *
+// OBSOLETE * g return the value of the CPU registers hex data or ENN
+// OBSOLETE * G set the value of the CPU registers OK or ENN
+// OBSOLETE * P set the value of a single CPU register OK or ENN
+// OBSOLETE *
+// OBSOLETE * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
+// OBSOLETE * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
+// OBSOLETE *
+// OBSOLETE * c Resume at current address SNN ( signal NN)
+// OBSOLETE * cAA..AA Continue at address AA..AA SNN
+// OBSOLETE *
+// OBSOLETE * s Step one instruction SNN
+// OBSOLETE * sAA..AA Step one instruction from AA..AA SNN
+// OBSOLETE *
+// OBSOLETE * k kill
+// OBSOLETE *
+// OBSOLETE * ? What was the last sigval ? SNN (signal NN)
+// OBSOLETE *
+// OBSOLETE * All commands and responses are sent with a packet which includes a
+// OBSOLETE * checksum. A packet consists of
+// OBSOLETE *
+
// OBSOLETE * $<packet info>#<checksum>.
+// OBSOLETE *
+// OBSOLETE * where
+
// OBSOLETE * <packet info> :: <characters representing the command or response>
+
// OBSOLETE * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
+// OBSOLETE *
+// OBSOLETE * When a packet is received, it is first acknowledged with either '+' or '-'.
+// OBSOLETE * '+' indicates a successful transfer. '-' indicates a failed transfer.
+// OBSOLETE *
+// OBSOLETE * Example:
+// OBSOLETE *
+// OBSOLETE * Host: Reply:
+// OBSOLETE * $m0,10#2a +$00010203040506070809101112131415#42
+// OBSOLETE *
+// OBSOLETE ****************************************************************************/
+// OBSOLETE
+// OBSOLETE #include <string.h>
+// OBSOLETE #include <signal.h>
+// OBSOLETE #include <sparclite.h>
+// OBSOLETE
+// OBSOLETE /************************************************************************
+// OBSOLETE *
+// OBSOLETE * external low-level support routines
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE extern void putDebugChar (int c); /* write a single character */
+// OBSOLETE extern int getDebugChar (void); /* read and return a single char */
+// OBSOLETE
+// OBSOLETE /************************************************************************/
+// OBSOLETE /* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
+// OBSOLETE /* at least NUMREGBYTES*2 are needed for register packets */
+// OBSOLETE #define BUFMAX 2048
+// OBSOLETE
+// OBSOLETE static int initialized = 0; /* !0 means we've been initialized */
+// OBSOLETE
+// OBSOLETE extern void breakinst ();
+// OBSOLETE static void set_mem_fault_trap (int enable);
+// OBSOLETE static void get_in_break_mode (void);
+// OBSOLETE
+// OBSOLETE static const char hexchars[]="0123456789abcdef";
+// OBSOLETE
+// OBSOLETE #define NUMREGS 80
+// OBSOLETE
+// OBSOLETE /* Number of bytes of registers. */
+// OBSOLETE #define NUMREGBYTES (NUMREGS * 4)
+// OBSOLETE enum regnames {G0, G1, G2, G3, G4, G5, G6, G7,
+// OBSOLETE O0, O1, O2, O3, O4, O5, SP, O7,
+// OBSOLETE L0, L1, L2, L3, L4, L5, L6, L7,
+// OBSOLETE I0, I1, I2, I3, I4, I5, FP, I7,
+// OBSOLETE
+// OBSOLETE F0, F1, F2, F3, F4, F5, F6, F7,
+// OBSOLETE F8, F9, F10, F11, F12, F13, F14, F15,
+// OBSOLETE F16, F17, F18, F19, F20, F21, F22, F23,
+// OBSOLETE F24, F25, F26, F27, F28, F29, F30, F31,
+// OBSOLETE Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR,
+// OBSOLETE DIA1, DIA2, DDA1, DDA2, DDV1, DDV2, DCR, DSR };
+// OBSOLETE
+// OBSOLETE /*************************** ASSEMBLY CODE MACROS *************************/
+// OBSOLETE /* */
+// OBSOLETE
+// OBSOLETE extern void trap_low();
+// OBSOLETE
+// OBSOLETE /* Create private copies of common functions used by the stub. This prevents
+// OBSOLETE nasty interactions between app code and the stub (for instance if user steps
+// OBSOLETE into strlen, etc..) */
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE strcpy (char *dst, const char *src)
+// OBSOLETE {
+// OBSOLETE char *retval = dst;
+// OBSOLETE
+// OBSOLETE while ((*dst++ = *src++) != '\000');
+// OBSOLETE
+// OBSOLETE return retval;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void *
+// OBSOLETE memcpy (void *vdst, const void *vsrc, int n)
+// OBSOLETE {
+// OBSOLETE char *dst = vdst;
+// OBSOLETE const char *src = vsrc;
+// OBSOLETE char *retval = dst;
+// OBSOLETE
+// OBSOLETE while (n-- > 0)
+// OBSOLETE *dst++ = *src++;
+// OBSOLETE
+// OBSOLETE return retval;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE asm("
+// OBSOLETE .reserve trapstack, 1000 * 4, \"bss\", 8
+// OBSOLETE
+// OBSOLETE .data
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE in_trap_handler:
+// OBSOLETE .word 0
+// OBSOLETE
+// OBSOLETE .text
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE ! This function is called when any SPARC trap (except window overflow or
+// OBSOLETE ! underflow) occurs. It makes sure that the invalid register window is still
+// OBSOLETE ! available before jumping into C code. It will also restore the world if you
+// OBSOLETE ! return from handle_exception.
+// OBSOLETE !
+// OBSOLETE ! On entry, trap_low expects l1 and l2 to contain pc and npc respectivly.
+// OBSOLETE ! Register usage throughout the routine is as follows:
+// OBSOLETE !
+// OBSOLETE ! l0 - psr
+// OBSOLETE ! l1 - pc
+// OBSOLETE ! l2 - npc
+// OBSOLETE ! l3 - wim
+// OBSOLETE ! l4 - scratch and y reg
+// OBSOLETE ! l5 - scratch and tbr
+// OBSOLETE ! l6 - unused
+// OBSOLETE ! l7 - unused
+// OBSOLETE
+// OBSOLETE .globl _trap_low
+// OBSOLETE _trap_low:
+// OBSOLETE mov %psr, %l0
+// OBSOLETE mov %wim, %l3
+// OBSOLETE
+// OBSOLETE srl %l3, %l0, %l4 ! wim >> cwp
+// OBSOLETE cmp %l4, 1
+// OBSOLETE bne window_fine ! Branch if not in the invalid window
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! Handle window overflow
+// OBSOLETE
+// OBSOLETE mov %g1, %l4 ! Save g1, we use it to hold the wim
+// OBSOLETE srl %l3, 1, %g1 ! Rotate wim right
+// OBSOLETE tst %g1
+// OBSOLETE bg good_wim ! Branch if new wim is non-zero
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! At this point, we need to bring a 1 into the high order bit of the wim.
+// OBSOLETE ! Since we don't want to make any assumptions about the number of register
+// OBSOLETE ! windows, we figure it out dynamically so as to setup the wim correctly.
+// OBSOLETE
+// OBSOLETE not %g1 ! Fill g1 with ones
+// OBSOLETE mov %g1, %wim ! Fill the wim with ones
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE mov %wim, %g1 ! Read back the wim
+// OBSOLETE inc %g1 ! Now g1 has 1 just to left of wim
+// OBSOLETE srl %g1, 1, %g1 ! Now put 1 at top of wim
+// OBSOLETE mov %g0, %wim ! Clear wim so that subsequent save
+// OBSOLETE nop ! won't trap
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE good_wim:
+// OBSOLETE save %g0, %g0, %g0 ! Slip into next window
+// OBSOLETE mov %g1, %wim ! Install the new wim
+// OBSOLETE
+// OBSOLETE std %l0, [%sp + 0 * 4] ! save L & I registers
+// OBSOLETE std %l2, [%sp + 2 * 4]
+// OBSOLETE std %l4, [%sp + 4 * 4]
+// OBSOLETE std %l6, [%sp + 6 * 4]
+// OBSOLETE
+// OBSOLETE std %i0, [%sp + 8 * 4]
+// OBSOLETE std %i2, [%sp + 10 * 4]
+// OBSOLETE std %i4, [%sp + 12 * 4]
+// OBSOLETE std %i6, [%sp + 14 * 4]
+// OBSOLETE
+// OBSOLETE restore ! Go back to trap window.
+// OBSOLETE mov %l4, %g1 ! Restore %g1
+// OBSOLETE
+// OBSOLETE window_fine:
+// OBSOLETE sethi %hi(in_trap_handler), %l4
+// OBSOLETE ld [%lo(in_trap_handler) + %l4], %l5
+// OBSOLETE tst %l5
+// OBSOLETE bg recursive_trap
+// OBSOLETE inc %l5
+// OBSOLETE
+// OBSOLETE set trapstack+1000*4, %sp ! Switch to trap stack
+// OBSOLETE
+// OBSOLETE recursive_trap:
+// OBSOLETE st %l5, [%lo(in_trap_handler) + %l4]
+// OBSOLETE sub %sp,(16+1+6+1+80)*4,%sp ! Make room for input & locals
+// OBSOLETE ! + hidden arg + arg spill
+// OBSOLETE ! + doubleword alignment
+// OBSOLETE ! + registers[72] local var
+// OBSOLETE
+// OBSOLETE std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
+// OBSOLETE std %g2, [%sp + (24 + 2) * 4]
+// OBSOLETE std %g4, [%sp + (24 + 4) * 4]
+// OBSOLETE std %g6, [%sp + (24 + 6) * 4]
+// OBSOLETE
+// OBSOLETE std %i0, [%sp + (24 + 8) * 4] ! registers[Ox]
+// OBSOLETE std %i2, [%sp + (24 + 10) * 4]
+// OBSOLETE std %i4, [%sp + (24 + 12) * 4]
+// OBSOLETE std %i6, [%sp + (24 + 14) * 4]
+// OBSOLETE
+// OBSOLETE mov %y, %l4
+// OBSOLETE mov %tbr, %l5
+// OBSOLETE st %l4, [%sp + (24 + 64) * 4] ! Y
+// OBSOLETE st %l0, [%sp + (24 + 65) * 4] ! PSR
+// OBSOLETE st %l3, [%sp + (24 + 66) * 4] ! WIM
+// OBSOLETE st %l5, [%sp + (24 + 67) * 4] ! TBR
+// OBSOLETE st %l1, [%sp + (24 + 68) * 4] ! PC
+// OBSOLETE st %l2, [%sp + (24 + 69) * 4] ! NPC
+// OBSOLETE
+// OBSOLETE or %l0, 0xf20, %l4
+// OBSOLETE mov %l4, %psr ! Turn on traps, disable interrupts
+// OBSOLETE
+// OBSOLETE set 0x1000, %l1
+// OBSOLETE btst %l1, %l0 ! FP enabled?
+// OBSOLETE be no_fpstore
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! Must save fsr first, to flush the FQ. This may cause a deferred fp trap, so
+// OBSOLETE ! traps must be enabled to allow the trap handler to clean things up.
+// OBSOLETE
+// OBSOLETE st %fsr, [%sp + (24 + 70) * 4]
+// OBSOLETE
+// OBSOLETE std %f0, [%sp + (24 + 32) * 4]
+// OBSOLETE std %f2, [%sp + (24 + 34) * 4]
+// OBSOLETE std %f4, [%sp + (24 + 36) * 4]
+// OBSOLETE std %f6, [%sp + (24 + 38) * 4]
+// OBSOLETE std %f8, [%sp + (24 + 40) * 4]
+// OBSOLETE std %f10, [%sp + (24 + 42) * 4]
+// OBSOLETE std %f12, [%sp + (24 + 44) * 4]
+// OBSOLETE std %f14, [%sp + (24 + 46) * 4]
+// OBSOLETE std %f16, [%sp + (24 + 48) * 4]
+// OBSOLETE std %f18, [%sp + (24 + 50) * 4]
+// OBSOLETE std %f20, [%sp + (24 + 52) * 4]
+// OBSOLETE std %f22, [%sp + (24 + 54) * 4]
+// OBSOLETE std %f24, [%sp + (24 + 56) * 4]
+// OBSOLETE std %f26, [%sp + (24 + 58) * 4]
+// OBSOLETE std %f28, [%sp + (24 + 60) * 4]
+// OBSOLETE std %f30, [%sp + (24 + 62) * 4]
+// OBSOLETE no_fpstore:
+// OBSOLETE
+// OBSOLETE call _handle_exception
+// OBSOLETE add %sp, 24 * 4, %o0 ! Pass address of registers
+// OBSOLETE
+// OBSOLETE ! Reload all of the registers that aren't on the stack
+// OBSOLETE
+// OBSOLETE ld [%sp + (24 + 1) * 4], %g1 ! registers[Gx]
+// OBSOLETE ldd [%sp + (24 + 2) * 4], %g2
+// OBSOLETE ldd [%sp + (24 + 4) * 4], %g4
+// OBSOLETE ldd [%sp + (24 + 6) * 4], %g6
+// OBSOLETE
+// OBSOLETE ldd [%sp + (24 + 8) * 4], %i0 ! registers[Ox]
+// OBSOLETE ldd [%sp + (24 + 10) * 4], %i2
+// OBSOLETE ldd [%sp + (24 + 12) * 4], %i4
+// OBSOLETE ldd [%sp + (24 + 14) * 4], %i6
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
+// OBSOLETE ldd [%sp + (24 + 68) * 4], %l2 ! PC & NPC
+// OBSOLETE
+// OBSOLETE set 0x1000, %l5
+// OBSOLETE btst %l5, %l1 ! FP enabled?
+// OBSOLETE be no_fpreload
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ldd [%sp + (24 + 32) * 4], %f0
+// OBSOLETE ldd [%sp + (24 + 34) * 4], %f2
+// OBSOLETE ldd [%sp + (24 + 36) * 4], %f4
+// OBSOLETE ldd [%sp + (24 + 38) * 4], %f6
+// OBSOLETE ldd [%sp + (24 + 40) * 4], %f8
+// OBSOLETE ldd [%sp + (24 + 42) * 4], %f10
+// OBSOLETE ldd [%sp + (24 + 44) * 4], %f12
+// OBSOLETE ldd [%sp + (24 + 46) * 4], %f14
+// OBSOLETE ldd [%sp + (24 + 48) * 4], %f16
+// OBSOLETE ldd [%sp + (24 + 50) * 4], %f18
+// OBSOLETE ldd [%sp + (24 + 52) * 4], %f20
+// OBSOLETE ldd [%sp + (24 + 54) * 4], %f22
+// OBSOLETE ldd [%sp + (24 + 56) * 4], %f24
+// OBSOLETE ldd [%sp + (24 + 58) * 4], %f26
+// OBSOLETE ldd [%sp + (24 + 60) * 4], %f28
+// OBSOLETE ldd [%sp + (24 + 62) * 4], %f30
+// OBSOLETE
+// OBSOLETE ld [%sp + (24 + 70) * 4], %fsr
+// OBSOLETE no_fpreload:
+// OBSOLETE
+// OBSOLETE restore ! Ensure that previous window is valid
+// OBSOLETE save %g0, %g0, %g0 ! by causing a window_underflow trap
+// OBSOLETE
+// OBSOLETE mov %l0, %y
+// OBSOLETE mov %l1, %psr ! Make sure that traps are disabled
+// OBSOLETE ! for rett
+// OBSOLETE sethi %hi(in_trap_handler), %l4
+// OBSOLETE ld [%lo(in_trap_handler) + %l4], %l5
+// OBSOLETE dec %l5
+// OBSOLETE st %l5, [%lo(in_trap_handler) + %l4]
+// OBSOLETE
+// OBSOLETE jmpl %l2, %g0 ! Restore old PC
+// OBSOLETE rett %l3 ! Restore old nPC
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE /* Convert ch from a hex digit to an int */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE hex (unsigned char ch)
+// OBSOLETE {
+// OBSOLETE if (ch >= 'a' && ch <= 'f')
+// OBSOLETE return ch-'a'+10;
+// OBSOLETE if (ch >= '0' && ch <= '9')
+// OBSOLETE return ch-'0';
+// OBSOLETE if (ch >= 'A' && ch <= 'F')
+// OBSOLETE return ch-'A'+10;
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static char remcomInBuffer[BUFMAX];
+// OBSOLETE static char remcomOutBuffer[BUFMAX];
+// OBSOLETE
+// OBSOLETE /* scan for the sequence $<data>#<checksum> */
+// OBSOLETE
+// OBSOLETE unsigned char *
+// OBSOLETE getpacket (void)
+// OBSOLETE {
+// OBSOLETE unsigned char *buffer = &remcomInBuffer[0];
+// OBSOLETE unsigned char checksum;
+// OBSOLETE unsigned char xmitcsum;
+// OBSOLETE int count;
+// OBSOLETE char ch;
+// OBSOLETE
+// OBSOLETE while (1)
+// OBSOLETE {
+// OBSOLETE /* wait around for the start character, ignore all other characters */
+// OBSOLETE while ((ch = getDebugChar ()) != '$')
+// OBSOLETE ;
+// OBSOLETE
+// OBSOLETE retry:
+// OBSOLETE checksum = 0;
+// OBSOLETE xmitcsum = -1;
+// OBSOLETE count = 0;
+// OBSOLETE
+// OBSOLETE /* now, read until a # or end of buffer is found */
+// OBSOLETE while (count < BUFMAX)
+// OBSOLETE {
+// OBSOLETE ch = getDebugChar ();
+// OBSOLETE if (ch == '$')
+// OBSOLETE goto retry;
+// OBSOLETE if (ch == '#')
+// OBSOLETE break;
+// OBSOLETE checksum = checksum + ch;
+// OBSOLETE buffer[count] = ch;
+// OBSOLETE count = count + 1;
+// OBSOLETE }
+// OBSOLETE buffer[count] = 0;
+// OBSOLETE
+// OBSOLETE if (ch == '#')
+// OBSOLETE {
+// OBSOLETE ch = getDebugChar ();
+// OBSOLETE xmitcsum = hex (ch) << 4;
+// OBSOLETE ch = getDebugChar ();
+// OBSOLETE xmitcsum += hex (ch);
+// OBSOLETE
+// OBSOLETE if (checksum != xmitcsum)
+// OBSOLETE {
+// OBSOLETE putDebugChar ('-'); /* failed checksum */
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE putDebugChar ('+'); /* successful transfer */
+// OBSOLETE
+// OBSOLETE /* if a sequence char is present, reply the sequence ID */
+// OBSOLETE if (buffer[2] == ':')
+// OBSOLETE {
+// OBSOLETE putDebugChar (buffer[0]);
+// OBSOLETE putDebugChar (buffer[1]);
+// OBSOLETE
+// OBSOLETE return &buffer[3];
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return &buffer[0];
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* send the packet in buffer. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE putpacket (unsigned char *buffer)
+// OBSOLETE {
+// OBSOLETE unsigned char checksum;
+// OBSOLETE int count;
+// OBSOLETE unsigned char ch;
+// OBSOLETE
+
// OBSOLETE /* $<packet info>#<checksum>. */
+// OBSOLETE do
+// OBSOLETE {
+// OBSOLETE putDebugChar('$');
+// OBSOLETE checksum = 0;
+// OBSOLETE count = 0;
+// OBSOLETE
+// OBSOLETE while (ch = buffer[count])
+// OBSOLETE {
+// OBSOLETE putDebugChar (ch);
+// OBSOLETE checksum += ch;
+// OBSOLETE count += 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE putDebugChar('#');
+// OBSOLETE putDebugChar(hexchars[checksum >> 4]);
+// OBSOLETE putDebugChar(hexchars[checksum & 0xf]);
+// OBSOLETE
+// OBSOLETE }
+// OBSOLETE while (getDebugChar() != '+');
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Indicate to caller of mem2hex or hex2mem that there has been an
+// OBSOLETE error. */
+// OBSOLETE static volatile int mem_err = 0;
+// OBSOLETE
+// OBSOLETE /* Convert the memory pointed to by mem into hex, placing result in buf.
+// OBSOLETE * Return a pointer to the last char put in buf (null), in case of mem fault,
+// OBSOLETE * return 0.
+// OBSOLETE * If MAY_FAULT is non-zero, then we will handle memory faults by returning
+// OBSOLETE * a 0, else treat a fault like any other fault in the stub.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static unsigned char *
+// OBSOLETE mem2hex (unsigned char *mem, unsigned char *buf, int count, int may_fault)
+// OBSOLETE {
+// OBSOLETE unsigned char ch;
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(may_fault);
+// OBSOLETE
+// OBSOLETE while (count-- > 0)
+// OBSOLETE {
+// OBSOLETE ch = *mem++;
+// OBSOLETE if (mem_err)
+// OBSOLETE return 0;
+// OBSOLETE *buf++ = hexchars[ch >> 4];
+// OBSOLETE *buf++ = hexchars[ch & 0xf];
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE *buf = 0;
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(0);
+// OBSOLETE
+// OBSOLETE return buf;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* convert the hex array pointed to by buf into binary to be placed in mem
+// OBSOLETE * return a pointer to the character AFTER the last byte written */
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE hex2mem (unsigned char *buf, unsigned char *mem, int count, int may_fault)
+// OBSOLETE {
+// OBSOLETE int i;
+// OBSOLETE unsigned char ch;
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(may_fault);
+// OBSOLETE
+// OBSOLETE for (i=0; i<count; i++)
+// OBSOLETE {
+// OBSOLETE ch = hex(*buf++) << 4;
+// OBSOLETE ch |= hex(*buf++);
+// OBSOLETE *mem++ = ch;
+// OBSOLETE if (mem_err)
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(0);
+// OBSOLETE
+// OBSOLETE return mem;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* This table contains the mapping between SPARC hardware trap types, and
+// OBSOLETE signals, which are primarily what GDB understands. It also indicates
+// OBSOLETE which hardware traps we need to commandeer when initializing the stub. */
+// OBSOLETE
+// OBSOLETE static struct hard_trap_info
+// OBSOLETE {
+// OBSOLETE unsigned char tt; /* Trap type code for SPARClite */
+// OBSOLETE unsigned char signo; /* Signal that we map this trap into */
+// OBSOLETE } hard_trap_info[] = {
+// OBSOLETE {0x01, SIGSEGV}, /* instruction access error */
+// OBSOLETE {0x02, SIGILL}, /* privileged instruction */
+// OBSOLETE {0x03, SIGILL}, /* illegal instruction */
+// OBSOLETE {0x04, SIGEMT}, /* fp disabled */
+// OBSOLETE {0x07, SIGBUS}, /* mem address not aligned */
+// OBSOLETE {0x09, SIGSEGV}, /* data access exception */
+// OBSOLETE {0x0a, SIGEMT}, /* tag overflow */
+// OBSOLETE {0x20, SIGBUS}, /* r register access error */
+// OBSOLETE {0x21, SIGBUS}, /* instruction access error */
+// OBSOLETE {0x24, SIGEMT}, /* cp disabled */
+// OBSOLETE {0x29, SIGBUS}, /* data access error */
+// OBSOLETE {0x2a, SIGFPE}, /* divide by zero */
+// OBSOLETE {0x2b, SIGBUS}, /* data store error */
+// OBSOLETE {0x80+1, SIGTRAP}, /* ta 1 - normal breakpoint instruction */
+// OBSOLETE {0xff, SIGTRAP}, /* hardware breakpoint */
+// OBSOLETE {0, 0} /* Must be last */
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE /* Set up exception handlers for tracing and breakpoints */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE set_debug_traps (void)
+// OBSOLETE {
+// OBSOLETE struct hard_trap_info *ht;
+// OBSOLETE
+// OBSOLETE /* Only setup fp traps if the FP is disabled. */
+// OBSOLETE
+// OBSOLETE for (ht = hard_trap_info;
+// OBSOLETE ht->tt != 0 && ht->signo != 0;
+// OBSOLETE ht++)
+// OBSOLETE if (ht->tt != 4 || ! (read_psr () & 0x1000))
+// OBSOLETE exceptionHandler(ht->tt, trap_low);
+// OBSOLETE
+// OBSOLETE initialized = 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE asm ("
+// OBSOLETE ! Trap handler for memory errors. This just sets mem_err to be non-zero. It
+// OBSOLETE ! assumes that %l1 is non-zero. This should be safe, as it is doubtful that
+// OBSOLETE ! 0 would ever contain code that could mem fault. This routine will skip
+// OBSOLETE ! past the faulting instruction after setting mem_err.
+// OBSOLETE
+// OBSOLETE .text
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE _fltr_set_mem_err:
+// OBSOLETE sethi %hi(_mem_err), %l0
+// OBSOLETE st %l1, [%l0 + %lo(_mem_err)]
+// OBSOLETE jmpl %l2, %g0
+// OBSOLETE rett %l2+4
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE set_mem_fault_trap (int enable)
+// OBSOLETE {
+// OBSOLETE extern void fltr_set_mem_err();
+// OBSOLETE mem_err = 0;
+// OBSOLETE
+// OBSOLETE if (enable)
+// OBSOLETE exceptionHandler(9, fltr_set_mem_err);
+// OBSOLETE else
+// OBSOLETE exceptionHandler(9, trap_low);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE asm ("
+// OBSOLETE .text
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE _dummy_hw_breakpoint:
+// OBSOLETE jmpl %l2, %g0
+// OBSOLETE rett %l2+4
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE get_in_break_mode (void)
+// OBSOLETE {
+// OBSOLETE extern void dummy_hw_breakpoint();
+// OBSOLETE
+// OBSOLETE exceptionHandler (255, dummy_hw_breakpoint);
+// OBSOLETE
+// OBSOLETE asm ("ta 255");
+// OBSOLETE
+// OBSOLETE exceptionHandler (255, trap_low);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Convert the SPARC hardware trap type code to a unix signal number. */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE computeSignal (int tt)
+// OBSOLETE {
+// OBSOLETE struct hard_trap_info *ht;
+// OBSOLETE
+// OBSOLETE for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
+// OBSOLETE if (ht->tt == tt)
+// OBSOLETE return ht->signo;
+// OBSOLETE
+// OBSOLETE return SIGHUP; /* default for things we don't know about */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * While we find nice hex chars, build an int.
+// OBSOLETE * Return number of chars processed.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE hexToInt(char **ptr, int *intValue)
+// OBSOLETE {
+// OBSOLETE int numChars = 0;
+// OBSOLETE int hexValue;
+// OBSOLETE
+// OBSOLETE *intValue = 0;
+// OBSOLETE
+// OBSOLETE while (**ptr)
+// OBSOLETE {
+// OBSOLETE hexValue = hex(**ptr);
+// OBSOLETE if (hexValue < 0)
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE *intValue = (*intValue << 4) | hexValue;
+// OBSOLETE numChars ++;
+// OBSOLETE
+// OBSOLETE (*ptr)++;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return (numChars);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * This function does all command procesing for interfacing to gdb. It
+// OBSOLETE * returns 1 if you should skip the instruction at the trap address, 0
+// OBSOLETE * otherwise.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE handle_exception (unsigned long *registers)
+// OBSOLETE {
+// OBSOLETE int tt; /* Trap type */
+// OBSOLETE int sigval;
+// OBSOLETE int addr;
+// OBSOLETE int length;
+// OBSOLETE char *ptr;
+// OBSOLETE unsigned long *sp;
+// OBSOLETE unsigned long dsr;
+// OBSOLETE
+// OBSOLETE /* First, we must force all of the windows to be spilled out */
+// OBSOLETE
+// OBSOLETE asm(" save %sp, -64, %sp
+// OBSOLETE save %sp, -64, %sp
+// OBSOLETE save %sp, -64, %sp
+// OBSOLETE save %sp, -64, %sp
+// OBSOLETE save %sp, -64, %sp
+// OBSOLETE save %sp, -64, %sp
+// OBSOLETE save %sp, -64, %sp
+// OBSOLETE save %sp, -64, %sp
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE get_in_break_mode (); /* Enable DSU register writes */
+// OBSOLETE
+// OBSOLETE registers[DIA1] = read_asi (1, 0xff00);
+// OBSOLETE registers[DIA2] = read_asi (1, 0xff04);
+// OBSOLETE registers[DDA1] = read_asi (1, 0xff08);
+// OBSOLETE registers[DDA2] = read_asi (1, 0xff0c);
+// OBSOLETE registers[DDV1] = read_asi (1, 0xff10);
+// OBSOLETE registers[DDV2] = read_asi (1, 0xff14);
+// OBSOLETE registers[DCR] = read_asi (1, 0xff18);
+// OBSOLETE registers[DSR] = read_asi (1, 0xff1c);
+// OBSOLETE
+// OBSOLETE if (registers[PC] == (unsigned long)breakinst)
+// OBSOLETE {
+// OBSOLETE registers[PC] = registers[NPC];
+// OBSOLETE registers[NPC] += 4;
+// OBSOLETE }
+// OBSOLETE sp = (unsigned long *)registers[SP];
+// OBSOLETE
+// OBSOLETE dsr = (unsigned long)registers[DSR];
+// OBSOLETE if (dsr & 0x3c)
+// OBSOLETE tt = 255;
+// OBSOLETE else
+// OBSOLETE tt = (registers[TBR] >> 4) & 0xff;
+// OBSOLETE
+// OBSOLETE /* reply to host that an exception has occurred */
+// OBSOLETE sigval = computeSignal(tt);
+// OBSOLETE ptr = remcomOutBuffer;
+// OBSOLETE
+// OBSOLETE *ptr++ = 'T';
+// OBSOLETE *ptr++ = hexchars[sigval >> 4];
+// OBSOLETE *ptr++ = hexchars[sigval & 0xf];
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[PC >> 4];
+// OBSOLETE *ptr++ = hexchars[PC & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)®isters[PC], ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[FP >> 4];
+// OBSOLETE *ptr++ = hexchars[FP & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex(sp + 8 + 6, ptr, 4, 0); /* FP */
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[SP >> 4];
+// OBSOLETE *ptr++ = hexchars[SP & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)&sp, ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[NPC >> 4];
+// OBSOLETE *ptr++ = hexchars[NPC & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)®isters[NPC], ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[O7 >> 4];
+// OBSOLETE *ptr++ = hexchars[O7 & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)®isters[O7], ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = 0;
+// OBSOLETE
+// OBSOLETE putpacket(remcomOutBuffer);
+// OBSOLETE
+// OBSOLETE while (1)
+// OBSOLETE {
+// OBSOLETE remcomOutBuffer[0] = 0;
+// OBSOLETE
+// OBSOLETE ptr = getpacket();
+// OBSOLETE switch (*ptr++)
+// OBSOLETE {
+// OBSOLETE case '?':
+// OBSOLETE remcomOutBuffer[0] = 'S';
+// OBSOLETE remcomOutBuffer[1] = hexchars[sigval >> 4];
+// OBSOLETE remcomOutBuffer[2] = hexchars[sigval & 0xf];
+// OBSOLETE remcomOutBuffer[3] = 0;
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'd':
+// OBSOLETE /* toggle debug flag */
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'g': /* return the value of the CPU registers */
+// OBSOLETE memcpy (®isters[L0], sp, 16 * 4); /* Copy L & I regs from stack */
+// OBSOLETE mem2hex ((char *)registers, remcomOutBuffer, NUMREGBYTES, 0);
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'G': /* Set the value of all registers */
+// OBSOLETE case 'P': /* Set the value of one register */
+// OBSOLETE {
+// OBSOLETE unsigned long *newsp, psr;
+// OBSOLETE
+// OBSOLETE psr = registers[PSR];
+// OBSOLETE
+// OBSOLETE if (ptr[-1] == 'P')
+// OBSOLETE {
+// OBSOLETE int regno;
+// OBSOLETE
+// OBSOLETE if (hexToInt (&ptr, ®no)
+// OBSOLETE && *ptr++ == '=')
+// OBSOLETE if (regno >= L0 && regno <= I7)
+// OBSOLETE hex2mem (ptr, sp + regno - L0, 4, 0);
+// OBSOLETE else
+// OBSOLETE hex2mem (ptr, (char *)®isters[regno], 4, 0);
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE strcpy (remcomOutBuffer, "E01");
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE hex2mem (ptr, (char *)registers, NUMREGBYTES, 0);
+// OBSOLETE memcpy (sp, ®isters[L0], 16 * 4); /* Copy L & I regs to stack */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* See if the stack pointer has moved. If so, then copy the saved
+// OBSOLETE locals and ins to the new location. This keeps the window
+// OBSOLETE overflow and underflow routines happy. */
+// OBSOLETE
+// OBSOLETE newsp = (unsigned long *)registers[SP];
+// OBSOLETE if (sp != newsp)
+// OBSOLETE sp = memcpy(newsp, sp, 16 * 4);
+// OBSOLETE
+// OBSOLETE /* Don't allow CWP to be modified. */
+// OBSOLETE
+// OBSOLETE if (psr != registers[PSR])
+// OBSOLETE registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f);
+// OBSOLETE
+// OBSOLETE strcpy(remcomOutBuffer,"OK");
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
+// OBSOLETE /* Try to read %x,%x. */
+// OBSOLETE
+// OBSOLETE if (hexToInt(&ptr, &addr)
+// OBSOLETE && *ptr++ == ','
+// OBSOLETE && hexToInt(&ptr, &length))
+// OBSOLETE {
+// OBSOLETE if (mem2hex((char *)addr, remcomOutBuffer, length, 1))
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE strcpy (remcomOutBuffer, "E03");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE strcpy(remcomOutBuffer,"E01");
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
+// OBSOLETE /* Try to read '%x,%x:'. */
+// OBSOLETE
+// OBSOLETE if (hexToInt(&ptr, &addr)
+// OBSOLETE && *ptr++ == ','
+// OBSOLETE && hexToInt(&ptr, &length)
+// OBSOLETE && *ptr++ == ':')
+// OBSOLETE {
+// OBSOLETE if (hex2mem(ptr, (char *)addr, length, 1))
+// OBSOLETE strcpy(remcomOutBuffer, "OK");
+// OBSOLETE else
+// OBSOLETE strcpy(remcomOutBuffer, "E03");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE strcpy(remcomOutBuffer, "E02");
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'c': /* cAA..AA Continue at address AA..AA(optional) */
+// OBSOLETE /* try to read optional parameter, pc unchanged if no parm */
+// OBSOLETE if (hexToInt(&ptr, &addr))
+// OBSOLETE {
+// OBSOLETE registers[PC] = addr;
+// OBSOLETE registers[NPC] = addr + 4;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Need to flush the instruction cache here, as we may have deposited a
+// OBSOLETE breakpoint, and the icache probably has no way of knowing that a data ref to
+// OBSOLETE some location may have changed something that is in the instruction cache.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE flush_i_cache ();
+// OBSOLETE
+// OBSOLETE if (!(registers[DSR] & 0x1) /* DSU enabled? */
+// OBSOLETE && !(registers[DCR] & 0x200)) /* Are we in break state? */
+// OBSOLETE { /* Yes, set the DSU regs */
+// OBSOLETE write_asi (1, 0xff00, registers[DIA1]);
+// OBSOLETE write_asi (1, 0xff04, registers[DIA2]);
+// OBSOLETE write_asi (1, 0xff08, registers[DDA1]);
+// OBSOLETE write_asi (1, 0xff0c, registers[DDA2]);
+// OBSOLETE write_asi (1, 0xff10, registers[DDV1]);
+// OBSOLETE write_asi (1, 0xff14, registers[DDV2]);
+// OBSOLETE write_asi (1, 0xff1c, registers[DSR]);
+// OBSOLETE write_asi (1, 0xff18, registers[DCR] | 0x200); /* Clear break */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE /* kill the program */
+// OBSOLETE case 'k' : /* do nothing */
+// OBSOLETE break;
+// OBSOLETE #if 0
+// OBSOLETE case 't': /* Test feature */
+// OBSOLETE asm (" std %f30,[%sp]");
+// OBSOLETE break;
+// OBSOLETE #endif
+// OBSOLETE case 'r': /* Reset */
+// OBSOLETE asm ("call 0
+// OBSOLETE nop ");
+// OBSOLETE break;
+// OBSOLETE } /* switch */
+// OBSOLETE
+// OBSOLETE /* reply to the request */
+// OBSOLETE putpacket(remcomOutBuffer);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* This function will generate a breakpoint exception. It is used at the
+// OBSOLETE beginning of a program to sync up with a debugger and can be used
+// OBSOLETE otherwise as a quick means to stop program execution and "break" into
+// OBSOLETE the debugger. */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE breakpoint (void)
+// OBSOLETE {
+// OBSOLETE if (!initialized)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE asm(" .globl _breakinst
+// OBSOLETE
+// OBSOLETE _breakinst: ta 1
+// OBSOLETE ");
+// OBSOLETE }
-/* Target dependent code for the Fujitsu SPARClite for GDB, the GNU debugger.
- Copyright 1994, 1995, 1996, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#include "defs.h"
-#include "gdbcore.h"
-#include "breakpoint.h"
-#include "target.h"
-#include "serial.h"
-#include "regcache.h"
-#include <sys/types.h>
-
-#if (!defined(__GO32__) && !defined(_WIN32)) || defined(__CYGWIN__)
-#define HAVE_SOCKETS
-#include <sys/time.h>
-#include <sys/socket.h>
-#include <netinet/in.h>
-#include <netdb.h>
-#endif
-
-static struct target_ops sparclite_ops;
-
-static char *remote_target_name = NULL;
-static struct serial *remote_desc = NULL;
-static int serial_flag;
-#ifdef HAVE_SOCKETS
-static int udp_fd = -1;
-#endif
-
-static struct serial *open_tty (char *name);
-static int send_resp (struct serial *desc, char c);
-static void close_tty (void * ignore);
-#ifdef HAVE_SOCKETS
-static int recv_udp_buf (int fd, unsigned char *buf, int len, int timeout);
-static int send_udp_buf (int fd, unsigned char *buf, int len);
-#endif
-static void sparclite_open (char *name, int from_tty);
-static void sparclite_close (int quitting);
-static void download (char *target_name, char *args, int from_tty,
- void (*write_routine) (bfd * from_bfd,
- asection * from_sec,
- file_ptr from_addr,
- bfd_vma to_addr, int len),
- void (*start_routine) (bfd_vma entry));
-static void sparclite_serial_start (bfd_vma entry);
-static void sparclite_serial_write (bfd * from_bfd, asection * from_sec,
- file_ptr from_addr,
- bfd_vma to_addr, int len);
-#ifdef HAVE_SOCKETS
-static unsigned short calc_checksum (unsigned char *buffer, int count);
-static void sparclite_udp_start (bfd_vma entry);
-static void sparclite_udp_write (bfd * from_bfd, asection * from_sec,
- file_ptr from_addr, bfd_vma to_addr,
- int len);
-#endif
-static void sparclite_download (char *filename, int from_tty);
-
-#define DDA2_SUP_ASI 0xb000000
-#define DDA1_SUP_ASI 0xb0000
-
-#define DDA2_ASI_MASK 0xff000000
-#define DDA1_ASI_MASK 0xff0000
-#define DIA2_SUP_MODE 0x8000
-#define DIA1_SUP_MODE 0x4000
-#define DDA2_ENABLE 0x100
-#define DDA1_ENABLE 0x80
-#define DIA2_ENABLE 0x40
-#define DIA1_ENABLE 0x20
-#define DSINGLE_STEP 0x10 /* not used */
-#define DDV_TYPE_MASK 0xc
-#define DDV_TYPE_LOAD 0x0
-#define DDV_TYPE_STORE 0x4
-#define DDV_TYPE_ACCESS 0x8
-#define DDV_TYPE_ALWAYS 0xc
-#define DDV_COND 0x2
-#define DDV_MASK 0x1
-
-int
-sparclite_insert_watchpoint (CORE_ADDR addr, int len, int type)
-{
- CORE_ADDR dcr;
-
- dcr = read_register (DCR_REGNUM);
-
- if (!(dcr & DDA1_ENABLE))
- {
- write_register (DDA1_REGNUM, addr);
- dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK);
- dcr |= (DDA1_SUP_ASI | DDA1_ENABLE);
- if (type == 1)
- {
- write_register (DDV1_REGNUM, 0);
- write_register (DDV2_REGNUM, 0xffffffff);
- dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK));
- }
- else if (type == 0)
- {
- write_register (DDV1_REGNUM, 0);
- write_register (DDV2_REGNUM, 0xffffffff);
- dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK));
- }
- else
- {
- write_register (DDV1_REGNUM, 0);
- write_register (DDV2_REGNUM, 0xffffffff);
- dcr |= (DDV_TYPE_ACCESS);
- }
- write_register (DCR_REGNUM, dcr);
- }
- else if (!(dcr & DDA2_ENABLE))
- {
- write_register (DDA2_REGNUM, addr);
- dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK);
- dcr |= (DDA2_SUP_ASI | DDA2_ENABLE);
- if (type == 1)
- {
- write_register (DDV1_REGNUM, 0);
- write_register (DDV2_REGNUM, 0xffffffff);
- dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK);
- }
- else if (type == 0)
- {
- write_register (DDV1_REGNUM, 0);
- write_register (DDV2_REGNUM, 0xffffffff);
- dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK);
- }
- else
- {
- write_register (DDV1_REGNUM, 0);
- write_register (DDV2_REGNUM, 0xffffffff);
- dcr |= (DDV_TYPE_ACCESS);
- }
- write_register (DCR_REGNUM, dcr);
- }
- else
- return -1;
-
- return 0;
-}
-
-int
-sparclite_remove_watchpoint (CORE_ADDR addr, int len, int type)
-{
- CORE_ADDR dcr, dda1, dda2;
-
- dcr = read_register (DCR_REGNUM);
- dda1 = read_register (DDA1_REGNUM);
- dda2 = read_register (DDA2_REGNUM);
-
- if ((dcr & DDA1_ENABLE) && addr == dda1)
- write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE));
- else if ((dcr & DDA2_ENABLE) && addr == dda2)
- write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE));
- else
- return -1;
-
- return 0;
-}
-
-int
-sparclite_insert_hw_breakpoint (CORE_ADDR addr, int len)
-{
- CORE_ADDR dcr;
-
- dcr = read_register (DCR_REGNUM);
-
- if (!(dcr & DIA1_ENABLE))
- {
- write_register (DIA1_REGNUM, addr);
- write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE));
- }
- else if (!(dcr & DIA2_ENABLE))
- {
- write_register (DIA2_REGNUM, addr);
- write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE));
- }
- else
- return -1;
-
- return 0;
-}
-
-int
-sparclite_remove_hw_breakpoint (CORE_ADDR addr, int shadow)
-{
- CORE_ADDR dcr, dia1, dia2;
-
- dcr = read_register (DCR_REGNUM);
- dia1 = read_register (DIA1_REGNUM);
- dia2 = read_register (DIA2_REGNUM);
-
- if ((dcr & DIA1_ENABLE) && addr == dia1)
- write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE));
- else if ((dcr & DIA2_ENABLE) && addr == dia2)
- write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE));
- else
- return -1;
-
- return 0;
-}
-
-int
-sparclite_check_watch_resources (int type, int cnt, int ot)
-{
- /* Watchpoints not supported on simulator. */
- if (strcmp (target_shortname, "sim") == 0)
- return 0;
-
- if (type == bp_hardware_breakpoint)
- {
- if (TARGET_HW_BREAK_LIMIT == 0)
- return 0;
- else if (cnt <= TARGET_HW_BREAK_LIMIT)
- return 1;
- }
- else
- {
- if (TARGET_HW_WATCH_LIMIT == 0)
- return 0;
- else if (ot)
- return -1;
- else if (cnt <= TARGET_HW_WATCH_LIMIT)
- return 1;
- }
- return -1;
-}
-
-CORE_ADDR
-sparclite_stopped_data_address (void)
-{
- CORE_ADDR dsr, dda1, dda2;
-
- dsr = read_register (DSR_REGNUM);
- dda1 = read_register (DDA1_REGNUM);
- dda2 = read_register (DDA2_REGNUM);
-
- if (dsr & 0x10)
- return dda1;
- else if (dsr & 0x20)
- return dda2;
- else
- return 0;
-}
-\f
-static struct serial *
-open_tty (char *name)
-{
- struct serial *desc;
-
- desc = serial_open (name);
- if (!desc)
- perror_with_name (name);
-
- if (baud_rate != -1)
- {
- if (serial_setbaudrate (desc, baud_rate))
- {
- serial_close (desc);
- perror_with_name (name);
- }
- }
-
- serial_raw (desc);
-
- serial_flush_input (desc);
-
- return desc;
-}
-
-/* Read a single character from the remote end, masking it down to 7 bits. */
-
-static int
-readchar (struct serial *desc, int timeout)
-{
- int ch;
- char s[10];
-
- ch = serial_readchar (desc, timeout);
-
- switch (ch)
- {
- case SERIAL_EOF:
- error ("SPARClite remote connection closed");
- case SERIAL_ERROR:
- perror_with_name ("SPARClite communication error");
- case SERIAL_TIMEOUT:
- error ("SPARClite remote timeout");
- default:
- if (remote_debug > 0)
- {
- sprintf (s, "[%02x]", ch & 0xff);
- puts_debug ("read -->", s, "<--");
- }
- return ch;
- }
-}
-
-static void
-debug_serial_write (struct serial *desc, char *buf, int len)
-{
- char s[10];
-
- serial_write (desc, buf, len);
- if (remote_debug > 0)
- {
- while (len-- > 0)
- {
- sprintf (s, "[%02x]", *buf & 0xff);
- puts_debug ("Sent -->", s, "<--");
- buf++;
- }
- }
-}
-
-
-static int
-send_resp (struct serial *desc, char c)
-{
- debug_serial_write (desc, &c, 1);
- return readchar (desc, remote_timeout);
-}
-
-static void
-close_tty (void *ignore)
-{
- if (!remote_desc)
- return;
-
- serial_close (remote_desc);
-
- remote_desc = NULL;
-}
-
-#ifdef HAVE_SOCKETS
-static int
-recv_udp_buf (int fd, unsigned char *buf, int len, int timeout)
-{
- int cc;
- fd_set readfds;
-
- FD_ZERO (&readfds);
- FD_SET (fd, &readfds);
-
- if (timeout >= 0)
- {
- struct timeval timebuf;
-
- timebuf.tv_sec = timeout;
- timebuf.tv_usec = 0;
- cc = select (fd + 1, &readfds, 0, 0, &timebuf);
- }
- else
- cc = select (fd + 1, &readfds, 0, 0, 0);
-
- if (cc == 0)
- return 0;
-
- if (cc != 1)
- perror_with_name ("recv_udp_buf: Bad return value from select:");
-
- cc = recv (fd, buf, len, 0);
-
- if (cc < 0)
- perror_with_name ("Got an error from recv: ");
-}
-
-static int
-send_udp_buf (int fd, unsigned char *buf, int len)
-{
- int cc;
-
- cc = send (fd, buf, len, 0);
-
- if (cc == len)
- return;
-
- if (cc < 0)
- perror_with_name ("Got an error from send: ");
-
- error ("Short count in send: tried %d, sent %d\n", len, cc);
-}
-#endif /* HAVE_SOCKETS */
-
-static void
-sparclite_open (char *name, int from_tty)
-{
- struct cleanup *old_chain;
- int c;
- char *p;
-
- if (!name)
- error ("You need to specify what device or hostname is associated with the SparcLite board.");
-
- target_preopen (from_tty);
-
- unpush_target (&sparclite_ops);
-
- if (remote_target_name)
- xfree (remote_target_name);
-
- remote_target_name = xstrdup (name);
-
- /* We need a 'serial' or 'udp' keyword to disambiguate host:port, which can
- mean either a serial port on a terminal server, or the IP address of a
- SPARClite demo board. If there's no colon, then it pretty much has to be
- a local device (except for DOS... grrmble) */
-
- p = strchr (name, ' ');
-
- if (p)
- {
- *p++ = '\000';
- while ((*p != '\000') && isspace (*p))
- p++;
-
- if (strncmp (name, "serial", strlen (name)) == 0)
- serial_flag = 1;
- else if (strncmp (name, "udp", strlen (name)) == 0)
- serial_flag = 0;
- else
- error ("Must specify either `serial' or `udp'.");
- }
- else
- {
- p = name;
-
- if (!strchr (name, ':'))
- serial_flag = 1; /* No colon is unambiguous (local device) */
- else
- error ("Usage: target sparclite serial /dev/ttyb\n\
-or: target sparclite udp host");
- }
-
- if (serial_flag)
- {
- remote_desc = open_tty (p);
-
- old_chain = make_cleanup (close_tty, 0 /*ignore*/);
-
- c = send_resp (remote_desc, 0x00);
-
- if (c != 0xaa)
- error ("Unknown response (0x%x) from SparcLite. Try resetting the board.",
- c);
-
- c = send_resp (remote_desc, 0x55);
-
- if (c != 0x55)
- error ("Sparclite appears to be ill.");
- }
- else
- {
-#ifdef HAVE_SOCKETS
- struct hostent *he;
- struct sockaddr_in sockaddr;
- unsigned char buffer[100];
- int cc;
-
- /* Setup the socket. Must be raw UDP. */
-
- he = gethostbyname (p);
-
- if (!he)
- error ("No such host %s.", p);
-
- udp_fd = socket (PF_INET, SOCK_DGRAM, 0);
-
- old_chain = make_cleanup (close, udp_fd);
-
- sockaddr.sin_family = PF_INET;
- sockaddr.sin_port = htons (7000);
- memcpy (&sockaddr.sin_addr.s_addr, he->h_addr, sizeof (struct in_addr));
-
- if (connect (udp_fd, &sockaddr, sizeof (sockaddr)))
- perror_with_name ("Connect failed");
-
- buffer[0] = 0x5;
- buffer[1] = 0;
-
- send_udp_buf (udp_fd, buffer, 2); /* Request version */
- cc = recv_udp_buf (udp_fd, buffer, sizeof (buffer), 5); /* Get response */
- if (cc == 0)
- error ("SPARClite isn't responding.");
-
- if (cc < 3)
- error ("SPARClite appears to be ill.");
-#else
- error ("UDP downloading is not supported for DOS hosts.");
-#endif /* HAVE_SOCKETS */
- }
-
- printf_unfiltered ("[SPARClite appears to be alive]\n");
-
- push_target (&sparclite_ops);
-
- discard_cleanups (old_chain);
-
- return;
-}
-
-static void
-sparclite_close (int quitting)
-{
- if (serial_flag)
- close_tty (0);
-#ifdef HAVE_SOCKETS
- else if (udp_fd != -1)
- close (udp_fd);
-#endif
-}
-
-#define LOAD_ADDRESS 0x40000000
-
-static void
-download (char *target_name, char *args, int from_tty,
- void (*write_routine) (bfd *from_bfd, asection *from_sec,
- file_ptr from_addr, bfd_vma to_addr, int len),
- void (*start_routine) (bfd_vma entry))
-{
- struct cleanup *old_chain;
- asection *section;
- bfd *pbfd;
- bfd_vma entry;
- int i;
-#define WRITESIZE 1024
- char *filename;
- int quiet;
- int nostart;
-
- quiet = 0;
- nostart = 0;
- filename = NULL;
-
- while (*args != '\000')
- {
- char *arg;
-
- while (isspace (*args))
- args++;
-
- arg = args;
-
- while ((*args != '\000') && !isspace (*args))
- args++;
-
- if (*args != '\000')
- *args++ = '\000';
-
- if (*arg != '-')
- filename = arg;
- else if (strncmp (arg, "-quiet", strlen (arg)) == 0)
- quiet = 1;
- else if (strncmp (arg, "-nostart", strlen (arg)) == 0)
- nostart = 1;
- else
- error ("unknown option `%s'", arg);
- }
-
- if (!filename)
- filename = get_exec_file (1);
-
- pbfd = bfd_openr (filename, gnutarget);
- if (pbfd == NULL)
- {
- perror_with_name (filename);
- return;
- }
- old_chain = make_cleanup_bfd_close (pbfd);
-
- if (!bfd_check_format (pbfd, bfd_object))
- error ("\"%s\" is not an object file: %s", filename,
- bfd_errmsg (bfd_get_error ()));
-
- for (section = pbfd->sections; section; section = section->next)
- {
- if (bfd_get_section_flags (pbfd, section) & SEC_LOAD)
- {
- bfd_vma section_address;
- bfd_size_type section_size;
- file_ptr fptr;
- const char *section_name;
-
- section_name = bfd_get_section_name (pbfd, section);
-
- section_address = bfd_get_section_vma (pbfd, section);
-
- /* Adjust sections from a.out files, since they don't
- carry their addresses with. */
- if (bfd_get_flavour (pbfd) == bfd_target_aout_flavour)
- {
- if (strcmp (section_name, ".text") == 0)
- section_address = bfd_get_start_address (pbfd);
- else if (strcmp (section_name, ".data") == 0)
- {
- /* Read the first 8 bytes of the data section.
- There should be the string 'DaTa' followed by
- a word containing the actual section address. */
- struct data_marker
- {
- char signature[4]; /* 'DaTa' */
- unsigned char sdata[4]; /* &sdata */
- }
- marker;
- bfd_get_section_contents (pbfd, section, &marker, 0,
- sizeof (marker));
- if (strncmp (marker.signature, "DaTa", 4) == 0)
- {
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- section_address = bfd_getb32 (marker.sdata);
- else
- section_address = bfd_getl32 (marker.sdata);
- }
- }
- }
-
- section_size = bfd_get_section_size_before_reloc (section);
-
- if (!quiet)
- printf_filtered ("[Loading section %s at 0x%x (%d bytes)]\n",
- bfd_get_section_name (pbfd, section),
- section_address,
- section_size);
-
- fptr = 0;
- while (section_size > 0)
- {
- int count;
- static char inds[] = "|/-\\";
- static int k = 0;
-
- QUIT;
-
- count = min (section_size, WRITESIZE);
-
- write_routine (pbfd, section, fptr, section_address, count);
-
- if (!quiet)
- {
- printf_unfiltered ("\r%c", inds[k++ % 4]);
- gdb_flush (gdb_stdout);
- }
-
- section_address += count;
- fptr += count;
- section_size -= count;
- }
- }
- }
-
- if (!nostart)
- {
- entry = bfd_get_start_address (pbfd);
-
- if (!quiet)
- printf_unfiltered ("[Starting %s at 0x%x]\n", filename, entry);
-
- start_routine (entry);
- }
-
- do_cleanups (old_chain);
-}
-
-static void
-sparclite_serial_start (bfd_vma entry)
-{
- char buffer[5];
- int i;
-
- buffer[0] = 0x03;
- store_unsigned_integer (buffer + 1, 4, entry);
-
- debug_serial_write (remote_desc, buffer, 1 + 4);
- i = readchar (remote_desc, remote_timeout);
- if (i != 0x55)
- error ("Can't start SparcLite. Error code %d\n", i);
-}
-
-static void
-sparclite_serial_write (bfd *from_bfd, asection *from_sec, file_ptr from_addr,
- bfd_vma to_addr, int len)
-{
- char buffer[4 + 4 + WRITESIZE]; /* addr + len + data */
- unsigned char checksum;
- int i;
-
- store_unsigned_integer (buffer, 4, to_addr); /* Address */
- store_unsigned_integer (buffer + 4, 4, len); /* Length */
-
- bfd_get_section_contents (from_bfd, from_sec, buffer + 8, from_addr, len);
-
- checksum = 0;
- for (i = 0; i < len; i++)
- checksum += buffer[8 + i];
-
- i = send_resp (remote_desc, 0x01);
-
- if (i != 0x5a)
- error ("Bad response from load command (0x%x)", i);
-
- debug_serial_write (remote_desc, buffer, 4 + 4 + len);
- i = readchar (remote_desc, remote_timeout);
-
- if (i != checksum)
- error ("Bad checksum from load command (0x%x)", i);
-}
-
-#ifdef HAVE_SOCKETS
-
-static unsigned short
-calc_checksum (unsigned char *buffer, int count)
-{
- unsigned short checksum;
-
- checksum = 0;
- for (; count > 0; count -= 2, buffer += 2)
- checksum += (*buffer << 8) | *(buffer + 1);
-
- if (count != 0)
- checksum += *buffer << 8;
-
- return checksum;
-}
-
-static void
-sparclite_udp_start (bfd_vma entry)
-{
- unsigned char buffer[6];
- int i;
-
- buffer[0] = 0x3;
- buffer[1] = 0;
- buffer[2] = entry >> 24;
- buffer[3] = entry >> 16;
- buffer[4] = entry >> 8;
- buffer[5] = entry;
-
- send_udp_buf (udp_fd, buffer, 6); /* Send start addr */
- i = recv_udp_buf (udp_fd, buffer, sizeof (buffer), -1); /* Get response */
-
- if (i < 1 || buffer[0] != 0x55)
- error ("Failed to take start address.");
-}
-
-static void
-sparclite_udp_write (bfd *from_bfd, asection *from_sec, file_ptr from_addr,
- bfd_vma to_addr, int len)
-{
- unsigned char buffer[2000];
- unsigned short checksum;
- static int pkt_num = 0;
- static unsigned long old_addr = -1;
- int i;
-
- while (1)
- {
- if (to_addr != old_addr)
- {
- buffer[0] = 0x1; /* Load command */
- buffer[1] = 0x1; /* Loading address */
- buffer[2] = to_addr >> 24;
- buffer[3] = to_addr >> 16;
- buffer[4] = to_addr >> 8;
- buffer[5] = to_addr;
-
- checksum = 0;
- for (i = 0; i < 6; i++)
- checksum += buffer[i];
- checksum &= 0xff;
-
- send_udp_buf (udp_fd, buffer, 6);
- i = recv_udp_buf (udp_fd, buffer, sizeof buffer, -1);
-
- if (i < 1)
- error ("Got back short checksum for load addr.");
-
- if (checksum != buffer[0])
- error ("Got back bad checksum for load addr.");
-
- pkt_num = 0; /* Load addr resets packet seq # */
- old_addr = to_addr;
- }
-
- bfd_get_section_contents (from_bfd, from_sec, buffer + 6, from_addr,
- len);
-
- checksum = calc_checksum (buffer + 6, len);
-
- buffer[0] = 0x1; /* Load command */
- buffer[1] = 0x2; /* Loading data */
- buffer[2] = pkt_num >> 8;
- buffer[3] = pkt_num;
- buffer[4] = checksum >> 8;
- buffer[5] = checksum;
-
- send_udp_buf (udp_fd, buffer, len + 6);
- i = recv_udp_buf (udp_fd, buffer, sizeof buffer, 3);
-
- if (i == 0)
- {
- fprintf_unfiltered (gdb_stderr, "send_data: timeout sending %d bytes to address 0x%x retrying\n", len, to_addr);
- continue;
- }
-
- if (buffer[0] != 0xff)
- error ("Got back bad response for load data.");
-
- old_addr += len;
- pkt_num++;
-
- return;
- }
-}
-
-#endif /* HAVE_SOCKETS */
-
-static void
-sparclite_download (char *filename, int from_tty)
-{
- if (!serial_flag)
-#ifdef HAVE_SOCKETS
- download (remote_target_name, filename, from_tty, sparclite_udp_write,
- sparclite_udp_start);
-#else
- internal_error (__FILE__, __LINE__, "failed internal consistency check"); /* sparclite_open should prevent this! */
-#endif
- else
- download (remote_target_name, filename, from_tty, sparclite_serial_write,
- sparclite_serial_start);
-}
-\f
-/* Set up the sparclite target vector. */
-
-static void
-init_sparclite_ops (void)
-{
- sparclite_ops.to_shortname = "sparclite";
- sparclite_ops.to_longname = "SPARClite download target";
- sparclite_ops.to_doc = "Download to a remote SPARClite target board via serial of UDP.\n\
-Specify the device it is connected to (e.g. /dev/ttya).";
- sparclite_ops.to_open = sparclite_open;
- sparclite_ops.to_close = sparclite_close;
- sparclite_ops.to_load = sparclite_download;
- sparclite_ops.to_stratum = download_stratum;
- sparclite_ops.to_magic = OPS_MAGIC;
-}
-
-void
-_initialize_sparcl_tdep (void)
-{
- init_sparclite_ops ();
- add_target (&sparclite_ops);
-}
+// OBSOLETE /* Target dependent code for the Fujitsu SPARClite for GDB, the GNU debugger.
+// OBSOLETE Copyright 1994, 1995, 1996, 1998, 1999, 2000, 2001
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE #include "defs.h"
+// OBSOLETE #include "gdbcore.h"
+// OBSOLETE #include "breakpoint.h"
+// OBSOLETE #include "target.h"
+// OBSOLETE #include "serial.h"
+// OBSOLETE #include "regcache.h"
+// OBSOLETE #include <sys/types.h>
+// OBSOLETE
+// OBSOLETE #if (!defined(__GO32__) && !defined(_WIN32)) || defined(__CYGWIN__)
+// OBSOLETE #define HAVE_SOCKETS
+// OBSOLETE #include <sys/time.h>
+// OBSOLETE #include <sys/socket.h>
+// OBSOLETE #include <netinet/in.h>
+// OBSOLETE #include <netdb.h>
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE static struct target_ops sparclite_ops;
+// OBSOLETE
+// OBSOLETE static char *remote_target_name = NULL;
+// OBSOLETE static struct serial *remote_desc = NULL;
+// OBSOLETE static int serial_flag;
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE static int udp_fd = -1;
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE static struct serial *open_tty (char *name);
+// OBSOLETE static int send_resp (struct serial *desc, char c);
+// OBSOLETE static void close_tty (void * ignore);
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE static int recv_udp_buf (int fd, unsigned char *buf, int len, int timeout);
+// OBSOLETE static int send_udp_buf (int fd, unsigned char *buf, int len);
+// OBSOLETE #endif
+// OBSOLETE static void sparclite_open (char *name, int from_tty);
+// OBSOLETE static void sparclite_close (int quitting);
+// OBSOLETE static void download (char *target_name, char *args, int from_tty,
+// OBSOLETE void (*write_routine) (bfd * from_bfd,
+// OBSOLETE asection * from_sec,
+// OBSOLETE file_ptr from_addr,
+// OBSOLETE bfd_vma to_addr, int len),
+// OBSOLETE void (*start_routine) (bfd_vma entry));
+// OBSOLETE static void sparclite_serial_start (bfd_vma entry);
+// OBSOLETE static void sparclite_serial_write (bfd * from_bfd, asection * from_sec,
+// OBSOLETE file_ptr from_addr,
+// OBSOLETE bfd_vma to_addr, int len);
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE static unsigned short calc_checksum (unsigned char *buffer, int count);
+// OBSOLETE static void sparclite_udp_start (bfd_vma entry);
+// OBSOLETE static void sparclite_udp_write (bfd * from_bfd, asection * from_sec,
+// OBSOLETE file_ptr from_addr, bfd_vma to_addr,
+// OBSOLETE int len);
+// OBSOLETE #endif
+// OBSOLETE static void sparclite_download (char *filename, int from_tty);
+// OBSOLETE
+// OBSOLETE #define DDA2_SUP_ASI 0xb000000
+// OBSOLETE #define DDA1_SUP_ASI 0xb0000
+// OBSOLETE
+// OBSOLETE #define DDA2_ASI_MASK 0xff000000
+// OBSOLETE #define DDA1_ASI_MASK 0xff0000
+// OBSOLETE #define DIA2_SUP_MODE 0x8000
+// OBSOLETE #define DIA1_SUP_MODE 0x4000
+// OBSOLETE #define DDA2_ENABLE 0x100
+// OBSOLETE #define DDA1_ENABLE 0x80
+// OBSOLETE #define DIA2_ENABLE 0x40
+// OBSOLETE #define DIA1_ENABLE 0x20
+// OBSOLETE #define DSINGLE_STEP 0x10 /* not used */
+// OBSOLETE #define DDV_TYPE_MASK 0xc
+// OBSOLETE #define DDV_TYPE_LOAD 0x0
+// OBSOLETE #define DDV_TYPE_STORE 0x4
+// OBSOLETE #define DDV_TYPE_ACCESS 0x8
+// OBSOLETE #define DDV_TYPE_ALWAYS 0xc
+// OBSOLETE #define DDV_COND 0x2
+// OBSOLETE #define DDV_MASK 0x1
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE sparclite_insert_watchpoint (CORE_ADDR addr, int len, int type)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR dcr;
+// OBSOLETE
+// OBSOLETE dcr = read_register (DCR_REGNUM);
+// OBSOLETE
+// OBSOLETE if (!(dcr & DDA1_ENABLE))
+// OBSOLETE {
+// OBSOLETE write_register (DDA1_REGNUM, addr);
+// OBSOLETE dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK);
+// OBSOLETE dcr |= (DDA1_SUP_ASI | DDA1_ENABLE);
+// OBSOLETE if (type == 1)
+// OBSOLETE {
+// OBSOLETE write_register (DDV1_REGNUM, 0);
+// OBSOLETE write_register (DDV2_REGNUM, 0xffffffff);
+// OBSOLETE dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK));
+// OBSOLETE }
+// OBSOLETE else if (type == 0)
+// OBSOLETE {
+// OBSOLETE write_register (DDV1_REGNUM, 0);
+// OBSOLETE write_register (DDV2_REGNUM, 0xffffffff);
+// OBSOLETE dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK));
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE write_register (DDV1_REGNUM, 0);
+// OBSOLETE write_register (DDV2_REGNUM, 0xffffffff);
+// OBSOLETE dcr |= (DDV_TYPE_ACCESS);
+// OBSOLETE }
+// OBSOLETE write_register (DCR_REGNUM, dcr);
+// OBSOLETE }
+// OBSOLETE else if (!(dcr & DDA2_ENABLE))
+// OBSOLETE {
+// OBSOLETE write_register (DDA2_REGNUM, addr);
+// OBSOLETE dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK);
+// OBSOLETE dcr |= (DDA2_SUP_ASI | DDA2_ENABLE);
+// OBSOLETE if (type == 1)
+// OBSOLETE {
+// OBSOLETE write_register (DDV1_REGNUM, 0);
+// OBSOLETE write_register (DDV2_REGNUM, 0xffffffff);
+// OBSOLETE dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK);
+// OBSOLETE }
+// OBSOLETE else if (type == 0)
+// OBSOLETE {
+// OBSOLETE write_register (DDV1_REGNUM, 0);
+// OBSOLETE write_register (DDV2_REGNUM, 0xffffffff);
+// OBSOLETE dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE write_register (DDV1_REGNUM, 0);
+// OBSOLETE write_register (DDV2_REGNUM, 0xffffffff);
+// OBSOLETE dcr |= (DDV_TYPE_ACCESS);
+// OBSOLETE }
+// OBSOLETE write_register (DCR_REGNUM, dcr);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE sparclite_remove_watchpoint (CORE_ADDR addr, int len, int type)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR dcr, dda1, dda2;
+// OBSOLETE
+// OBSOLETE dcr = read_register (DCR_REGNUM);
+// OBSOLETE dda1 = read_register (DDA1_REGNUM);
+// OBSOLETE dda2 = read_register (DDA2_REGNUM);
+// OBSOLETE
+// OBSOLETE if ((dcr & DDA1_ENABLE) && addr == dda1)
+// OBSOLETE write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE));
+// OBSOLETE else if ((dcr & DDA2_ENABLE) && addr == dda2)
+// OBSOLETE write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE));
+// OBSOLETE else
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE sparclite_insert_hw_breakpoint (CORE_ADDR addr, int len)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR dcr;
+// OBSOLETE
+// OBSOLETE dcr = read_register (DCR_REGNUM);
+// OBSOLETE
+// OBSOLETE if (!(dcr & DIA1_ENABLE))
+// OBSOLETE {
+// OBSOLETE write_register (DIA1_REGNUM, addr);
+// OBSOLETE write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE));
+// OBSOLETE }
+// OBSOLETE else if (!(dcr & DIA2_ENABLE))
+// OBSOLETE {
+// OBSOLETE write_register (DIA2_REGNUM, addr);
+// OBSOLETE write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE));
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE sparclite_remove_hw_breakpoint (CORE_ADDR addr, int shadow)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR dcr, dia1, dia2;
+// OBSOLETE
+// OBSOLETE dcr = read_register (DCR_REGNUM);
+// OBSOLETE dia1 = read_register (DIA1_REGNUM);
+// OBSOLETE dia2 = read_register (DIA2_REGNUM);
+// OBSOLETE
+// OBSOLETE if ((dcr & DIA1_ENABLE) && addr == dia1)
+// OBSOLETE write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE));
+// OBSOLETE else if ((dcr & DIA2_ENABLE) && addr == dia2)
+// OBSOLETE write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE));
+// OBSOLETE else
+// OBSOLETE return -1;
+// OBSOLETE
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE sparclite_check_watch_resources (int type, int cnt, int ot)
+// OBSOLETE {
+// OBSOLETE /* Watchpoints not supported on simulator. */
+// OBSOLETE if (strcmp (target_shortname, "sim") == 0)
+// OBSOLETE return 0;
+// OBSOLETE
+// OBSOLETE if (type == bp_hardware_breakpoint)
+// OBSOLETE {
+// OBSOLETE if (TARGET_HW_BREAK_LIMIT == 0)
+// OBSOLETE return 0;
+// OBSOLETE else if (cnt <= TARGET_HW_BREAK_LIMIT)
+// OBSOLETE return 1;
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE if (TARGET_HW_WATCH_LIMIT == 0)
+// OBSOLETE return 0;
+// OBSOLETE else if (ot)
+// OBSOLETE return -1;
+// OBSOLETE else if (cnt <= TARGET_HW_WATCH_LIMIT)
+// OBSOLETE return 1;
+// OBSOLETE }
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE CORE_ADDR
+// OBSOLETE sparclite_stopped_data_address (void)
+// OBSOLETE {
+// OBSOLETE CORE_ADDR dsr, dda1, dda2;
+// OBSOLETE
+// OBSOLETE dsr = read_register (DSR_REGNUM);
+// OBSOLETE dda1 = read_register (DDA1_REGNUM);
+// OBSOLETE dda2 = read_register (DDA2_REGNUM);
+// OBSOLETE
+// OBSOLETE if (dsr & 0x10)
+// OBSOLETE return dda1;
+// OBSOLETE else if (dsr & 0x20)
+// OBSOLETE return dda2;
+// OBSOLETE else
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE static struct serial *
+// OBSOLETE open_tty (char *name)
+// OBSOLETE {
+// OBSOLETE struct serial *desc;
+// OBSOLETE
+// OBSOLETE desc = serial_open (name);
+// OBSOLETE if (!desc)
+// OBSOLETE perror_with_name (name);
+// OBSOLETE
+// OBSOLETE if (baud_rate != -1)
+// OBSOLETE {
+// OBSOLETE if (serial_setbaudrate (desc, baud_rate))
+// OBSOLETE {
+// OBSOLETE serial_close (desc);
+// OBSOLETE perror_with_name (name);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE serial_raw (desc);
+// OBSOLETE
+// OBSOLETE serial_flush_input (desc);
+// OBSOLETE
+// OBSOLETE return desc;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Read a single character from the remote end, masking it down to 7 bits. */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE readchar (struct serial *desc, int timeout)
+// OBSOLETE {
+// OBSOLETE int ch;
+// OBSOLETE char s[10];
+// OBSOLETE
+// OBSOLETE ch = serial_readchar (desc, timeout);
+// OBSOLETE
+// OBSOLETE switch (ch)
+// OBSOLETE {
+// OBSOLETE case SERIAL_EOF:
+// OBSOLETE error ("SPARClite remote connection closed");
+// OBSOLETE case SERIAL_ERROR:
+// OBSOLETE perror_with_name ("SPARClite communication error");
+// OBSOLETE case SERIAL_TIMEOUT:
+// OBSOLETE error ("SPARClite remote timeout");
+// OBSOLETE default:
+// OBSOLETE if (remote_debug > 0)
+// OBSOLETE {
+// OBSOLETE sprintf (s, "[%02x]", ch & 0xff);
+// OBSOLETE puts_debug ("read -->", s, "<--");
+// OBSOLETE }
+// OBSOLETE return ch;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE debug_serial_write (struct serial *desc, char *buf, int len)
+// OBSOLETE {
+// OBSOLETE char s[10];
+// OBSOLETE
+// OBSOLETE serial_write (desc, buf, len);
+// OBSOLETE if (remote_debug > 0)
+// OBSOLETE {
+// OBSOLETE while (len-- > 0)
+// OBSOLETE {
+// OBSOLETE sprintf (s, "[%02x]", *buf & 0xff);
+// OBSOLETE puts_debug ("Sent -->", s, "<--");
+// OBSOLETE buf++;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE send_resp (struct serial *desc, char c)
+// OBSOLETE {
+// OBSOLETE debug_serial_write (desc, &c, 1);
+// OBSOLETE return readchar (desc, remote_timeout);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE close_tty (void *ignore)
+// OBSOLETE {
+// OBSOLETE if (!remote_desc)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE serial_close (remote_desc);
+// OBSOLETE
+// OBSOLETE remote_desc = NULL;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE static int
+// OBSOLETE recv_udp_buf (int fd, unsigned char *buf, int len, int timeout)
+// OBSOLETE {
+// OBSOLETE int cc;
+// OBSOLETE fd_set readfds;
+// OBSOLETE
+// OBSOLETE FD_ZERO (&readfds);
+// OBSOLETE FD_SET (fd, &readfds);
+// OBSOLETE
+// OBSOLETE if (timeout >= 0)
+// OBSOLETE {
+// OBSOLETE struct timeval timebuf;
+// OBSOLETE
+// OBSOLETE timebuf.tv_sec = timeout;
+// OBSOLETE timebuf.tv_usec = 0;
+// OBSOLETE cc = select (fd + 1, &readfds, 0, 0, &timebuf);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE cc = select (fd + 1, &readfds, 0, 0, 0);
+// OBSOLETE
+// OBSOLETE if (cc == 0)
+// OBSOLETE return 0;
+// OBSOLETE
+// OBSOLETE if (cc != 1)
+// OBSOLETE perror_with_name ("recv_udp_buf: Bad return value from select:");
+// OBSOLETE
+// OBSOLETE cc = recv (fd, buf, len, 0);
+// OBSOLETE
+// OBSOLETE if (cc < 0)
+// OBSOLETE perror_with_name ("Got an error from recv: ");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE send_udp_buf (int fd, unsigned char *buf, int len)
+// OBSOLETE {
+// OBSOLETE int cc;
+// OBSOLETE
+// OBSOLETE cc = send (fd, buf, len, 0);
+// OBSOLETE
+// OBSOLETE if (cc == len)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE if (cc < 0)
+// OBSOLETE perror_with_name ("Got an error from send: ");
+// OBSOLETE
+// OBSOLETE error ("Short count in send: tried %d, sent %d\n", len, cc);
+// OBSOLETE }
+// OBSOLETE #endif /* HAVE_SOCKETS */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclite_open (char *name, int from_tty)
+// OBSOLETE {
+// OBSOLETE struct cleanup *old_chain;
+// OBSOLETE int c;
+// OBSOLETE char *p;
+// OBSOLETE
+// OBSOLETE if (!name)
+// OBSOLETE error ("You need to specify what device or hostname is associated with the SparcLite board.");
+// OBSOLETE
+// OBSOLETE target_preopen (from_tty);
+// OBSOLETE
+// OBSOLETE unpush_target (&sparclite_ops);
+// OBSOLETE
+// OBSOLETE if (remote_target_name)
+// OBSOLETE xfree (remote_target_name);
+// OBSOLETE
+// OBSOLETE remote_target_name = xstrdup (name);
+// OBSOLETE
+// OBSOLETE /* We need a 'serial' or 'udp' keyword to disambiguate host:port, which can
+// OBSOLETE mean either a serial port on a terminal server, or the IP address of a
+// OBSOLETE SPARClite demo board. If there's no colon, then it pretty much has to be
+// OBSOLETE a local device (except for DOS... grrmble) */
+// OBSOLETE
+// OBSOLETE p = strchr (name, ' ');
+// OBSOLETE
+// OBSOLETE if (p)
+// OBSOLETE {
+// OBSOLETE *p++ = '\000';
+// OBSOLETE while ((*p != '\000') && isspace (*p))
+// OBSOLETE p++;
+// OBSOLETE
+// OBSOLETE if (strncmp (name, "serial", strlen (name)) == 0)
+// OBSOLETE serial_flag = 1;
+// OBSOLETE else if (strncmp (name, "udp", strlen (name)) == 0)
+// OBSOLETE serial_flag = 0;
+// OBSOLETE else
+// OBSOLETE error ("Must specify either `serial' or `udp'.");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE p = name;
+// OBSOLETE
+// OBSOLETE if (!strchr (name, ':'))
+// OBSOLETE serial_flag = 1; /* No colon is unambiguous (local device) */
+// OBSOLETE else
+// OBSOLETE error ("Usage: target sparclite serial /dev/ttyb\n\
+// OBSOLETE or: target sparclite udp host");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (serial_flag)
+// OBSOLETE {
+// OBSOLETE remote_desc = open_tty (p);
+// OBSOLETE
+// OBSOLETE old_chain = make_cleanup (close_tty, 0 /*ignore*/);
+// OBSOLETE
+// OBSOLETE c = send_resp (remote_desc, 0x00);
+// OBSOLETE
+// OBSOLETE if (c != 0xaa)
+// OBSOLETE error ("Unknown response (0x%x) from SparcLite. Try resetting the board.",
+// OBSOLETE c);
+// OBSOLETE
+// OBSOLETE c = send_resp (remote_desc, 0x55);
+// OBSOLETE
+// OBSOLETE if (c != 0x55)
+// OBSOLETE error ("Sparclite appears to be ill.");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE struct hostent *he;
+// OBSOLETE struct sockaddr_in sockaddr;
+// OBSOLETE unsigned char buffer[100];
+// OBSOLETE int cc;
+// OBSOLETE
+// OBSOLETE /* Setup the socket. Must be raw UDP. */
+// OBSOLETE
+// OBSOLETE he = gethostbyname (p);
+// OBSOLETE
+// OBSOLETE if (!he)
+// OBSOLETE error ("No such host %s.", p);
+// OBSOLETE
+// OBSOLETE udp_fd = socket (PF_INET, SOCK_DGRAM, 0);
+// OBSOLETE
+// OBSOLETE old_chain = make_cleanup (close, udp_fd);
+// OBSOLETE
+// OBSOLETE sockaddr.sin_family = PF_INET;
+// OBSOLETE sockaddr.sin_port = htons (7000);
+// OBSOLETE memcpy (&sockaddr.sin_addr.s_addr, he->h_addr, sizeof (struct in_addr));
+// OBSOLETE
+// OBSOLETE if (connect (udp_fd, &sockaddr, sizeof (sockaddr)))
+// OBSOLETE perror_with_name ("Connect failed");
+// OBSOLETE
+// OBSOLETE buffer[0] = 0x5;
+// OBSOLETE buffer[1] = 0;
+// OBSOLETE
+// OBSOLETE send_udp_buf (udp_fd, buffer, 2); /* Request version */
+// OBSOLETE cc = recv_udp_buf (udp_fd, buffer, sizeof (buffer), 5); /* Get response */
+// OBSOLETE if (cc == 0)
+// OBSOLETE error ("SPARClite isn't responding.");
+// OBSOLETE
+// OBSOLETE if (cc < 3)
+// OBSOLETE error ("SPARClite appears to be ill.");
+// OBSOLETE #else
+// OBSOLETE error ("UDP downloading is not supported for DOS hosts.");
+// OBSOLETE #endif /* HAVE_SOCKETS */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE printf_unfiltered ("[SPARClite appears to be alive]\n");
+// OBSOLETE
+// OBSOLETE push_target (&sparclite_ops);
+// OBSOLETE
+// OBSOLETE discard_cleanups (old_chain);
+// OBSOLETE
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclite_close (int quitting)
+// OBSOLETE {
+// OBSOLETE if (serial_flag)
+// OBSOLETE close_tty (0);
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE else if (udp_fd != -1)
+// OBSOLETE close (udp_fd);
+// OBSOLETE #endif
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #define LOAD_ADDRESS 0x40000000
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE download (char *target_name, char *args, int from_tty,
+// OBSOLETE void (*write_routine) (bfd *from_bfd, asection *from_sec,
+// OBSOLETE file_ptr from_addr, bfd_vma to_addr, int len),
+// OBSOLETE void (*start_routine) (bfd_vma entry))
+// OBSOLETE {
+// OBSOLETE struct cleanup *old_chain;
+// OBSOLETE asection *section;
+// OBSOLETE bfd *pbfd;
+// OBSOLETE bfd_vma entry;
+// OBSOLETE int i;
+// OBSOLETE #define WRITESIZE 1024
+// OBSOLETE char *filename;
+// OBSOLETE int quiet;
+// OBSOLETE int nostart;
+// OBSOLETE
+// OBSOLETE quiet = 0;
+// OBSOLETE nostart = 0;
+// OBSOLETE filename = NULL;
+// OBSOLETE
+// OBSOLETE while (*args != '\000')
+// OBSOLETE {
+// OBSOLETE char *arg;
+// OBSOLETE
+// OBSOLETE while (isspace (*args))
+// OBSOLETE args++;
+// OBSOLETE
+// OBSOLETE arg = args;
+// OBSOLETE
+// OBSOLETE while ((*args != '\000') && !isspace (*args))
+// OBSOLETE args++;
+// OBSOLETE
+// OBSOLETE if (*args != '\000')
+// OBSOLETE *args++ = '\000';
+// OBSOLETE
+// OBSOLETE if (*arg != '-')
+// OBSOLETE filename = arg;
+// OBSOLETE else if (strncmp (arg, "-quiet", strlen (arg)) == 0)
+// OBSOLETE quiet = 1;
+// OBSOLETE else if (strncmp (arg, "-nostart", strlen (arg)) == 0)
+// OBSOLETE nostart = 1;
+// OBSOLETE else
+// OBSOLETE error ("unknown option `%s'", arg);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!filename)
+// OBSOLETE filename = get_exec_file (1);
+// OBSOLETE
+// OBSOLETE pbfd = bfd_openr (filename, gnutarget);
+// OBSOLETE if (pbfd == NULL)
+// OBSOLETE {
+// OBSOLETE perror_with_name (filename);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE old_chain = make_cleanup_bfd_close (pbfd);
+// OBSOLETE
+// OBSOLETE if (!bfd_check_format (pbfd, bfd_object))
+// OBSOLETE error ("\"%s\" is not an object file: %s", filename,
+// OBSOLETE bfd_errmsg (bfd_get_error ()));
+// OBSOLETE
+// OBSOLETE for (section = pbfd->sections; section; section = section->next)
+// OBSOLETE {
+// OBSOLETE if (bfd_get_section_flags (pbfd, section) & SEC_LOAD)
+// OBSOLETE {
+// OBSOLETE bfd_vma section_address;
+// OBSOLETE bfd_size_type section_size;
+// OBSOLETE file_ptr fptr;
+// OBSOLETE const char *section_name;
+// OBSOLETE
+// OBSOLETE section_name = bfd_get_section_name (pbfd, section);
+// OBSOLETE
+// OBSOLETE section_address = bfd_get_section_vma (pbfd, section);
+// OBSOLETE
+// OBSOLETE /* Adjust sections from a.out files, since they don't
+// OBSOLETE carry their addresses with. */
+// OBSOLETE if (bfd_get_flavour (pbfd) == bfd_target_aout_flavour)
+// OBSOLETE {
+// OBSOLETE if (strcmp (section_name, ".text") == 0)
+// OBSOLETE section_address = bfd_get_start_address (pbfd);
+// OBSOLETE else if (strcmp (section_name, ".data") == 0)
+// OBSOLETE {
+// OBSOLETE /* Read the first 8 bytes of the data section.
+// OBSOLETE There should be the string 'DaTa' followed by
+// OBSOLETE a word containing the actual section address. */
+// OBSOLETE struct data_marker
+// OBSOLETE {
+// OBSOLETE char signature[4]; /* 'DaTa' */
+// OBSOLETE unsigned char sdata[4]; /* &sdata */
+// OBSOLETE }
+// OBSOLETE marker;
+// OBSOLETE bfd_get_section_contents (pbfd, section, &marker, 0,
+// OBSOLETE sizeof (marker));
+// OBSOLETE if (strncmp (marker.signature, "DaTa", 4) == 0)
+// OBSOLETE {
+// OBSOLETE if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+// OBSOLETE section_address = bfd_getb32 (marker.sdata);
+// OBSOLETE else
+// OBSOLETE section_address = bfd_getl32 (marker.sdata);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE section_size = bfd_get_section_size_before_reloc (section);
+// OBSOLETE
+// OBSOLETE if (!quiet)
+// OBSOLETE printf_filtered ("[Loading section %s at 0x%x (%d bytes)]\n",
+// OBSOLETE bfd_get_section_name (pbfd, section),
+// OBSOLETE section_address,
+// OBSOLETE section_size);
+// OBSOLETE
+// OBSOLETE fptr = 0;
+// OBSOLETE while (section_size > 0)
+// OBSOLETE {
+// OBSOLETE int count;
+// OBSOLETE static char inds[] = "|/-\\";
+// OBSOLETE static int k = 0;
+// OBSOLETE
+// OBSOLETE QUIT;
+// OBSOLETE
+// OBSOLETE count = min (section_size, WRITESIZE);
+// OBSOLETE
+// OBSOLETE write_routine (pbfd, section, fptr, section_address, count);
+// OBSOLETE
+// OBSOLETE if (!quiet)
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("\r%c", inds[k++ % 4]);
+// OBSOLETE gdb_flush (gdb_stdout);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE section_address += count;
+// OBSOLETE fptr += count;
+// OBSOLETE section_size -= count;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (!nostart)
+// OBSOLETE {
+// OBSOLETE entry = bfd_get_start_address (pbfd);
+// OBSOLETE
+// OBSOLETE if (!quiet)
+// OBSOLETE printf_unfiltered ("[Starting %s at 0x%x]\n", filename, entry);
+// OBSOLETE
+// OBSOLETE start_routine (entry);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE do_cleanups (old_chain);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclite_serial_start (bfd_vma entry)
+// OBSOLETE {
+// OBSOLETE char buffer[5];
+// OBSOLETE int i;
+// OBSOLETE
+// OBSOLETE buffer[0] = 0x03;
+// OBSOLETE store_unsigned_integer (buffer + 1, 4, entry);
+// OBSOLETE
+// OBSOLETE debug_serial_write (remote_desc, buffer, 1 + 4);
+// OBSOLETE i = readchar (remote_desc, remote_timeout);
+// OBSOLETE if (i != 0x55)
+// OBSOLETE error ("Can't start SparcLite. Error code %d\n", i);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclite_serial_write (bfd *from_bfd, asection *from_sec, file_ptr from_addr,
+// OBSOLETE bfd_vma to_addr, int len)
+// OBSOLETE {
+// OBSOLETE char buffer[4 + 4 + WRITESIZE]; /* addr + len + data */
+// OBSOLETE unsigned char checksum;
+// OBSOLETE int i;
+// OBSOLETE
+// OBSOLETE store_unsigned_integer (buffer, 4, to_addr); /* Address */
+// OBSOLETE store_unsigned_integer (buffer + 4, 4, len); /* Length */
+// OBSOLETE
+// OBSOLETE bfd_get_section_contents (from_bfd, from_sec, buffer + 8, from_addr, len);
+// OBSOLETE
+// OBSOLETE checksum = 0;
+// OBSOLETE for (i = 0; i < len; i++)
+// OBSOLETE checksum += buffer[8 + i];
+// OBSOLETE
+// OBSOLETE i = send_resp (remote_desc, 0x01);
+// OBSOLETE
+// OBSOLETE if (i != 0x5a)
+// OBSOLETE error ("Bad response from load command (0x%x)", i);
+// OBSOLETE
+// OBSOLETE debug_serial_write (remote_desc, buffer, 4 + 4 + len);
+// OBSOLETE i = readchar (remote_desc, remote_timeout);
+// OBSOLETE
+// OBSOLETE if (i != checksum)
+// OBSOLETE error ("Bad checksum from load command (0x%x)", i);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE
+// OBSOLETE static unsigned short
+// OBSOLETE calc_checksum (unsigned char *buffer, int count)
+// OBSOLETE {
+// OBSOLETE unsigned short checksum;
+// OBSOLETE
+// OBSOLETE checksum = 0;
+// OBSOLETE for (; count > 0; count -= 2, buffer += 2)
+// OBSOLETE checksum += (*buffer << 8) | *(buffer + 1);
+// OBSOLETE
+// OBSOLETE if (count != 0)
+// OBSOLETE checksum += *buffer << 8;
+// OBSOLETE
+// OBSOLETE return checksum;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclite_udp_start (bfd_vma entry)
+// OBSOLETE {
+// OBSOLETE unsigned char buffer[6];
+// OBSOLETE int i;
+// OBSOLETE
+// OBSOLETE buffer[0] = 0x3;
+// OBSOLETE buffer[1] = 0;
+// OBSOLETE buffer[2] = entry >> 24;
+// OBSOLETE buffer[3] = entry >> 16;
+// OBSOLETE buffer[4] = entry >> 8;
+// OBSOLETE buffer[5] = entry;
+// OBSOLETE
+// OBSOLETE send_udp_buf (udp_fd, buffer, 6); /* Send start addr */
+// OBSOLETE i = recv_udp_buf (udp_fd, buffer, sizeof (buffer), -1); /* Get response */
+// OBSOLETE
+// OBSOLETE if (i < 1 || buffer[0] != 0x55)
+// OBSOLETE error ("Failed to take start address.");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclite_udp_write (bfd *from_bfd, asection *from_sec, file_ptr from_addr,
+// OBSOLETE bfd_vma to_addr, int len)
+// OBSOLETE {
+// OBSOLETE unsigned char buffer[2000];
+// OBSOLETE unsigned short checksum;
+// OBSOLETE static int pkt_num = 0;
+// OBSOLETE static unsigned long old_addr = -1;
+// OBSOLETE int i;
+// OBSOLETE
+// OBSOLETE while (1)
+// OBSOLETE {
+// OBSOLETE if (to_addr != old_addr)
+// OBSOLETE {
+// OBSOLETE buffer[0] = 0x1; /* Load command */
+// OBSOLETE buffer[1] = 0x1; /* Loading address */
+// OBSOLETE buffer[2] = to_addr >> 24;
+// OBSOLETE buffer[3] = to_addr >> 16;
+// OBSOLETE buffer[4] = to_addr >> 8;
+// OBSOLETE buffer[5] = to_addr;
+// OBSOLETE
+// OBSOLETE checksum = 0;
+// OBSOLETE for (i = 0; i < 6; i++)
+// OBSOLETE checksum += buffer[i];
+// OBSOLETE checksum &= 0xff;
+// OBSOLETE
+// OBSOLETE send_udp_buf (udp_fd, buffer, 6);
+// OBSOLETE i = recv_udp_buf (udp_fd, buffer, sizeof buffer, -1);
+// OBSOLETE
+// OBSOLETE if (i < 1)
+// OBSOLETE error ("Got back short checksum for load addr.");
+// OBSOLETE
+// OBSOLETE if (checksum != buffer[0])
+// OBSOLETE error ("Got back bad checksum for load addr.");
+// OBSOLETE
+// OBSOLETE pkt_num = 0; /* Load addr resets packet seq # */
+// OBSOLETE old_addr = to_addr;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE bfd_get_section_contents (from_bfd, from_sec, buffer + 6, from_addr,
+// OBSOLETE len);
+// OBSOLETE
+// OBSOLETE checksum = calc_checksum (buffer + 6, len);
+// OBSOLETE
+// OBSOLETE buffer[0] = 0x1; /* Load command */
+// OBSOLETE buffer[1] = 0x2; /* Loading data */
+// OBSOLETE buffer[2] = pkt_num >> 8;
+// OBSOLETE buffer[3] = pkt_num;
+// OBSOLETE buffer[4] = checksum >> 8;
+// OBSOLETE buffer[5] = checksum;
+// OBSOLETE
+// OBSOLETE send_udp_buf (udp_fd, buffer, len + 6);
+// OBSOLETE i = recv_udp_buf (udp_fd, buffer, sizeof buffer, 3);
+// OBSOLETE
+// OBSOLETE if (i == 0)
+// OBSOLETE {
+// OBSOLETE fprintf_unfiltered (gdb_stderr, "send_data: timeout sending %d bytes to address 0x%x retrying\n", len, to_addr);
+// OBSOLETE continue;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (buffer[0] != 0xff)
+// OBSOLETE error ("Got back bad response for load data.");
+// OBSOLETE
+// OBSOLETE old_addr += len;
+// OBSOLETE pkt_num++;
+// OBSOLETE
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #endif /* HAVE_SOCKETS */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclite_download (char *filename, int from_tty)
+// OBSOLETE {
+// OBSOLETE if (!serial_flag)
+// OBSOLETE #ifdef HAVE_SOCKETS
+// OBSOLETE download (remote_target_name, filename, from_tty, sparclite_udp_write,
+// OBSOLETE sparclite_udp_start);
+// OBSOLETE #else
+// OBSOLETE internal_error (__FILE__, __LINE__, "failed internal consistency check"); /* sparclite_open should prevent this! */
+// OBSOLETE #endif
+// OBSOLETE else
+// OBSOLETE download (remote_target_name, filename, from_tty, sparclite_serial_write,
+// OBSOLETE sparclite_serial_start);
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* Set up the sparclite target vector. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE init_sparclite_ops (void)
+// OBSOLETE {
+// OBSOLETE sparclite_ops.to_shortname = "sparclite";
+// OBSOLETE sparclite_ops.to_longname = "SPARClite download target";
+// OBSOLETE sparclite_ops.to_doc = "Download to a remote SPARClite target board via serial of UDP.\n\
+// OBSOLETE Specify the device it is connected to (e.g. /dev/ttya).";
+// OBSOLETE sparclite_ops.to_open = sparclite_open;
+// OBSOLETE sparclite_ops.to_close = sparclite_close;
+// OBSOLETE sparclite_ops.to_load = sparclite_download;
+// OBSOLETE sparclite_ops.to_stratum = download_stratum;
+// OBSOLETE sparclite_ops.to_magic = OPS_MAGIC;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE _initialize_sparcl_tdep (void)
+// OBSOLETE {
+// OBSOLETE init_sparclite_ops ();
+// OBSOLETE add_target (&sparclite_ops);
+// OBSOLETE }
-/* Remote target glue for the SPARC Sparclet ROM monitor.
-
- Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free
- Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-
-#include "defs.h"
-#include "gdbcore.h"
-#include "target.h"
-#include "monitor.h"
-#include "serial.h"
-#include "srec.h"
-#include "symtab.h"
-#include "symfile.h" /* for generic_load */
-#include "regcache.h"
-#include <time.h>
-
-extern void report_transfer_performance (unsigned long, time_t, time_t);
-
-static struct target_ops sparclet_ops;
-
-static void sparclet_open (char *args, int from_tty);
-
-/* This array of registers need to match the indexes used by GDB.
- This exists because the various ROM monitors use different strings
- than does GDB, and don't necessarily support all the registers
- either. So, typing "info reg sp" becomes a "r30". */
-
-/*PSR 0x00000080 impl ver icc AW LE EE EC EF PIL S PS ET CWP WIM
- 0x0 0x0 0x0 0 0 0 0 0 0x0 1 0 0 0x00 0x2
- 0000010
- INS LOCALS OUTS GLOBALS
- 0 0x00000000 0x00000000 0x00000000 0x00000000
- 1 0x00000000 0x00000000 0x00000000 0x00000000
- 2 0x00000000 0x00000000 0x00000000 0x00000000
- 3 0x00000000 0x00000000 0x00000000 0x00000000
- 4 0x00000000 0x00000000 0x00000000 0x00000000
- 5 0x00000000 0x00001000 0x00000000 0x00000000
- 6 0x00000000 0x00000000 0x123f0000 0x00000000
- 7 0x00000000 0x00000000 0x00000000 0x00000000
- pc: 0x12010000 0x00000000 unimp
- npc: 0x12010004 0x00001000 unimp 0x1000
- tbr: 0x00000000
- y: 0x00000000
- */
-/* these correspond to the offsets from tm-* files from config directories */
-
-/* is wim part of psr?? */
-/* monitor wants lower case */
-static char *sparclet_regnames[] = {
- "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
-
- "", "", "", "", "", "", "", "", /* no FPU regs */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* no CPSR, FPSR */
- "y", "psr", "wim", "tbr", "pc", "npc", "", "",
-
- "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
-
- /* ASR15 ASR19 (don't display them) */
- "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22",
-/*
- "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
- "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
- "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
- "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
- "apsr",
- */
-};
-
-
-
-/* Function: sparclet_supply_register
- Just returns with no action.
- This function is required, because parse_register_dump (monitor.c)
- expects to be able to call it. If we don't supply something, it will
- call a null pointer and core-dump. Since this function does not
- actually do anything, GDB will request the registers individually. */
-
-static void
-sparclet_supply_register (char *regname, int regnamelen, char *val, int vallen)
-{
- return;
-}
-
-static void
-sparclet_load (struct serial *desc, char *file, int hashmark)
-{
- bfd *abfd;
- asection *s;
- int i;
- CORE_ADDR load_offset;
- time_t start_time, end_time;
- unsigned long data_count = 0;
-
- /* enable user to specify address for downloading as 2nd arg to load */
-
- i = sscanf (file, "%*s 0x%lx", &load_offset);
- if (i >= 1)
- {
- char *p;
-
- for (p = file; *p != '\000' && !isspace (*p); p++);
-
- *p = '\000';
- }
- else
- load_offset = 0;
-
- abfd = bfd_openr (file, 0);
- if (!abfd)
- {
- printf_filtered ("Unable to open file %s\n", file);
- return;
- }
-
- if (bfd_check_format (abfd, bfd_object) == 0)
- {
- printf_filtered ("File is not an object file\n");
- return;
- }
-
- start_time = time (NULL);
-
- for (s = abfd->sections; s; s = s->next)
- if (s->flags & SEC_LOAD)
- {
- bfd_size_type section_size;
- bfd_vma vma;
-
- vma = bfd_get_section_vma (abfd, s) + load_offset;
- section_size = bfd_section_size (abfd, s);
-
- data_count += section_size;
-
- printf_filtered ("%s\t: 0x%4x .. 0x%4x ",
- bfd_get_section_name (abfd, s), vma,
- vma + section_size);
- gdb_flush (gdb_stdout);
-
- monitor_printf ("load c r %x %x\r", vma, section_size);
-
- monitor_expect ("load: loading ", NULL, 0);
- monitor_expect ("\r", NULL, 0);
-
- for (i = 0; i < section_size; i += 2048)
- {
- int numbytes;
- char buf[2048];
-
- numbytes = min (sizeof buf, section_size - i);
-
- bfd_get_section_contents (abfd, s, buf, i, numbytes);
-
- serial_write (desc, buf, numbytes);
-
- if (hashmark)
- {
- putchar_unfiltered ('#');
- gdb_flush (gdb_stdout);
- }
- } /* Per-packet (or S-record) loop */
-
- monitor_expect_prompt (NULL, 0);
-
- putchar_unfiltered ('\n');
- } /* Loadable sections */
-
- monitor_printf ("reg pc %x\r", bfd_get_start_address (abfd));
- monitor_expect_prompt (NULL, 0);
- monitor_printf ("reg npc %x\r", bfd_get_start_address (abfd) + 4);
- monitor_expect_prompt (NULL, 0);
-
- monitor_printf ("run\r");
-
- end_time = time (NULL);
-
- if (hashmark)
- putchar_unfiltered ('\n');
-
- report_transfer_performance (data_count, start_time, end_time);
-
- pop_target ();
- push_remote_target (monitor_get_dev_name (), 1);
-
- throw_exception (RETURN_QUIT);
-}
-
-/* Define the monitor command strings. Since these are passed directly
- through to a printf style function, we may include formatting
- strings. We also need a CR or LF on the end. */
-
-/* need to pause the monitor for timing reasons, so slow it down */
-
-static char *sparclet_inits[] =
-{"\n\r\r\n", NULL};
-
-static struct monitor_ops sparclet_cmds;
-
-static void
-init_sparclet_cmds (void)
-{
- sparclet_cmds.flags = MO_CLR_BREAK_USES_ADDR |
- MO_HEX_PREFIX |
- MO_NO_ECHO_ON_OPEN |
- MO_NO_ECHO_ON_SETMEM |
- MO_RUN_FIRST_TIME |
- MO_GETMEM_READ_SINGLE; /* flags */
- sparclet_cmds.init = sparclet_inits; /* Init strings */
- sparclet_cmds.cont = "cont\r"; /* continue command */
- sparclet_cmds.step = "step\r"; /* single step */
- sparclet_cmds.stop = "\r"; /* break interrupts the program */
- sparclet_cmds.set_break = "+bp %x\r"; /* set a breakpoint */
- sparclet_cmds.clr_break = "-bp %x\r"; /* can't use "br" because only 2 hw bps are supported */
- sparclet_cmds.clr_all_break = "-bp %x\r"; /* clear a breakpoint */
- "-bp\r"; /* clear all breakpoints */
- sparclet_cmds.fill = "fill %x -n %x -v %x -b\r"; /* fill (start length val) */
- /* can't use "fi" because it takes words, not bytes */
- /* ex [addr] [-n count] [-b|-s|-l] default: ex cur -n 1 -b */
- sparclet_cmds.setmem.cmdb = "ex %x -b\r%x\rq\r"; /* setmem.cmdb (addr, value) */
- sparclet_cmds.setmem.cmdw = "ex %x -s\r%x\rq\r"; /* setmem.cmdw (addr, value) */
- sparclet_cmds.setmem.cmdl = "ex %x -l\r%x\rq\r"; /* setmem.cmdl (addr, value) */
- sparclet_cmds.setmem.cmdll = NULL; /* setmem.cmdll (addr, value) */
- sparclet_cmds.setmem.resp_delim = NULL; /*": " *//* setmem.resp_delim */
- sparclet_cmds.setmem.term = NULL; /*"? " *//* setmem.term */
- sparclet_cmds.setmem.term_cmd = NULL; /*"q\r" *//* setmem.term_cmd */
- /* since the parsing of multiple bytes is difficult due to
- interspersed addresses, we'll only read 1 value at a time,
- even tho these can handle a count */
- /* we can use -n to set count to read, but may have to parse? */
- sparclet_cmds.getmem.cmdb = "ex %x -n 1 -b\r"; /* getmem.cmdb (addr, #bytes) */
- sparclet_cmds.getmem.cmdw = "ex %x -n 1 -s\r"; /* getmem.cmdw (addr, #swords) */
- sparclet_cmds.getmem.cmdl = "ex %x -n 1 -l\r"; /* getmem.cmdl (addr, #words) */
- sparclet_cmds.getmem.cmdll = NULL; /* getmem.cmdll (addr, #dwords) */
- sparclet_cmds.getmem.resp_delim = ": "; /* getmem.resp_delim */
- sparclet_cmds.getmem.term = NULL; /* getmem.term */
- sparclet_cmds.getmem.term_cmd = NULL; /* getmem.term_cmd */
- sparclet_cmds.setreg.cmd = "reg %s 0x%x\r"; /* setreg.cmd (name, value) */
- sparclet_cmds.setreg.resp_delim = NULL; /* setreg.resp_delim */
- sparclet_cmds.setreg.term = NULL; /* setreg.term */
- sparclet_cmds.setreg.term_cmd = NULL; /* setreg.term_cmd */
- sparclet_cmds.getreg.cmd = "reg %s\r"; /* getreg.cmd (name) */
- sparclet_cmds.getreg.resp_delim = " "; /* getreg.resp_delim */
- sparclet_cmds.getreg.term = NULL; /* getreg.term */
- sparclet_cmds.getreg.term_cmd = NULL; /* getreg.term_cmd */
- sparclet_cmds.dump_registers = "reg\r"; /* dump_registers */
- sparclet_cmds.register_pattern = "\\(\\w+\\)=\\([0-9a-fA-F]+\\)"; /* register_pattern */
- sparclet_cmds.supply_register = sparclet_supply_register; /* supply_register */
- sparclet_cmds.load_routine = sparclet_load; /* load_routine */
- sparclet_cmds.load = NULL; /* download command (srecs on console) */
- sparclet_cmds.loadresp = NULL; /* load response */
- sparclet_cmds.prompt = "monitor>"; /* monitor command prompt */
- /* yikes! gdb core dumps without this delimitor!! */
- sparclet_cmds.line_term = "\r"; /* end-of-command delimitor */
- sparclet_cmds.cmd_end = NULL; /* optional command terminator */
- sparclet_cmds.target = &sparclet_ops; /* target operations */
- sparclet_cmds.stopbits = SERIAL_1_STOPBITS; /* number of stop bits */
- sparclet_cmds.regnames = sparclet_regnames; /* registers names */
- sparclet_cmds.magic = MONITOR_OPS_MAGIC; /* magic */
-};
-
-static void
-sparclet_open (char *args, int from_tty)
-{
- monitor_open (args, &sparclet_cmds, from_tty);
-}
-
-void
-_initialize_sparclet (void)
-{
- int i;
- init_sparclet_cmds ();
-
- for (i = 0; i < NUM_REGS; i++)
- if (sparclet_regnames[i][0] == 'c' ||
- sparclet_regnames[i][0] == 'a')
- sparclet_regnames[i] = 0; /* mon can't report c* or a* regs */
-
- sparclet_regnames[0] = 0; /* mon won't report %G0 */
-
- init_monitor_ops (&sparclet_ops);
- sparclet_ops.to_shortname = "sparclet"; /* for the target command */
- sparclet_ops.to_longname = "SPARC Sparclet monitor";
- /* use SW breaks; target only supports 2 HW breakpoints */
- sparclet_ops.to_insert_breakpoint = memory_insert_breakpoint;
- sparclet_ops.to_remove_breakpoint = memory_remove_breakpoint;
-
- sparclet_ops.to_doc =
- "Use a board running the Sparclet debug monitor.\n\
-Specify the serial device it is connected to (e.g. /dev/ttya).";
-
- sparclet_ops.to_open = sparclet_open;
- add_target (&sparclet_ops);
-}
+// OBSOLETE /* Remote target glue for the SPARC Sparclet ROM monitor.
+// OBSOLETE
+// OBSOLETE Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free
+// OBSOLETE Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE #include "defs.h"
+// OBSOLETE #include "gdbcore.h"
+// OBSOLETE #include "target.h"
+// OBSOLETE #include "monitor.h"
+// OBSOLETE #include "serial.h"
+// OBSOLETE #include "srec.h"
+// OBSOLETE #include "symtab.h"
+// OBSOLETE #include "symfile.h" /* for generic_load */
+// OBSOLETE #include "regcache.h"
+// OBSOLETE #include <time.h>
+// OBSOLETE
+// OBSOLETE extern void report_transfer_performance (unsigned long, time_t, time_t);
+// OBSOLETE
+// OBSOLETE static struct target_ops sparclet_ops;
+// OBSOLETE
+// OBSOLETE static void sparclet_open (char *args, int from_tty);
+// OBSOLETE
+// OBSOLETE /* This array of registers need to match the indexes used by GDB.
+// OBSOLETE This exists because the various ROM monitors use different strings
+// OBSOLETE than does GDB, and don't necessarily support all the registers
+// OBSOLETE either. So, typing "info reg sp" becomes a "r30". */
+// OBSOLETE
+// OBSOLETE /*PSR 0x00000080 impl ver icc AW LE EE EC EF PIL S PS ET CWP WIM
+// OBSOLETE 0x0 0x0 0x0 0 0 0 0 0 0x0 1 0 0 0x00 0x2
+// OBSOLETE 0000010
+// OBSOLETE INS LOCALS OUTS GLOBALS
+// OBSOLETE 0 0x00000000 0x00000000 0x00000000 0x00000000
+// OBSOLETE 1 0x00000000 0x00000000 0x00000000 0x00000000
+// OBSOLETE 2 0x00000000 0x00000000 0x00000000 0x00000000
+// OBSOLETE 3 0x00000000 0x00000000 0x00000000 0x00000000
+// OBSOLETE 4 0x00000000 0x00000000 0x00000000 0x00000000
+// OBSOLETE 5 0x00000000 0x00001000 0x00000000 0x00000000
+// OBSOLETE 6 0x00000000 0x00000000 0x123f0000 0x00000000
+// OBSOLETE 7 0x00000000 0x00000000 0x00000000 0x00000000
+// OBSOLETE pc: 0x12010000 0x00000000 unimp
+// OBSOLETE npc: 0x12010004 0x00001000 unimp 0x1000
+// OBSOLETE tbr: 0x00000000
+// OBSOLETE y: 0x00000000
+// OBSOLETE */
+// OBSOLETE /* these correspond to the offsets from tm-* files from config directories */
+// OBSOLETE
+// OBSOLETE /* is wim part of psr?? */
+// OBSOLETE /* monitor wants lower case */
+// OBSOLETE static char *sparclet_regnames[] = {
+// OBSOLETE "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+// OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
+// OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+// OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
+// OBSOLETE
+// OBSOLETE "", "", "", "", "", "", "", "", /* no FPU regs */
+// OBSOLETE "", "", "", "", "", "", "", "",
+// OBSOLETE "", "", "", "", "", "", "", "",
+// OBSOLETE "", "", "", "", "", "", "", "",
+// OBSOLETE /* no CPSR, FPSR */
+// OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "", "",
+// OBSOLETE
+// OBSOLETE "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
+// OBSOLETE
+// OBSOLETE /* ASR15 ASR19 (don't display them) */
+// OBSOLETE "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22",
+// OBSOLETE /*
+// OBSOLETE "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
+// OBSOLETE "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
+// OBSOLETE "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
+// OBSOLETE "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
+// OBSOLETE "apsr",
+// OBSOLETE */
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE /* Function: sparclet_supply_register
+// OBSOLETE Just returns with no action.
+// OBSOLETE This function is required, because parse_register_dump (monitor.c)
+// OBSOLETE expects to be able to call it. If we don't supply something, it will
+// OBSOLETE call a null pointer and core-dump. Since this function does not
+// OBSOLETE actually do anything, GDB will request the registers individually. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclet_supply_register (char *regname, int regnamelen, char *val, int vallen)
+// OBSOLETE {
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclet_load (struct serial *desc, char *file, int hashmark)
+// OBSOLETE {
+// OBSOLETE bfd *abfd;
+// OBSOLETE asection *s;
+// OBSOLETE int i;
+// OBSOLETE CORE_ADDR load_offset;
+// OBSOLETE time_t start_time, end_time;
+// OBSOLETE unsigned long data_count = 0;
+// OBSOLETE
+// OBSOLETE /* enable user to specify address for downloading as 2nd arg to load */
+// OBSOLETE
+// OBSOLETE i = sscanf (file, "%*s 0x%lx", &load_offset);
+// OBSOLETE if (i >= 1)
+// OBSOLETE {
+// OBSOLETE char *p;
+// OBSOLETE
+// OBSOLETE for (p = file; *p != '\000' && !isspace (*p); p++);
+// OBSOLETE
+// OBSOLETE *p = '\000';
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE load_offset = 0;
+// OBSOLETE
+// OBSOLETE abfd = bfd_openr (file, 0);
+// OBSOLETE if (!abfd)
+// OBSOLETE {
+// OBSOLETE printf_filtered ("Unable to open file %s\n", file);
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (bfd_check_format (abfd, bfd_object) == 0)
+// OBSOLETE {
+// OBSOLETE printf_filtered ("File is not an object file\n");
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE start_time = time (NULL);
+// OBSOLETE
+// OBSOLETE for (s = abfd->sections; s; s = s->next)
+// OBSOLETE if (s->flags & SEC_LOAD)
+// OBSOLETE {
+// OBSOLETE bfd_size_type section_size;
+// OBSOLETE bfd_vma vma;
+// OBSOLETE
+// OBSOLETE vma = bfd_get_section_vma (abfd, s) + load_offset;
+// OBSOLETE section_size = bfd_section_size (abfd, s);
+// OBSOLETE
+// OBSOLETE data_count += section_size;
+// OBSOLETE
+// OBSOLETE printf_filtered ("%s\t: 0x%4x .. 0x%4x ",
+// OBSOLETE bfd_get_section_name (abfd, s), vma,
+// OBSOLETE vma + section_size);
+// OBSOLETE gdb_flush (gdb_stdout);
+// OBSOLETE
+// OBSOLETE monitor_printf ("load c r %x %x\r", vma, section_size);
+// OBSOLETE
+// OBSOLETE monitor_expect ("load: loading ", NULL, 0);
+// OBSOLETE monitor_expect ("\r", NULL, 0);
+// OBSOLETE
+// OBSOLETE for (i = 0; i < section_size; i += 2048)
+// OBSOLETE {
+// OBSOLETE int numbytes;
+// OBSOLETE char buf[2048];
+// OBSOLETE
+// OBSOLETE numbytes = min (sizeof buf, section_size - i);
+// OBSOLETE
+// OBSOLETE bfd_get_section_contents (abfd, s, buf, i, numbytes);
+// OBSOLETE
+// OBSOLETE serial_write (desc, buf, numbytes);
+// OBSOLETE
+// OBSOLETE if (hashmark)
+// OBSOLETE {
+// OBSOLETE putchar_unfiltered ('#');
+// OBSOLETE gdb_flush (gdb_stdout);
+// OBSOLETE }
+// OBSOLETE } /* Per-packet (or S-record) loop */
+// OBSOLETE
+// OBSOLETE monitor_expect_prompt (NULL, 0);
+// OBSOLETE
+// OBSOLETE putchar_unfiltered ('\n');
+// OBSOLETE } /* Loadable sections */
+// OBSOLETE
+// OBSOLETE monitor_printf ("reg pc %x\r", bfd_get_start_address (abfd));
+// OBSOLETE monitor_expect_prompt (NULL, 0);
+// OBSOLETE monitor_printf ("reg npc %x\r", bfd_get_start_address (abfd) + 4);
+// OBSOLETE monitor_expect_prompt (NULL, 0);
+// OBSOLETE
+// OBSOLETE monitor_printf ("run\r");
+// OBSOLETE
+// OBSOLETE end_time = time (NULL);
+// OBSOLETE
+// OBSOLETE if (hashmark)
+// OBSOLETE putchar_unfiltered ('\n');
+// OBSOLETE
+// OBSOLETE report_transfer_performance (data_count, start_time, end_time);
+// OBSOLETE
+// OBSOLETE pop_target ();
+// OBSOLETE push_remote_target (monitor_get_dev_name (), 1);
+// OBSOLETE
+// OBSOLETE throw_exception (RETURN_QUIT);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Define the monitor command strings. Since these are passed directly
+// OBSOLETE through to a printf style function, we may include formatting
+// OBSOLETE strings. We also need a CR or LF on the end. */
+// OBSOLETE
+// OBSOLETE /* need to pause the monitor for timing reasons, so slow it down */
+// OBSOLETE
+// OBSOLETE static char *sparclet_inits[] =
+// OBSOLETE {"\n\r\r\n", NULL};
+// OBSOLETE
+// OBSOLETE static struct monitor_ops sparclet_cmds;
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE init_sparclet_cmds (void)
+// OBSOLETE {
+// OBSOLETE sparclet_cmds.flags = MO_CLR_BREAK_USES_ADDR |
+// OBSOLETE MO_HEX_PREFIX |
+// OBSOLETE MO_NO_ECHO_ON_OPEN |
+// OBSOLETE MO_NO_ECHO_ON_SETMEM |
+// OBSOLETE MO_RUN_FIRST_TIME |
+// OBSOLETE MO_GETMEM_READ_SINGLE; /* flags */
+// OBSOLETE sparclet_cmds.init = sparclet_inits; /* Init strings */
+// OBSOLETE sparclet_cmds.cont = "cont\r"; /* continue command */
+// OBSOLETE sparclet_cmds.step = "step\r"; /* single step */
+// OBSOLETE sparclet_cmds.stop = "\r"; /* break interrupts the program */
+// OBSOLETE sparclet_cmds.set_break = "+bp %x\r"; /* set a breakpoint */
+// OBSOLETE sparclet_cmds.clr_break = "-bp %x\r"; /* can't use "br" because only 2 hw bps are supported */
+// OBSOLETE sparclet_cmds.clr_all_break = "-bp %x\r"; /* clear a breakpoint */
+// OBSOLETE "-bp\r"; /* clear all breakpoints */
+// OBSOLETE sparclet_cmds.fill = "fill %x -n %x -v %x -b\r"; /* fill (start length val) */
+// OBSOLETE /* can't use "fi" because it takes words, not bytes */
+// OBSOLETE /* ex [addr] [-n count] [-b|-s|-l] default: ex cur -n 1 -b */
+// OBSOLETE sparclet_cmds.setmem.cmdb = "ex %x -b\r%x\rq\r"; /* setmem.cmdb (addr, value) */
+// OBSOLETE sparclet_cmds.setmem.cmdw = "ex %x -s\r%x\rq\r"; /* setmem.cmdw (addr, value) */
+// OBSOLETE sparclet_cmds.setmem.cmdl = "ex %x -l\r%x\rq\r"; /* setmem.cmdl (addr, value) */
+// OBSOLETE sparclet_cmds.setmem.cmdll = NULL; /* setmem.cmdll (addr, value) */
+// OBSOLETE sparclet_cmds.setmem.resp_delim = NULL; /*": " *//* setmem.resp_delim */
+// OBSOLETE sparclet_cmds.setmem.term = NULL; /*"? " *//* setmem.term */
+// OBSOLETE sparclet_cmds.setmem.term_cmd = NULL; /*"q\r" *//* setmem.term_cmd */
+// OBSOLETE /* since the parsing of multiple bytes is difficult due to
+// OBSOLETE interspersed addresses, we'll only read 1 value at a time,
+// OBSOLETE even tho these can handle a count */
+// OBSOLETE /* we can use -n to set count to read, but may have to parse? */
+// OBSOLETE sparclet_cmds.getmem.cmdb = "ex %x -n 1 -b\r"; /* getmem.cmdb (addr, #bytes) */
+// OBSOLETE sparclet_cmds.getmem.cmdw = "ex %x -n 1 -s\r"; /* getmem.cmdw (addr, #swords) */
+// OBSOLETE sparclet_cmds.getmem.cmdl = "ex %x -n 1 -l\r"; /* getmem.cmdl (addr, #words) */
+// OBSOLETE sparclet_cmds.getmem.cmdll = NULL; /* getmem.cmdll (addr, #dwords) */
+// OBSOLETE sparclet_cmds.getmem.resp_delim = ": "; /* getmem.resp_delim */
+// OBSOLETE sparclet_cmds.getmem.term = NULL; /* getmem.term */
+// OBSOLETE sparclet_cmds.getmem.term_cmd = NULL; /* getmem.term_cmd */
+// OBSOLETE sparclet_cmds.setreg.cmd = "reg %s 0x%x\r"; /* setreg.cmd (name, value) */
+// OBSOLETE sparclet_cmds.setreg.resp_delim = NULL; /* setreg.resp_delim */
+// OBSOLETE sparclet_cmds.setreg.term = NULL; /* setreg.term */
+// OBSOLETE sparclet_cmds.setreg.term_cmd = NULL; /* setreg.term_cmd */
+// OBSOLETE sparclet_cmds.getreg.cmd = "reg %s\r"; /* getreg.cmd (name) */
+// OBSOLETE sparclet_cmds.getreg.resp_delim = " "; /* getreg.resp_delim */
+// OBSOLETE sparclet_cmds.getreg.term = NULL; /* getreg.term */
+// OBSOLETE sparclet_cmds.getreg.term_cmd = NULL; /* getreg.term_cmd */
+// OBSOLETE sparclet_cmds.dump_registers = "reg\r"; /* dump_registers */
+// OBSOLETE sparclet_cmds.register_pattern = "\\(\\w+\\)=\\([0-9a-fA-F]+\\)"; /* register_pattern */
+// OBSOLETE sparclet_cmds.supply_register = sparclet_supply_register; /* supply_register */
+// OBSOLETE sparclet_cmds.load_routine = sparclet_load; /* load_routine */
+// OBSOLETE sparclet_cmds.load = NULL; /* download command (srecs on console) */
+// OBSOLETE sparclet_cmds.loadresp = NULL; /* load response */
+// OBSOLETE sparclet_cmds.prompt = "monitor>"; /* monitor command prompt */
+// OBSOLETE /* yikes! gdb core dumps without this delimitor!! */
+// OBSOLETE sparclet_cmds.line_term = "\r"; /* end-of-command delimitor */
+// OBSOLETE sparclet_cmds.cmd_end = NULL; /* optional command terminator */
+// OBSOLETE sparclet_cmds.target = &sparclet_ops; /* target operations */
+// OBSOLETE sparclet_cmds.stopbits = SERIAL_1_STOPBITS; /* number of stop bits */
+// OBSOLETE sparclet_cmds.regnames = sparclet_regnames; /* registers names */
+// OBSOLETE sparclet_cmds.magic = MONITOR_OPS_MAGIC; /* magic */
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE sparclet_open (char *args, int from_tty)
+// OBSOLETE {
+// OBSOLETE monitor_open (args, &sparclet_cmds, from_tty);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE _initialize_sparclet (void)
+// OBSOLETE {
+// OBSOLETE int i;
+// OBSOLETE init_sparclet_cmds ();
+// OBSOLETE
+// OBSOLETE for (i = 0; i < NUM_REGS; i++)
+// OBSOLETE if (sparclet_regnames[i][0] == 'c' ||
+// OBSOLETE sparclet_regnames[i][0] == 'a')
+// OBSOLETE sparclet_regnames[i] = 0; /* mon can't report c* or a* regs */
+// OBSOLETE
+// OBSOLETE sparclet_regnames[0] = 0; /* mon won't report %G0 */
+// OBSOLETE
+// OBSOLETE init_monitor_ops (&sparclet_ops);
+// OBSOLETE sparclet_ops.to_shortname = "sparclet"; /* for the target command */
+// OBSOLETE sparclet_ops.to_longname = "SPARC Sparclet monitor";
+// OBSOLETE /* use SW breaks; target only supports 2 HW breakpoints */
+// OBSOLETE sparclet_ops.to_insert_breakpoint = memory_insert_breakpoint;
+// OBSOLETE sparclet_ops.to_remove_breakpoint = memory_remove_breakpoint;
+// OBSOLETE
+// OBSOLETE sparclet_ops.to_doc =
+// OBSOLETE "Use a board running the Sparclet debug monitor.\n\
+// OBSOLETE Specify the serial device it is connected to (e.g. /dev/ttya).";
+// OBSOLETE
+// OBSOLETE sparclet_ops.to_open = sparclet_open;
+// OBSOLETE add_target (&sparclet_ops);
+// OBSOLETE }
-/****************************************************************************
-
- THIS SOFTWARE IS NOT COPYRIGHTED
-
- HP offers the following for use in the public domain. HP makes no
- warranty with regard to the software or it's performance and the
- user accepts the software "AS IS" with all faults.
-
- HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
- TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-
-****************************************************************************/
-
-/****************************************************************************
- * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
- *
- * Module name: remcom.c $
- * Revision: 1.34 $
- * Date: 91/03/09 12:29:49 $
- * Contributor: Lake Stevens Instrument Division$
- *
- * Description: low level support for gdb debugger. $
- *
- * Considerations: only works on target hardware $
- *
- * Written by: Glenn Engel $
- * ModuleState: Experimental $
- *
- * NOTES: See Below $
- *
- * Modified for SPARC by Stu Grossman, Cygnus Support.
- * Based on sparc-stub.c, it's modified for SPARClite Debug Unit hardware
- * breakpoint support to create sparclite-stub.c, by Kung Hsu, Cygnus Support.
- *
- * This code has been extensively tested on the Fujitsu SPARClite demo board.
- *
- * To enable debugger support, two things need to happen. One, a
- * call to set_debug_traps() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint(). Breakpoint()
- * simulates a breakpoint by executing a trap #1.
- *
- *************
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- * P set the value of a single CPU register OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: <two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- ****************************************************************************/
-
-#include <string.h>
-#include <signal.h>
-
-/************************************************************************
- *
- * external low-level support routines
- */
-
-extern void putDebugChar(); /* write a single character */
-extern int getDebugChar(); /* read and return a single char */
-
-/************************************************************************/
-/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
-/* at least NUMREGBYTES*2 are needed for register packets */
-#define BUFMAX 2048
-
-static int initialized = 0; /* !0 means we've been initialized */
-static int remote_debug = 0; /* turn on verbose debugging */
-
-extern void breakinst();
-void _cprint();
-static void hw_breakpoint();
-static void set_mem_fault_trap();
-static void get_in_break_mode();
-static unsigned char *mem2hex();
-
-static const char hexchars[]="0123456789abcdef";
-
-#define NUMREGS 121
-
-static unsigned long saved_stack_pointer;
-
-/* Number of bytes of registers. */
-#define NUMREGBYTES (NUMREGS * 4)
-enum regnames { G0, G1, G2, G3, G4, G5, G6, G7,
- O0, O1, O2, O3, O4, O5, SP, O7,
- L0, L1, L2, L3, L4, L5, L6, L7,
- I0, I1, I2, I3, I4, I5, FP, I7,
-
- F0, F1, F2, F3, F4, F5, F6, F7,
- F8, F9, F10, F11, F12, F13, F14, F15,
- F16, F17, F18, F19, F20, F21, F22, F23,
- F24, F25, F26, F27, F28, F29, F30, F31,
-
- Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR,
- CCSR, CCPR, CCCRCR, CCOR, CCOBR, CCIBR, CCIR, UNUSED1,
-
- ASR1, ASR15, ASR17, ASR18, ASR19, ASR20, ASR21, ASR22,
- /* the following not actually implemented */
- AWR0, AWR1, AWR2, AWR3, AWR4, AWR5, AWR6, AWR7,
- AWR8, AWR9, AWR10, AWR11, AWR12, AWR13, AWR14, AWR15,
- AWR16, AWR17, AWR18, AWR19, AWR20, AWR21, AWR22, AWR23,
- AWR24, AWR25, AWR26, AWR27, AWR28, AWR29, AWR30, AWR31,
- APSR
-};
-
-/*************************** ASSEMBLY CODE MACROS *************************/
-/* */
-
-extern void trap_low();
-
-asm("
- .reserve trapstack, 1000 * 4, \"bss\", 8
-
- .data
- .align 4
-
-in_trap_handler:
- .word 0
-
- .text
- .align 4
-
-! This function is called when any SPARC trap (except window overflow or
-! underflow) occurs. It makes sure that the invalid register window is still
-! available before jumping into C code. It will also restore the world if you
-! return from handle_exception.
-!
-! On entry, trap_low expects l1 and l2 to contain pc and npc respectivly.
-
- .globl _trap_low
-_trap_low:
- mov %psr, %l0
- mov %wim, %l3
-
- srl %l3, %l0, %l4 ! wim >> cwp
- and %l4, 0xff, %l4 ! Mask off windows 28, 29
- cmp %l4, 1
- bne window_fine ! Branch if not in the invalid window
- nop
-
-! Handle window overflow
-
- mov %g1, %l4 ! Save g1, we use it to hold the wim
- srl %l3, 1, %g1 ! Rotate wim right
- and %g1, 0xff, %g1 ! Mask off windows 28, 29
- tst %g1
- bg good_wim ! Branch if new wim is non-zero
- nop
-
-! At this point, we need to bring a 1 into the high order bit of the wim.
-! Since we don't want to make any assumptions about the number of register
-! windows, we figure it out dynamically so as to setup the wim correctly.
-
- ! The normal way doesn't work on the sparclet as register windows
- ! 28 and 29 are special purpose windows.
- !not %g1 ! Fill g1 with ones
- !mov %g1, %wim ! Fill the wim with ones
- !nop
- !nop
- !nop
- !mov %wim, %g1 ! Read back the wim
- !inc %g1 ! Now g1 has 1 just to left of wim
- !srl %g1, 1, %g1 ! Now put 1 at top of wim
-
- mov 0x80, %g1 ! Hack for sparclet
-
- ! This doesn't work on the sparclet.
- !mov %g0, %wim ! Clear wim so that subsequent save
- ! won't trap
- andn %l3, 0xff, %l5 ! Clear wim but not windows 28, 29
- mov %l5, %wim
- nop
- nop
- nop
-
-good_wim:
- save %g0, %g0, %g0 ! Slip into next window
- mov %g1, %wim ! Install the new wim
-
- std %l0, [%sp + 0 * 4] ! save L & I registers
- std %l2, [%sp + 2 * 4]
- std %l4, [%sp + 4 * 4]
- std %l6, [%sp + 6 * 4]
-
- std %i0, [%sp + 8 * 4]
- std %i2, [%sp + 10 * 4]
- std %i4, [%sp + 12 * 4]
- std %i6, [%sp + 14 * 4]
-
- restore ! Go back to trap window.
- mov %l4, %g1 ! Restore %g1
-
-window_fine:
- sethi %hi(in_trap_handler), %l4
- ld [%lo(in_trap_handler) + %l4], %l5
- tst %l5
- bg recursive_trap
- inc %l5
-
- set trapstack+1000*4, %sp ! Switch to trap stack
-
-recursive_trap:
- st %l5, [%lo(in_trap_handler) + %l4]
- sub %sp,(16+1+6+1+88)*4,%sp ! Make room for input & locals
- ! + hidden arg + arg spill
- ! + doubleword alignment
- ! + registers[121]
-
- std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
- std %g2, [%sp + (24 + 2) * 4]
- std %g4, [%sp + (24 + 4) * 4]
- std %g6, [%sp + (24 + 6) * 4]
-
- std %i0, [%sp + (24 + 8) * 4] ! registers[Ox]
- std %i2, [%sp + (24 + 10) * 4]
- std %i4, [%sp + (24 + 12) * 4]
- std %i6, [%sp + (24 + 14) * 4]
-
- ! FP regs (sparclet doesn't have fpu)
-
- mov %y, %l4
- mov %tbr, %l5
- st %l4, [%sp + (24 + 64) * 4] ! Y
- st %l0, [%sp + (24 + 65) * 4] ! PSR
- st %l3, [%sp + (24 + 66) * 4] ! WIM
- st %l5, [%sp + (24 + 67) * 4] ! TBR
- st %l1, [%sp + (24 + 68) * 4] ! PC
- st %l2, [%sp + (24 + 69) * 4] ! NPC
- ! CPSR and FPSR not impl
- or %l0, 0xf20, %l4
- mov %l4, %psr ! Turn on traps, disable interrupts
- nop
- nop
- nop
-
-! Save coprocessor state.
-! See SK/demo/hdlc_demo/ldc_swap_context.S.
-
- mov %psr, %l0
- sethi %hi(0x2000), %l5 ! EC bit in PSR
- or %l5, %l0, %l5
- mov %l5, %psr ! enable coprocessor
- nop ! 3 nops after write to %psr (needed?)
- nop
- nop
- crdcxt %ccsr, %l1 ! capture CCSR
- mov 0x6, %l2
- cwrcxt %l2, %ccsr ! set CCP state machine for CCFR
- crdcxt %ccfr, %l2 ! capture CCOR
- cwrcxt %l2, %ccfr ! tickle CCFR
- crdcxt %ccfr, %l3 ! capture CCOBR
- cwrcxt %l3, %ccfr ! tickle CCFR
- crdcxt %ccfr, %l4 ! capture CCIBR
- cwrcxt %l4, %ccfr ! tickle CCFR
- crdcxt %ccfr, %l5 ! capture CCIR
- cwrcxt %l5, %ccfr ! tickle CCFR
- crdcxt %ccpr, %l6 ! capture CCPR
- crdcxt %cccrcr, %l7 ! capture CCCRCR
- st %l1, [%sp + (24 + 72) * 4] ! save CCSR
- st %l2, [%sp + (24 + 75) * 4] ! save CCOR
- st %l3, [%sp + (24 + 76) * 4] ! save CCOBR
- st %l4, [%sp + (24 + 77) * 4] ! save CCIBR
- st %l5, [%sp + (24 + 78) * 4] ! save CCIR
- st %l6, [%sp + (24 + 73) * 4] ! save CCPR
- st %l7, [%sp + (24 + 74) * 4] ! save CCCRCR
- mov %l0, %psr ! restore original PSR
- nop ! 3 nops after write to %psr (needed?)
- nop
- nop
-
-! End of saving coprocessor state.
-! Save asr regs
-
-! Part of this is silly -- we should not display ASR15 or ASR19 at all.
-
- sethi %hi(0x01000000), %l6
- st %l6, [%sp + (24 + 81) * 4] ! ASR15 == NOP
- sethi %hi(0xdeadc0de), %l6
- or %l6, %lo(0xdeadc0de), %l6
- st %l6, [%sp + (24 + 84) * 4] ! ASR19 == DEADC0DE
-
- rd %asr1, %l4
- st %l4, [%sp + (24 + 80) * 4]
-! rd %asr15, %l4 ! must not read ASR15
-! st %l4, [%sp + (24 + 81) * 4] ! (illegal instr trap)
- rd %asr17, %l4
- st %l4, [%sp + (24 + 82) * 4]
- rd %asr18, %l4
- st %l4, [%sp + (24 + 83) * 4]
-! rd %asr19, %l4 ! must not read asr19
-! st %l4, [%sp + (24 + 84) * 4] ! (halts the CPU)
- rd %asr20, %l4
- st %l4, [%sp + (24 + 85) * 4]
- rd %asr21, %l4
- st %l4, [%sp + (24 + 86) * 4]
- rd %asr22, %l4
- st %l4, [%sp + (24 + 87) * 4]
-
-! End of saving asr regs
-
- call _handle_exception
- add %sp, 24 * 4, %o0 ! Pass address of registers
-
-! Reload all of the registers that aren't on the stack
-
- ld [%sp + (24 + 1) * 4], %g1 ! registers[Gx]
- ldd [%sp + (24 + 2) * 4], %g2
- ldd [%sp + (24 + 4) * 4], %g4
- ldd [%sp + (24 + 6) * 4], %g6
-
- ldd [%sp + (24 + 8) * 4], %i0 ! registers[Ox]
- ldd [%sp + (24 + 10) * 4], %i2
- ldd [%sp + (24 + 12) * 4], %i4
- ldd [%sp + (24 + 14) * 4], %i6
-
- ! FP regs (sparclet doesn't have fpu)
-
-! Update the coprocessor registers.
-! See SK/demo/hdlc_demo/ldc_swap_context.S.
-
- mov %psr, %l0
- sethi %hi(0x2000), %l5 ! EC bit in PSR
- or %l5, %l0, %l5
- mov %l5, %psr ! enable coprocessor
- nop ! 3 nops after write to %psr (needed?)
- nop
- nop
-
- mov 0x6, %l2
- cwrcxt %l2, %ccsr ! set CCP state machine for CCFR
-
- ld [%sp + (24 + 72) * 4], %l1 ! saved CCSR
- ld [%sp + (24 + 75) * 4], %l2 ! saved CCOR
- ld [%sp + (24 + 76) * 4], %l3 ! saved CCOBR
- ld [%sp + (24 + 77) * 4], %l4 ! saved CCIBR
- ld [%sp + (24 + 78) * 4], %l5 ! saved CCIR
- ld [%sp + (24 + 73) * 4], %l6 ! saved CCPR
- ld [%sp + (24 + 74) * 4], %l7 ! saved CCCRCR
-
- cwrcxt %l2, %ccfr ! restore CCOR
- cwrcxt %l3, %ccfr ! restore CCOBR
- cwrcxt %l4, %ccfr ! restore CCIBR
- cwrcxt %l5, %ccfr ! restore CCIR
- cwrcxt %l6, %ccpr ! restore CCPR
- cwrcxt %l7, %cccrcr ! restore CCCRCR
- cwrcxt %l1, %ccsr ! restore CCSR
-
- mov %l0, %psr ! restore PSR
- nop ! 3 nops after write to %psr (needed?)
- nop
- nop
-
-! End of coprocessor handling stuff.
-! Update asr regs
-
- ld [%sp + (24 + 80) * 4], %l4
- wr %l4, %asr1
-! ld [%sp + (24 + 81) * 4], %l4 ! can't write asr15
-! wr %l4, %asr15
- ld [%sp + (24 + 82) * 4], %l4
- wr %l4, %asr17
- ld [%sp + (24 + 83) * 4], %l4
- wr %l4, %asr18
-! ld [%sp + (24 + 84) * 4], %l4 ! can't write asr19
-! wr %l4, %asr19
-! ld [%sp + (24 + 85) * 4], %l4 ! can't write asr20
-! wr %l4, %asr20
-! ld [%sp + (24 + 86) * 4], %l4 ! can't write asr21
-! wr %l4, %asr21
- ld [%sp + (24 + 87) * 4], %l4
- wr %l4, %asr22
-
-! End of restoring asr regs
-
-
- ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
- ldd [%sp + (24 + 68) * 4], %l2 ! PC & NPC
-
- restore ! Ensure that previous window is valid
- save %g0, %g0, %g0 ! by causing a window_underflow trap
-
- mov %l0, %y
- mov %l1, %psr ! Make sure that traps are disabled
- ! for rett
- nop ! 3 nops after write to %psr (needed?)
- nop
- nop
-
- sethi %hi(in_trap_handler), %l4
- ld [%lo(in_trap_handler) + %l4], %l5
- dec %l5
- st %l5, [%lo(in_trap_handler) + %l4]
-
- jmpl %l2, %g0 ! Restore old PC
- rett %l3 ! Restore old nPC
-");
-
-/* Convert ch from a hex digit to an int */
-
-static int
-hex (unsigned char ch)
-{
- if (ch >= 'a' && ch <= 'f')
- return ch-'a'+10;
- if (ch >= '0' && ch <= '9')
- return ch-'0';
- if (ch >= 'A' && ch <= 'F')
- return ch-'A'+10;
- return -1;
-}
-
-static char remcomInBuffer[BUFMAX];
-static char remcomOutBuffer[BUFMAX];
-
-/* scan for the sequence $<data>#<checksum> */
-
-unsigned char *
-getpacket (void)
-{
- unsigned char *buffer = &remcomInBuffer[0];
- unsigned char checksum;
- unsigned char xmitcsum;
- int count;
- char ch;
-
- while (1)
- {
- /* wait around for the start character, ignore all other characters */
- while ((ch = getDebugChar ()) != '$')
- ;
-
-retry:
- checksum = 0;
- xmitcsum = -1;
- count = 0;
-
- /* now, read until a # or end of buffer is found */
- while (count < BUFMAX)
- {
- ch = getDebugChar ();
- if (ch == '$')
- goto retry;
- if (ch == '#')
- break;
- checksum = checksum + ch;
- buffer[count] = ch;
- count = count + 1;
- }
- buffer[count] = 0;
-
- if (ch == '#')
- {
- ch = getDebugChar ();
- xmitcsum = hex (ch) << 4;
- ch = getDebugChar ();
- xmitcsum += hex (ch);
-
- if (checksum != xmitcsum)
- {
- putDebugChar ('-'); /* failed checksum */
- }
- else
- {
- putDebugChar ('+'); /* successful transfer */
-
- /* if a sequence char is present, reply the sequence ID */
- if (buffer[2] == ':')
- {
- putDebugChar (buffer[0]);
- putDebugChar (buffer[1]);
-
- return &buffer[3];
- }
-
- return &buffer[0];
- }
- }
- }
-}
-
-/* send the packet in buffer. */
-
-static void
-putpacket (unsigned char *buffer)
-{
- unsigned char checksum;
- int count;
- unsigned char ch;
-
- /* $<packet info>#<checksum>. */
- do
- {
- putDebugChar('$');
- checksum = 0;
- count = 0;
-
- while (ch = buffer[count])
- {
- putDebugChar(ch);
- checksum += ch;
- count += 1;
- }
-
- putDebugChar('#');
- putDebugChar(hexchars[checksum >> 4]);
- putDebugChar(hexchars[checksum & 0xf]);
-
- }
- while (getDebugChar() != '+');
-}
-
-/* Indicate to caller of mem2hex or hex2mem that there has been an
- error. */
-static volatile int mem_err = 0;
-
-/* Convert the memory pointed to by mem into hex, placing result in buf.
- * Return a pointer to the last char put in buf (null), in case of mem fault,
- * return 0.
- * If MAY_FAULT is non-zero, then we will handle memory faults by returning
- * a 0, else treat a fault like any other fault in the stub.
- */
-
-static unsigned char *
-mem2hex (unsigned char *mem, unsigned char *buf, int count, int may_fault)
-{
- unsigned char ch;
-
- set_mem_fault_trap(may_fault);
-
- while (count-- > 0)
- {
- ch = *mem++;
- if (mem_err)
- return 0;
- *buf++ = hexchars[ch >> 4];
- *buf++ = hexchars[ch & 0xf];
- }
-
- *buf = 0;
-
- set_mem_fault_trap(0);
-
- return buf;
-}
-
-/* convert the hex array pointed to by buf into binary to be placed in mem
- * return a pointer to the character AFTER the last byte written */
-
-static char *
-hex2mem (unsigned char *buf, unsigned char *mem, int count, int may_fault)
-{
- int i;
- unsigned char ch;
-
- set_mem_fault_trap(may_fault);
-
- for (i=0; i<count; i++)
- {
- ch = hex(*buf++) << 4;
- ch |= hex(*buf++);
- *mem++ = ch;
- if (mem_err)
- return 0;
- }
-
- set_mem_fault_trap(0);
-
- return mem;
-}
-
-/* This table contains the mapping between SPARC hardware trap types, and
- signals, which are primarily what GDB understands. It also indicates
- which hardware traps we need to commandeer when initializing the stub. */
-
-static struct hard_trap_info
-{
- unsigned char tt; /* Trap type code for SPARClite */
- unsigned char signo; /* Signal that we map this trap into */
-} hard_trap_info[] = {
- {1, SIGSEGV}, /* instruction access exception */
- {0x3b, SIGSEGV}, /* instruction access error */
- {2, SIGILL}, /* illegal instruction */
- {3, SIGILL}, /* privileged instruction */
- {4, SIGEMT}, /* fp disabled */
- {0x24, SIGEMT}, /* cp disabled */
- {7, SIGBUS}, /* mem address not aligned */
- {0x29, SIGSEGV}, /* data access exception */
- {10, SIGEMT}, /* tag overflow */
- {128+1, SIGTRAP}, /* ta 1 - normal breakpoint instruction */
- {0, 0} /* Must be last */
-};
-
-/* Set up exception handlers for tracing and breakpoints */
-
-void
-set_debug_traps (void)
-{
- struct hard_trap_info *ht;
-
- for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
- exceptionHandler(ht->tt, trap_low);
-
- initialized = 1;
-}
-
-asm ("
-! Trap handler for memory errors. This just sets mem_err to be non-zero. It
-! assumes that %l1 is non-zero. This should be safe, as it is doubtful that
-! 0 would ever contain code that could mem fault. This routine will skip
-! past the faulting instruction after setting mem_err.
-
- .text
- .align 4
-
-_fltr_set_mem_err:
- sethi %hi(_mem_err), %l0
- st %l1, [%l0 + %lo(_mem_err)]
- jmpl %l2, %g0
- rett %l2+4
-");
-
-static void
-set_mem_fault_trap (int enable)
-{
- extern void fltr_set_mem_err();
- mem_err = 0;
-
- if (enable)
- exceptionHandler(0x29, fltr_set_mem_err);
- else
- exceptionHandler(0x29, trap_low);
-}
-
-asm ("
- .text
- .align 4
-
-_dummy_hw_breakpoint:
- jmpl %l2, %g0
- rett %l2+4
- nop
- nop
-");
-
-static void
-set_hw_breakpoint_trap (int enable)
-{
- extern void dummy_hw_breakpoint();
-
- if (enable)
- exceptionHandler(255, dummy_hw_breakpoint);
- else
- exceptionHandler(255, trap_low);
-}
-
-static void
-get_in_break_mode (void)
-{
-#if 0
- int x;
- mesg("get_in_break_mode, sp = ");
- phex(&x);
-#endif
- set_hw_breakpoint_trap(1);
-
- asm("
- sethi %hi(0xff10), %l4
- or %l4, %lo(0xff10), %l4
- sta %g0, [%l4]0x1
- nop
- nop
- nop
- ");
-
- set_hw_breakpoint_trap(0);
-}
-
-/* Convert the SPARC hardware trap type code to a unix signal number. */
-
-static int
-computeSignal (int tt)
-{
- struct hard_trap_info *ht;
-
- for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
- if (ht->tt == tt)
- return ht->signo;
-
- return SIGHUP; /* default for things we don't know about */
-}
-
-/*
- * While we find nice hex chars, build an int.
- * Return number of chars processed.
- */
-
-static int
-hexToInt(char **ptr, int *intValue)
-{
- int numChars = 0;
- int hexValue;
-
- *intValue = 0;
-
- while (**ptr)
- {
- hexValue = hex(**ptr);
- if (hexValue < 0)
- break;
-
- *intValue = (*intValue << 4) | hexValue;
- numChars ++;
-
- (*ptr)++;
- }
-
- return (numChars);
-}
-
-/*
- * This function does all command procesing for interfacing to gdb. It
- * returns 1 if you should skip the instruction at the trap address, 0
- * otherwise.
- */
-
-static void
-handle_exception (unsigned long *registers)
-{
- int tt; /* Trap type */
- int sigval;
- int addr;
- int length;
- char *ptr;
- unsigned long *sp;
- unsigned long dsr;
-
-/* First, we must force all of the windows to be spilled out */
-
- asm("
- ! Ugh. sparclet has broken save
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- !save %sp, -64, %sp
- save
- add %fp,-64,%sp
- restore
- restore
- restore
- restore
- restore
- restore
- restore
- restore
-");
-
- if (registers[PC] == (unsigned long)breakinst)
- {
- registers[PC] = registers[NPC];
- registers[NPC] += 4;
- }
- sp = (unsigned long *)registers[SP];
-
- tt = (registers[TBR] >> 4) & 0xff;
-
- /* reply to host that an exception has occurred */
- sigval = computeSignal(tt);
- ptr = remcomOutBuffer;
-
- *ptr++ = 'T';
- *ptr++ = hexchars[sigval >> 4];
- *ptr++ = hexchars[sigval & 0xf];
-
- *ptr++ = hexchars[PC >> 4];
- *ptr++ = hexchars[PC & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)®isters[PC], ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = hexchars[FP >> 4];
- *ptr++ = hexchars[FP & 0xf];
- *ptr++ = ':';
- ptr = mem2hex(sp + 8 + 6, ptr, 4, 0); /* FP */
- *ptr++ = ';';
-
- *ptr++ = hexchars[SP >> 4];
- *ptr++ = hexchars[SP & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)&sp, ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = hexchars[NPC >> 4];
- *ptr++ = hexchars[NPC & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)®isters[NPC], ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = hexchars[O7 >> 4];
- *ptr++ = hexchars[O7 & 0xf];
- *ptr++ = ':';
- ptr = mem2hex((char *)®isters[O7], ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = 0;
-
- putpacket(remcomOutBuffer);
-
- while (1)
- {
- remcomOutBuffer[0] = 0;
-
- ptr = getpacket();
- switch (*ptr++)
- {
- case '?':
- remcomOutBuffer[0] = 'S';
- remcomOutBuffer[1] = hexchars[sigval >> 4];
- remcomOutBuffer[2] = hexchars[sigval & 0xf];
- remcomOutBuffer[3] = 0;
- break;
-
- case 'd':
- remote_debug = !(remote_debug); /* toggle debug flag */
- break;
-
- case 'g': /* return the value of the CPU registers */
- {
- ptr = remcomOutBuffer;
- ptr = mem2hex((char *)registers, ptr, 16 * 4, 0); /* G & O regs */
- ptr = mem2hex(sp + 0, ptr, 16 * 4, 0); /* L & I regs */
- memset(ptr, '0', 32 * 8); /* Floating point */
- ptr = mem2hex((char *)®isters[Y],
- ptr + 32 * 4 * 2,
- 8 * 4,
- 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
- ptr = mem2hex((char *)®isters[CCSR],
- ptr,
- 8 * 4,
- 0); /* CCSR, CCPR, CCCRCR, CCOR, CCOBR, CCIBR, CCIR */
- ptr = mem2hex((char *)®isters[ASR1],
- ptr,
- 8 * 4,
- 0); /* ASR1,ASR15,ASR17,ASR18,ASR19,ASR20,ASR21,ASR22 */
-#if 0 /* not implemented */
- ptr = mem2hex((char *) ®isters[AWR0],
- ptr,
- 32 * 4,
- 0); /* Alternate Window Registers */
-#endif
- }
- break;
-
- case 'G': /* set value of all the CPU registers - return OK */
- case 'P': /* set value of one CPU register - return OK */
- {
- unsigned long *newsp, psr;
-
- psr = registers[PSR];
-
- if (ptr[-1] == 'P') /* do a single register */
- {
- int regno;
-
- if (hexToInt (&ptr, ®no)
- && *ptr++ == '=')
- if (regno >= L0 && regno <= I7)
- hex2mem (ptr, sp + regno - L0, 4, 0);
- else
- hex2mem (ptr, (char *)®isters[regno], 4, 0);
- else
- {
- strcpy (remcomOutBuffer, "E01");
- break;
- }
- }
- else
- {
- hex2mem(ptr, (char *)registers, 16 * 4, 0); /* G & O regs */
- hex2mem(ptr + 16 * 4 * 2, sp + 0, 16 * 4, 0); /* L & I regs */
- hex2mem(ptr + 64 * 4 * 2, (char *)®isters[Y],
- 8 * 4, 0); /* Y,PSR,WIM,TBR,PC,NPC,FPSR,CPSR */
- hex2mem(ptr + 72 * 4 * 2, (char *)®isters[CCSR],
- 8 * 4, 0); /* CCSR,CCPR,CCCRCR,CCOR,CCOBR,CCIBR,CCIR */
- hex2mem(ptr + 80 * 4 * 2, (char *)®isters[ASR1],
- 8 * 4, 0); /* ASR1 ... ASR22 */
-#if 0 /* not implemented */
- hex2mem(ptr + 88 * 4 * 2, (char *)®isters[AWR0],
- 8 * 4, 0); /* Alternate Window Registers */
-#endif
- }
- /* See if the stack pointer has moved. If so, then copy the saved
- locals and ins to the new location. This keeps the window
- overflow and underflow routines happy. */
-
- newsp = (unsigned long *)registers[SP];
- if (sp != newsp)
- sp = memcpy(newsp, sp, 16 * 4);
-
- /* Don't allow CWP to be modified. */
-
- if (psr != registers[PSR])
- registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f);
-
- strcpy(remcomOutBuffer,"OK");
- }
- break;
-
- case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
- /* Try to read %x,%x. */
-
- if (hexToInt(&ptr, &addr)
- && *ptr++ == ','
- && hexToInt(&ptr, &length))
- {
- if (mem2hex((char *)addr, remcomOutBuffer, length, 1))
- break;
-
- strcpy (remcomOutBuffer, "E03");
- }
- else
- strcpy(remcomOutBuffer,"E01");
- break;
-
- case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
- /* Try to read '%x,%x:'. */
-
- if (hexToInt(&ptr, &addr)
- && *ptr++ == ','
- && hexToInt(&ptr, &length)
- && *ptr++ == ':')
- {
- if (hex2mem(ptr, (char *)addr, length, 1))
- strcpy(remcomOutBuffer, "OK");
- else
- strcpy(remcomOutBuffer, "E03");
- }
- else
- strcpy(remcomOutBuffer, "E02");
- break;
-
- case 'c': /* cAA..AA Continue at address AA..AA(optional) */
- /* try to read optional parameter, pc unchanged if no parm */
-
- if (hexToInt(&ptr, &addr))
- {
- registers[PC] = addr;
- registers[NPC] = addr + 4;
- }
-
-/* Need to flush the instruction cache here, as we may have deposited a
- breakpoint, and the icache probably has no way of knowing that a data ref to
- some location may have changed something that is in the instruction cache.
- */
-
- flush_i_cache();
- return;
-
- /* kill the program */
- case 'k' : /* do nothing */
- break;
-#if 0
- case 't': /* Test feature */
- asm (" std %f30,[%sp]");
- break;
-#endif
- case 'r': /* Reset */
- asm ("call 0
- nop ");
- break;
- } /* switch */
-
- /* reply to the request */
- putpacket(remcomOutBuffer);
- }
-}
-
-/* This function will generate a breakpoint exception. It is used at the
- beginning of a program to sync up with a debugger and can be used
- otherwise as a quick means to stop program execution and "break" into
- the debugger. */
-
-void
-breakpoint (void)
-{
- if (!initialized)
- return;
-
- asm(" .globl _breakinst
-
- _breakinst: ta 1
- ");
-}
-
-static void
-hw_breakpoint (void)
-{
- asm("
- ta 127
- ");
-}
-
-#if 0 /* experimental and never finished, left here for reference */
-static void
-splet_temp(void)
-{
- asm(" sub %sp,(16+1+6+1+121)*4,%sp ! Make room for input & locals
- ! + hidden arg + arg spill
- ! + doubleword alignment
- ! + registers[121]
-
-! Leave a trail of breadcrumbs! (save register save area for debugging)
- mov %sp, %l0
- add %l0, 24*4, %l0
- sethi %hi(_debug_registers), %l1
- st %l0, [%lo(_debug_registers) + %l1]
-
-! Save the Alternate Register Set: (not implemented yet)
-! To save the Alternate Register set, we must:
-! 1) Save the current SP in some global location.
-! 2) Swap the register sets.
-! 3) Save the Alternate SP in the Y register
-! 4) Fetch the SP that we saved in step 1.
-! 5) Use that to save the rest of the regs (not forgetting ASP in Y)
-! 6) Restore the Alternate SP from Y
-! 7) Swap the registers back.
-
-! 1) Copy the current stack pointer to global _SAVED_STACK_POINTER:
- sethi %hi(_saved_stack_pointer), %l0
- st %sp, [%lo(_saved_stack_pointer) + %l0]
-
-! 2) Swap the register sets:
- mov %psr, %l1
- sethi %hi(0x10000), %l2
- xor %l1, %l2, %l1
- mov %l1, %psr
- nop ! 3 nops after write to %psr (needed?)
- nop
- nop
-
-! 3) Save Alternate L0 in Y
- wr %l0, 0, %y
-
-! 4) Load former SP into alternate SP, using L0
- sethi %hi(_saved_stack_pointer), %l0
- or %lo(_saved_stack_pointer), %l0, %l0
- swap [%l0], %sp
-
-! 4.5) Restore alternate L0
- rd %y, %l0
-
-! 5) Save the Alternate Window Registers
- st %r0, [%sp + (24 + 88) * 4] ! AWR0
- st %r1, [%sp + (24 + 89) * 4] ! AWR1
- st %r2, [%sp + (24 + 90) * 4] ! AWR2
- st %r3, [%sp + (24 + 91) * 4] ! AWR3
- st %r4, [%sp + (24 + 92) * 4] ! AWR4
- st %r5, [%sp + (24 + 93) * 4] ! AWR5
- st %r6, [%sp + (24 + 94) * 4] ! AWR6
- st %r7, [%sp + (24 + 95) * 4] ! AWR7
- st %r8, [%sp + (24 + 96) * 4] ! AWR8
- st %r9, [%sp + (24 + 97) * 4] ! AWR9
- st %r10, [%sp + (24 + 98) * 4] ! AWR10
- st %r11, [%sp + (24 + 99) * 4] ! AWR11
- st %r12, [%sp + (24 + 100) * 4] ! AWR12
- st %r13, [%sp + (24 + 101) * 4] ! AWR13
-! st %r14, [%sp + (24 + 102) * 4] ! AWR14 (SP)
- st %r15, [%sp + (24 + 103) * 4] ! AWR15
- st %r16, [%sp + (24 + 104) * 4] ! AWR16
- st %r17, [%sp + (24 + 105) * 4] ! AWR17
- st %r18, [%sp + (24 + 106) * 4] ! AWR18
- st %r19, [%sp + (24 + 107) * 4] ! AWR19
- st %r20, [%sp + (24 + 108) * 4] ! AWR20
- st %r21, [%sp + (24 + 109) * 4] ! AWR21
- st %r22, [%sp + (24 + 110) * 4] ! AWR22
- st %r23, [%sp + (24 + 111) * 4] ! AWR23
- st %r24, [%sp + (24 + 112) * 4] ! AWR24
- st %r25, [%sp + (24 + 113) * 4] ! AWR25
- st %r26, [%sp + (24 + 114) * 4] ! AWR26
- st %r27, [%sp + (24 + 115) * 4] ! AWR27
- st %r28, [%sp + (24 + 116) * 4] ! AWR28
- st %r29, [%sp + (24 + 117) * 4] ! AWR29
- st %r30, [%sp + (24 + 118) * 4] ! AWR30
- st %r31, [%sp + (24 + 119) * 4] ! AWR21
-
-! Get the Alternate PSR (I hope...)
-
- rd %psr, %l2
- st %l2, [%sp + (24 + 120) * 4] ! APSR
-
-! Don't forget the alternate stack pointer
-
- rd %y, %l3
- st %l3, [%sp + (24 + 102) * 4] ! AWR14 (SP)
-
-! 6) Restore the Alternate SP (saved in Y)
-
- rd %y, %o6
-
-
-! 7) Swap the registers back:
-
- mov %psr, %l1
- sethi %hi(0x10000), %l2
- xor %l1, %l2, %l1
- mov %l1, %psr
- nop ! 3 nops after write to %psr (needed?)
- nop
- nop
-");
-}
-
-#endif
+// OBSOLETE /****************************************************************************
+// OBSOLETE
+// OBSOLETE THIS SOFTWARE IS NOT COPYRIGHTED
+// OBSOLETE
+// OBSOLETE HP offers the following for use in the public domain. HP makes no
+// OBSOLETE warranty with regard to the software or it's performance and the
+// OBSOLETE user accepts the software "AS IS" with all faults.
+// OBSOLETE
+// OBSOLETE HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
+// OBSOLETE TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OBSOLETE OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+// OBSOLETE
+// OBSOLETE ****************************************************************************/
+// OBSOLETE
+// OBSOLETE /****************************************************************************
+// OBSOLETE * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
+// OBSOLETE *
+// OBSOLETE * Module name: remcom.c $
+// OBSOLETE * Revision: 1.34 $
+// OBSOLETE * Date: 91/03/09 12:29:49 $
+// OBSOLETE * Contributor: Lake Stevens Instrument Division$
+// OBSOLETE *
+// OBSOLETE * Description: low level support for gdb debugger. $
+// OBSOLETE *
+// OBSOLETE * Considerations: only works on target hardware $
+// OBSOLETE *
+// OBSOLETE * Written by: Glenn Engel $
+// OBSOLETE * ModuleState: Experimental $
+// OBSOLETE *
+// OBSOLETE * NOTES: See Below $
+// OBSOLETE *
+// OBSOLETE * Modified for SPARC by Stu Grossman, Cygnus Support.
+// OBSOLETE * Based on sparc-stub.c, it's modified for SPARClite Debug Unit hardware
+// OBSOLETE * breakpoint support to create sparclite-stub.c, by Kung Hsu, Cygnus Support.
+// OBSOLETE *
+// OBSOLETE * This code has been extensively tested on the Fujitsu SPARClite demo board.
+// OBSOLETE *
+// OBSOLETE * To enable debugger support, two things need to happen. One, a
+// OBSOLETE * call to set_debug_traps() is necessary in order to allow any breakpoints
+// OBSOLETE * or error conditions to be properly intercepted and reported to gdb.
+// OBSOLETE * Two, a breakpoint needs to be generated to begin communication. This
+// OBSOLETE * is most easily accomplished by a call to breakpoint(). Breakpoint()
+// OBSOLETE * simulates a breakpoint by executing a trap #1.
+// OBSOLETE *
+// OBSOLETE *************
+// OBSOLETE *
+// OBSOLETE * The following gdb commands are supported:
+// OBSOLETE *
+// OBSOLETE * command function Return value
+// OBSOLETE *
+// OBSOLETE * g return the value of the CPU registers hex data or ENN
+// OBSOLETE * G set the value of the CPU registers OK or ENN
+// OBSOLETE * P set the value of a single CPU register OK or ENN
+// OBSOLETE *
+// OBSOLETE * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
+// OBSOLETE * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
+// OBSOLETE *
+// OBSOLETE * c Resume at current address SNN ( signal NN)
+// OBSOLETE * cAA..AA Continue at address AA..AA SNN
+// OBSOLETE *
+// OBSOLETE * s Step one instruction SNN
+// OBSOLETE * sAA..AA Step one instruction from AA..AA SNN
+// OBSOLETE *
+// OBSOLETE * k kill
+// OBSOLETE *
+// OBSOLETE * ? What was the last sigval ? SNN (signal NN)
+// OBSOLETE *
+// OBSOLETE * All commands and responses are sent with a packet which includes a
+// OBSOLETE * checksum. A packet consists of
+// OBSOLETE *
+
// OBSOLETE * $<packet info>#<checksum>.
+// OBSOLETE *
+// OBSOLETE * where
+
// OBSOLETE * <packet info> :: <characters representing the command or response>
+
// OBSOLETE * <checksum> :: <two hex digits computed as modulo 256 sum of <packetinfo>>
+// OBSOLETE *
+// OBSOLETE * When a packet is received, it is first acknowledged with either '+' or '-'.
+// OBSOLETE * '+' indicates a successful transfer. '-' indicates a failed transfer.
+// OBSOLETE *
+// OBSOLETE * Example:
+// OBSOLETE *
+// OBSOLETE * Host: Reply:
+// OBSOLETE * $m0,10#2a +$00010203040506070809101112131415#42
+// OBSOLETE *
+// OBSOLETE ****************************************************************************/
+// OBSOLETE
+// OBSOLETE #include <string.h>
+// OBSOLETE #include <signal.h>
+// OBSOLETE
+// OBSOLETE /************************************************************************
+// OBSOLETE *
+// OBSOLETE * external low-level support routines
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE extern void putDebugChar(); /* write a single character */
+// OBSOLETE extern int getDebugChar(); /* read and return a single char */
+// OBSOLETE
+// OBSOLETE /************************************************************************/
+// OBSOLETE /* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
+// OBSOLETE /* at least NUMREGBYTES*2 are needed for register packets */
+// OBSOLETE #define BUFMAX 2048
+// OBSOLETE
+// OBSOLETE static int initialized = 0; /* !0 means we've been initialized */
+// OBSOLETE static int remote_debug = 0; /* turn on verbose debugging */
+// OBSOLETE
+// OBSOLETE extern void breakinst();
+// OBSOLETE void _cprint();
+// OBSOLETE static void hw_breakpoint();
+// OBSOLETE static void set_mem_fault_trap();
+// OBSOLETE static void get_in_break_mode();
+// OBSOLETE static unsigned char *mem2hex();
+// OBSOLETE
+// OBSOLETE static const char hexchars[]="0123456789abcdef";
+// OBSOLETE
+// OBSOLETE #define NUMREGS 121
+// OBSOLETE
+// OBSOLETE static unsigned long saved_stack_pointer;
+// OBSOLETE
+// OBSOLETE /* Number of bytes of registers. */
+// OBSOLETE #define NUMREGBYTES (NUMREGS * 4)
+// OBSOLETE enum regnames { G0, G1, G2, G3, G4, G5, G6, G7,
+// OBSOLETE O0, O1, O2, O3, O4, O5, SP, O7,
+// OBSOLETE L0, L1, L2, L3, L4, L5, L6, L7,
+// OBSOLETE I0, I1, I2, I3, I4, I5, FP, I7,
+// OBSOLETE
+// OBSOLETE F0, F1, F2, F3, F4, F5, F6, F7,
+// OBSOLETE F8, F9, F10, F11, F12, F13, F14, F15,
+// OBSOLETE F16, F17, F18, F19, F20, F21, F22, F23,
+// OBSOLETE F24, F25, F26, F27, F28, F29, F30, F31,
+// OBSOLETE
+// OBSOLETE Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR,
+// OBSOLETE CCSR, CCPR, CCCRCR, CCOR, CCOBR, CCIBR, CCIR, UNUSED1,
+// OBSOLETE
+// OBSOLETE ASR1, ASR15, ASR17, ASR18, ASR19, ASR20, ASR21, ASR22,
+// OBSOLETE /* the following not actually implemented */
+// OBSOLETE AWR0, AWR1, AWR2, AWR3, AWR4, AWR5, AWR6, AWR7,
+// OBSOLETE AWR8, AWR9, AWR10, AWR11, AWR12, AWR13, AWR14, AWR15,
+// OBSOLETE AWR16, AWR17, AWR18, AWR19, AWR20, AWR21, AWR22, AWR23,
+// OBSOLETE AWR24, AWR25, AWR26, AWR27, AWR28, AWR29, AWR30, AWR31,
+// OBSOLETE APSR
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE /*************************** ASSEMBLY CODE MACROS *************************/
+// OBSOLETE /* */
+// OBSOLETE
+// OBSOLETE extern void trap_low();
+// OBSOLETE
+// OBSOLETE asm("
+// OBSOLETE .reserve trapstack, 1000 * 4, \"bss\", 8
+// OBSOLETE
+// OBSOLETE .data
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE in_trap_handler:
+// OBSOLETE .word 0
+// OBSOLETE
+// OBSOLETE .text
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE ! This function is called when any SPARC trap (except window overflow or
+// OBSOLETE ! underflow) occurs. It makes sure that the invalid register window is still
+// OBSOLETE ! available before jumping into C code. It will also restore the world if you
+// OBSOLETE ! return from handle_exception.
+// OBSOLETE !
+// OBSOLETE ! On entry, trap_low expects l1 and l2 to contain pc and npc respectivly.
+// OBSOLETE
+// OBSOLETE .globl _trap_low
+// OBSOLETE _trap_low:
+// OBSOLETE mov %psr, %l0
+// OBSOLETE mov %wim, %l3
+// OBSOLETE
+// OBSOLETE srl %l3, %l0, %l4 ! wim >> cwp
+// OBSOLETE and %l4, 0xff, %l4 ! Mask off windows 28, 29
+// OBSOLETE cmp %l4, 1
+// OBSOLETE bne window_fine ! Branch if not in the invalid window
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! Handle window overflow
+// OBSOLETE
+// OBSOLETE mov %g1, %l4 ! Save g1, we use it to hold the wim
+// OBSOLETE srl %l3, 1, %g1 ! Rotate wim right
+// OBSOLETE and %g1, 0xff, %g1 ! Mask off windows 28, 29
+// OBSOLETE tst %g1
+// OBSOLETE bg good_wim ! Branch if new wim is non-zero
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! At this point, we need to bring a 1 into the high order bit of the wim.
+// OBSOLETE ! Since we don't want to make any assumptions about the number of register
+// OBSOLETE ! windows, we figure it out dynamically so as to setup the wim correctly.
+// OBSOLETE
+// OBSOLETE ! The normal way doesn't work on the sparclet as register windows
+// OBSOLETE ! 28 and 29 are special purpose windows.
+// OBSOLETE !not %g1 ! Fill g1 with ones
+// OBSOLETE !mov %g1, %wim ! Fill the wim with ones
+// OBSOLETE !nop
+// OBSOLETE !nop
+// OBSOLETE !nop
+// OBSOLETE !mov %wim, %g1 ! Read back the wim
+// OBSOLETE !inc %g1 ! Now g1 has 1 just to left of wim
+// OBSOLETE !srl %g1, 1, %g1 ! Now put 1 at top of wim
+// OBSOLETE
+// OBSOLETE mov 0x80, %g1 ! Hack for sparclet
+// OBSOLETE
+// OBSOLETE ! This doesn't work on the sparclet.
+// OBSOLETE !mov %g0, %wim ! Clear wim so that subsequent save
+// OBSOLETE ! won't trap
+// OBSOLETE andn %l3, 0xff, %l5 ! Clear wim but not windows 28, 29
+// OBSOLETE mov %l5, %wim
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE good_wim:
+// OBSOLETE save %g0, %g0, %g0 ! Slip into next window
+// OBSOLETE mov %g1, %wim ! Install the new wim
+// OBSOLETE
+// OBSOLETE std %l0, [%sp + 0 * 4] ! save L & I registers
+// OBSOLETE std %l2, [%sp + 2 * 4]
+// OBSOLETE std %l4, [%sp + 4 * 4]
+// OBSOLETE std %l6, [%sp + 6 * 4]
+// OBSOLETE
+// OBSOLETE std %i0, [%sp + 8 * 4]
+// OBSOLETE std %i2, [%sp + 10 * 4]
+// OBSOLETE std %i4, [%sp + 12 * 4]
+// OBSOLETE std %i6, [%sp + 14 * 4]
+// OBSOLETE
+// OBSOLETE restore ! Go back to trap window.
+// OBSOLETE mov %l4, %g1 ! Restore %g1
+// OBSOLETE
+// OBSOLETE window_fine:
+// OBSOLETE sethi %hi(in_trap_handler), %l4
+// OBSOLETE ld [%lo(in_trap_handler) + %l4], %l5
+// OBSOLETE tst %l5
+// OBSOLETE bg recursive_trap
+// OBSOLETE inc %l5
+// OBSOLETE
+// OBSOLETE set trapstack+1000*4, %sp ! Switch to trap stack
+// OBSOLETE
+// OBSOLETE recursive_trap:
+// OBSOLETE st %l5, [%lo(in_trap_handler) + %l4]
+// OBSOLETE sub %sp,(16+1+6+1+88)*4,%sp ! Make room for input & locals
+// OBSOLETE ! + hidden arg + arg spill
+// OBSOLETE ! + doubleword alignment
+// OBSOLETE ! + registers[121]
+// OBSOLETE
+// OBSOLETE std %g0, [%sp + (24 + 0) * 4] ! registers[Gx]
+// OBSOLETE std %g2, [%sp + (24 + 2) * 4]
+// OBSOLETE std %g4, [%sp + (24 + 4) * 4]
+// OBSOLETE std %g6, [%sp + (24 + 6) * 4]
+// OBSOLETE
+// OBSOLETE std %i0, [%sp + (24 + 8) * 4] ! registers[Ox]
+// OBSOLETE std %i2, [%sp + (24 + 10) * 4]
+// OBSOLETE std %i4, [%sp + (24 + 12) * 4]
+// OBSOLETE std %i6, [%sp + (24 + 14) * 4]
+// OBSOLETE
+// OBSOLETE ! FP regs (sparclet doesn't have fpu)
+// OBSOLETE
+// OBSOLETE mov %y, %l4
+// OBSOLETE mov %tbr, %l5
+// OBSOLETE st %l4, [%sp + (24 + 64) * 4] ! Y
+// OBSOLETE st %l0, [%sp + (24 + 65) * 4] ! PSR
+// OBSOLETE st %l3, [%sp + (24 + 66) * 4] ! WIM
+// OBSOLETE st %l5, [%sp + (24 + 67) * 4] ! TBR
+// OBSOLETE st %l1, [%sp + (24 + 68) * 4] ! PC
+// OBSOLETE st %l2, [%sp + (24 + 69) * 4] ! NPC
+// OBSOLETE ! CPSR and FPSR not impl
+// OBSOLETE or %l0, 0xf20, %l4
+// OBSOLETE mov %l4, %psr ! Turn on traps, disable interrupts
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! Save coprocessor state.
+// OBSOLETE ! See SK/demo/hdlc_demo/ldc_swap_context.S.
+// OBSOLETE
+// OBSOLETE mov %psr, %l0
+// OBSOLETE sethi %hi(0x2000), %l5 ! EC bit in PSR
+// OBSOLETE or %l5, %l0, %l5
+// OBSOLETE mov %l5, %psr ! enable coprocessor
+// OBSOLETE nop ! 3 nops after write to %psr (needed?)
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE crdcxt %ccsr, %l1 ! capture CCSR
+// OBSOLETE mov 0x6, %l2
+// OBSOLETE cwrcxt %l2, %ccsr ! set CCP state machine for CCFR
+// OBSOLETE crdcxt %ccfr, %l2 ! capture CCOR
+// OBSOLETE cwrcxt %l2, %ccfr ! tickle CCFR
+// OBSOLETE crdcxt %ccfr, %l3 ! capture CCOBR
+// OBSOLETE cwrcxt %l3, %ccfr ! tickle CCFR
+// OBSOLETE crdcxt %ccfr, %l4 ! capture CCIBR
+// OBSOLETE cwrcxt %l4, %ccfr ! tickle CCFR
+// OBSOLETE crdcxt %ccfr, %l5 ! capture CCIR
+// OBSOLETE cwrcxt %l5, %ccfr ! tickle CCFR
+// OBSOLETE crdcxt %ccpr, %l6 ! capture CCPR
+// OBSOLETE crdcxt %cccrcr, %l7 ! capture CCCRCR
+// OBSOLETE st %l1, [%sp + (24 + 72) * 4] ! save CCSR
+// OBSOLETE st %l2, [%sp + (24 + 75) * 4] ! save CCOR
+// OBSOLETE st %l3, [%sp + (24 + 76) * 4] ! save CCOBR
+// OBSOLETE st %l4, [%sp + (24 + 77) * 4] ! save CCIBR
+// OBSOLETE st %l5, [%sp + (24 + 78) * 4] ! save CCIR
+// OBSOLETE st %l6, [%sp + (24 + 73) * 4] ! save CCPR
+// OBSOLETE st %l7, [%sp + (24 + 74) * 4] ! save CCCRCR
+// OBSOLETE mov %l0, %psr ! restore original PSR
+// OBSOLETE nop ! 3 nops after write to %psr (needed?)
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! End of saving coprocessor state.
+// OBSOLETE ! Save asr regs
+// OBSOLETE
+// OBSOLETE ! Part of this is silly -- we should not display ASR15 or ASR19 at all.
+// OBSOLETE
+// OBSOLETE sethi %hi(0x01000000), %l6
+// OBSOLETE st %l6, [%sp + (24 + 81) * 4] ! ASR15 == NOP
+// OBSOLETE sethi %hi(0xdeadc0de), %l6
+// OBSOLETE or %l6, %lo(0xdeadc0de), %l6
+// OBSOLETE st %l6, [%sp + (24 + 84) * 4] ! ASR19 == DEADC0DE
+// OBSOLETE
+// OBSOLETE rd %asr1, %l4
+// OBSOLETE st %l4, [%sp + (24 + 80) * 4]
+// OBSOLETE ! rd %asr15, %l4 ! must not read ASR15
+// OBSOLETE ! st %l4, [%sp + (24 + 81) * 4] ! (illegal instr trap)
+// OBSOLETE rd %asr17, %l4
+// OBSOLETE st %l4, [%sp + (24 + 82) * 4]
+// OBSOLETE rd %asr18, %l4
+// OBSOLETE st %l4, [%sp + (24 + 83) * 4]
+// OBSOLETE ! rd %asr19, %l4 ! must not read asr19
+// OBSOLETE ! st %l4, [%sp + (24 + 84) * 4] ! (halts the CPU)
+// OBSOLETE rd %asr20, %l4
+// OBSOLETE st %l4, [%sp + (24 + 85) * 4]
+// OBSOLETE rd %asr21, %l4
+// OBSOLETE st %l4, [%sp + (24 + 86) * 4]
+// OBSOLETE rd %asr22, %l4
+// OBSOLETE st %l4, [%sp + (24 + 87) * 4]
+// OBSOLETE
+// OBSOLETE ! End of saving asr regs
+// OBSOLETE
+// OBSOLETE call _handle_exception
+// OBSOLETE add %sp, 24 * 4, %o0 ! Pass address of registers
+// OBSOLETE
+// OBSOLETE ! Reload all of the registers that aren't on the stack
+// OBSOLETE
+// OBSOLETE ld [%sp + (24 + 1) * 4], %g1 ! registers[Gx]
+// OBSOLETE ldd [%sp + (24 + 2) * 4], %g2
+// OBSOLETE ldd [%sp + (24 + 4) * 4], %g4
+// OBSOLETE ldd [%sp + (24 + 6) * 4], %g6
+// OBSOLETE
+// OBSOLETE ldd [%sp + (24 + 8) * 4], %i0 ! registers[Ox]
+// OBSOLETE ldd [%sp + (24 + 10) * 4], %i2
+// OBSOLETE ldd [%sp + (24 + 12) * 4], %i4
+// OBSOLETE ldd [%sp + (24 + 14) * 4], %i6
+// OBSOLETE
+// OBSOLETE ! FP regs (sparclet doesn't have fpu)
+// OBSOLETE
+// OBSOLETE ! Update the coprocessor registers.
+// OBSOLETE ! See SK/demo/hdlc_demo/ldc_swap_context.S.
+// OBSOLETE
+// OBSOLETE mov %psr, %l0
+// OBSOLETE sethi %hi(0x2000), %l5 ! EC bit in PSR
+// OBSOLETE or %l5, %l0, %l5
+// OBSOLETE mov %l5, %psr ! enable coprocessor
+// OBSOLETE nop ! 3 nops after write to %psr (needed?)
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE mov 0x6, %l2
+// OBSOLETE cwrcxt %l2, %ccsr ! set CCP state machine for CCFR
+// OBSOLETE
+// OBSOLETE ld [%sp + (24 + 72) * 4], %l1 ! saved CCSR
+// OBSOLETE ld [%sp + (24 + 75) * 4], %l2 ! saved CCOR
+// OBSOLETE ld [%sp + (24 + 76) * 4], %l3 ! saved CCOBR
+// OBSOLETE ld [%sp + (24 + 77) * 4], %l4 ! saved CCIBR
+// OBSOLETE ld [%sp + (24 + 78) * 4], %l5 ! saved CCIR
+// OBSOLETE ld [%sp + (24 + 73) * 4], %l6 ! saved CCPR
+// OBSOLETE ld [%sp + (24 + 74) * 4], %l7 ! saved CCCRCR
+// OBSOLETE
+// OBSOLETE cwrcxt %l2, %ccfr ! restore CCOR
+// OBSOLETE cwrcxt %l3, %ccfr ! restore CCOBR
+// OBSOLETE cwrcxt %l4, %ccfr ! restore CCIBR
+// OBSOLETE cwrcxt %l5, %ccfr ! restore CCIR
+// OBSOLETE cwrcxt %l6, %ccpr ! restore CCPR
+// OBSOLETE cwrcxt %l7, %cccrcr ! restore CCCRCR
+// OBSOLETE cwrcxt %l1, %ccsr ! restore CCSR
+// OBSOLETE
+// OBSOLETE mov %l0, %psr ! restore PSR
+// OBSOLETE nop ! 3 nops after write to %psr (needed?)
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! End of coprocessor handling stuff.
+// OBSOLETE ! Update asr regs
+// OBSOLETE
+// OBSOLETE ld [%sp + (24 + 80) * 4], %l4
+// OBSOLETE wr %l4, %asr1
+// OBSOLETE ! ld [%sp + (24 + 81) * 4], %l4 ! can't write asr15
+// OBSOLETE ! wr %l4, %asr15
+// OBSOLETE ld [%sp + (24 + 82) * 4], %l4
+// OBSOLETE wr %l4, %asr17
+// OBSOLETE ld [%sp + (24 + 83) * 4], %l4
+// OBSOLETE wr %l4, %asr18
+// OBSOLETE ! ld [%sp + (24 + 84) * 4], %l4 ! can't write asr19
+// OBSOLETE ! wr %l4, %asr19
+// OBSOLETE ! ld [%sp + (24 + 85) * 4], %l4 ! can't write asr20
+// OBSOLETE ! wr %l4, %asr20
+// OBSOLETE ! ld [%sp + (24 + 86) * 4], %l4 ! can't write asr21
+// OBSOLETE ! wr %l4, %asr21
+// OBSOLETE ld [%sp + (24 + 87) * 4], %l4
+// OBSOLETE wr %l4, %asr22
+// OBSOLETE
+// OBSOLETE ! End of restoring asr regs
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE ldd [%sp + (24 + 64) * 4], %l0 ! Y & PSR
+// OBSOLETE ldd [%sp + (24 + 68) * 4], %l2 ! PC & NPC
+// OBSOLETE
+// OBSOLETE restore ! Ensure that previous window is valid
+// OBSOLETE save %g0, %g0, %g0 ! by causing a window_underflow trap
+// OBSOLETE
+// OBSOLETE mov %l0, %y
+// OBSOLETE mov %l1, %psr ! Make sure that traps are disabled
+// OBSOLETE ! for rett
+// OBSOLETE nop ! 3 nops after write to %psr (needed?)
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE sethi %hi(in_trap_handler), %l4
+// OBSOLETE ld [%lo(in_trap_handler) + %l4], %l5
+// OBSOLETE dec %l5
+// OBSOLETE st %l5, [%lo(in_trap_handler) + %l4]
+// OBSOLETE
+// OBSOLETE jmpl %l2, %g0 ! Restore old PC
+// OBSOLETE rett %l3 ! Restore old nPC
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE /* Convert ch from a hex digit to an int */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE hex (unsigned char ch)
+// OBSOLETE {
+// OBSOLETE if (ch >= 'a' && ch <= 'f')
+// OBSOLETE return ch-'a'+10;
+// OBSOLETE if (ch >= '0' && ch <= '9')
+// OBSOLETE return ch-'0';
+// OBSOLETE if (ch >= 'A' && ch <= 'F')
+// OBSOLETE return ch-'A'+10;
+// OBSOLETE return -1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static char remcomInBuffer[BUFMAX];
+// OBSOLETE static char remcomOutBuffer[BUFMAX];
+// OBSOLETE
+// OBSOLETE /* scan for the sequence $<data>#<checksum> */
+// OBSOLETE
+// OBSOLETE unsigned char *
+// OBSOLETE getpacket (void)
+// OBSOLETE {
+// OBSOLETE unsigned char *buffer = &remcomInBuffer[0];
+// OBSOLETE unsigned char checksum;
+// OBSOLETE unsigned char xmitcsum;
+// OBSOLETE int count;
+// OBSOLETE char ch;
+// OBSOLETE
+// OBSOLETE while (1)
+// OBSOLETE {
+// OBSOLETE /* wait around for the start character, ignore all other characters */
+// OBSOLETE while ((ch = getDebugChar ()) != '$')
+// OBSOLETE ;
+// OBSOLETE
+// OBSOLETE retry:
+// OBSOLETE checksum = 0;
+// OBSOLETE xmitcsum = -1;
+// OBSOLETE count = 0;
+// OBSOLETE
+// OBSOLETE /* now, read until a # or end of buffer is found */
+// OBSOLETE while (count < BUFMAX)
+// OBSOLETE {
+// OBSOLETE ch = getDebugChar ();
+// OBSOLETE if (ch == '$')
+// OBSOLETE goto retry;
+// OBSOLETE if (ch == '#')
+// OBSOLETE break;
+// OBSOLETE checksum = checksum + ch;
+// OBSOLETE buffer[count] = ch;
+// OBSOLETE count = count + 1;
+// OBSOLETE }
+// OBSOLETE buffer[count] = 0;
+// OBSOLETE
+// OBSOLETE if (ch == '#')
+// OBSOLETE {
+// OBSOLETE ch = getDebugChar ();
+// OBSOLETE xmitcsum = hex (ch) << 4;
+// OBSOLETE ch = getDebugChar ();
+// OBSOLETE xmitcsum += hex (ch);
+// OBSOLETE
+// OBSOLETE if (checksum != xmitcsum)
+// OBSOLETE {
+// OBSOLETE putDebugChar ('-'); /* failed checksum */
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE putDebugChar ('+'); /* successful transfer */
+// OBSOLETE
+// OBSOLETE /* if a sequence char is present, reply the sequence ID */
+// OBSOLETE if (buffer[2] == ':')
+// OBSOLETE {
+// OBSOLETE putDebugChar (buffer[0]);
+// OBSOLETE putDebugChar (buffer[1]);
+// OBSOLETE
+// OBSOLETE return &buffer[3];
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return &buffer[0];
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* send the packet in buffer. */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE putpacket (unsigned char *buffer)
+// OBSOLETE {
+// OBSOLETE unsigned char checksum;
+// OBSOLETE int count;
+// OBSOLETE unsigned char ch;
+// OBSOLETE
+
// OBSOLETE /* $<packet info>#<checksum>. */
+// OBSOLETE do
+// OBSOLETE {
+// OBSOLETE putDebugChar('$');
+// OBSOLETE checksum = 0;
+// OBSOLETE count = 0;
+// OBSOLETE
+// OBSOLETE while (ch = buffer[count])
+// OBSOLETE {
+// OBSOLETE putDebugChar(ch);
+// OBSOLETE checksum += ch;
+// OBSOLETE count += 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE putDebugChar('#');
+// OBSOLETE putDebugChar(hexchars[checksum >> 4]);
+// OBSOLETE putDebugChar(hexchars[checksum & 0xf]);
+// OBSOLETE
+// OBSOLETE }
+// OBSOLETE while (getDebugChar() != '+');
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Indicate to caller of mem2hex or hex2mem that there has been an
+// OBSOLETE error. */
+// OBSOLETE static volatile int mem_err = 0;
+// OBSOLETE
+// OBSOLETE /* Convert the memory pointed to by mem into hex, placing result in buf.
+// OBSOLETE * Return a pointer to the last char put in buf (null), in case of mem fault,
+// OBSOLETE * return 0.
+// OBSOLETE * If MAY_FAULT is non-zero, then we will handle memory faults by returning
+// OBSOLETE * a 0, else treat a fault like any other fault in the stub.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static unsigned char *
+// OBSOLETE mem2hex (unsigned char *mem, unsigned char *buf, int count, int may_fault)
+// OBSOLETE {
+// OBSOLETE unsigned char ch;
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(may_fault);
+// OBSOLETE
+// OBSOLETE while (count-- > 0)
+// OBSOLETE {
+// OBSOLETE ch = *mem++;
+// OBSOLETE if (mem_err)
+// OBSOLETE return 0;
+// OBSOLETE *buf++ = hexchars[ch >> 4];
+// OBSOLETE *buf++ = hexchars[ch & 0xf];
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE *buf = 0;
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(0);
+// OBSOLETE
+// OBSOLETE return buf;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* convert the hex array pointed to by buf into binary to be placed in mem
+// OBSOLETE * return a pointer to the character AFTER the last byte written */
+// OBSOLETE
+// OBSOLETE static char *
+// OBSOLETE hex2mem (unsigned char *buf, unsigned char *mem, int count, int may_fault)
+// OBSOLETE {
+// OBSOLETE int i;
+// OBSOLETE unsigned char ch;
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(may_fault);
+// OBSOLETE
+// OBSOLETE for (i=0; i<count; i++)
+// OBSOLETE {
+// OBSOLETE ch = hex(*buf++) << 4;
+// OBSOLETE ch |= hex(*buf++);
+// OBSOLETE *mem++ = ch;
+// OBSOLETE if (mem_err)
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE set_mem_fault_trap(0);
+// OBSOLETE
+// OBSOLETE return mem;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* This table contains the mapping between SPARC hardware trap types, and
+// OBSOLETE signals, which are primarily what GDB understands. It also indicates
+// OBSOLETE which hardware traps we need to commandeer when initializing the stub. */
+// OBSOLETE
+// OBSOLETE static struct hard_trap_info
+// OBSOLETE {
+// OBSOLETE unsigned char tt; /* Trap type code for SPARClite */
+// OBSOLETE unsigned char signo; /* Signal that we map this trap into */
+// OBSOLETE } hard_trap_info[] = {
+// OBSOLETE {1, SIGSEGV}, /* instruction access exception */
+// OBSOLETE {0x3b, SIGSEGV}, /* instruction access error */
+// OBSOLETE {2, SIGILL}, /* illegal instruction */
+// OBSOLETE {3, SIGILL}, /* privileged instruction */
+// OBSOLETE {4, SIGEMT}, /* fp disabled */
+// OBSOLETE {0x24, SIGEMT}, /* cp disabled */
+// OBSOLETE {7, SIGBUS}, /* mem address not aligned */
+// OBSOLETE {0x29, SIGSEGV}, /* data access exception */
+// OBSOLETE {10, SIGEMT}, /* tag overflow */
+// OBSOLETE {128+1, SIGTRAP}, /* ta 1 - normal breakpoint instruction */
+// OBSOLETE {0, 0} /* Must be last */
+// OBSOLETE };
+// OBSOLETE
+// OBSOLETE /* Set up exception handlers for tracing and breakpoints */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE set_debug_traps (void)
+// OBSOLETE {
+// OBSOLETE struct hard_trap_info *ht;
+// OBSOLETE
+// OBSOLETE for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
+// OBSOLETE exceptionHandler(ht->tt, trap_low);
+// OBSOLETE
+// OBSOLETE initialized = 1;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE asm ("
+// OBSOLETE ! Trap handler for memory errors. This just sets mem_err to be non-zero. It
+// OBSOLETE ! assumes that %l1 is non-zero. This should be safe, as it is doubtful that
+// OBSOLETE ! 0 would ever contain code that could mem fault. This routine will skip
+// OBSOLETE ! past the faulting instruction after setting mem_err.
+// OBSOLETE
+// OBSOLETE .text
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE _fltr_set_mem_err:
+// OBSOLETE sethi %hi(_mem_err), %l0
+// OBSOLETE st %l1, [%l0 + %lo(_mem_err)]
+// OBSOLETE jmpl %l2, %g0
+// OBSOLETE rett %l2+4
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE set_mem_fault_trap (int enable)
+// OBSOLETE {
+// OBSOLETE extern void fltr_set_mem_err();
+// OBSOLETE mem_err = 0;
+// OBSOLETE
+// OBSOLETE if (enable)
+// OBSOLETE exceptionHandler(0x29, fltr_set_mem_err);
+// OBSOLETE else
+// OBSOLETE exceptionHandler(0x29, trap_low);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE asm ("
+// OBSOLETE .text
+// OBSOLETE .align 4
+// OBSOLETE
+// OBSOLETE _dummy_hw_breakpoint:
+// OBSOLETE jmpl %l2, %g0
+// OBSOLETE rett %l2+4
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE set_hw_breakpoint_trap (int enable)
+// OBSOLETE {
+// OBSOLETE extern void dummy_hw_breakpoint();
+// OBSOLETE
+// OBSOLETE if (enable)
+// OBSOLETE exceptionHandler(255, dummy_hw_breakpoint);
+// OBSOLETE else
+// OBSOLETE exceptionHandler(255, trap_low);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE get_in_break_mode (void)
+// OBSOLETE {
+// OBSOLETE #if 0
+// OBSOLETE int x;
+// OBSOLETE mesg("get_in_break_mode, sp = ");
+// OBSOLETE phex(&x);
+// OBSOLETE #endif
+// OBSOLETE set_hw_breakpoint_trap(1);
+// OBSOLETE
+// OBSOLETE asm("
+// OBSOLETE sethi %hi(0xff10), %l4
+// OBSOLETE or %l4, %lo(0xff10), %l4
+// OBSOLETE sta %g0, [%l4]0x1
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE set_hw_breakpoint_trap(0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Convert the SPARC hardware trap type code to a unix signal number. */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE computeSignal (int tt)
+// OBSOLETE {
+// OBSOLETE struct hard_trap_info *ht;
+// OBSOLETE
+// OBSOLETE for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
+// OBSOLETE if (ht->tt == tt)
+// OBSOLETE return ht->signo;
+// OBSOLETE
+// OBSOLETE return SIGHUP; /* default for things we don't know about */
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * While we find nice hex chars, build an int.
+// OBSOLETE * Return number of chars processed.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static int
+// OBSOLETE hexToInt(char **ptr, int *intValue)
+// OBSOLETE {
+// OBSOLETE int numChars = 0;
+// OBSOLETE int hexValue;
+// OBSOLETE
+// OBSOLETE *intValue = 0;
+// OBSOLETE
+// OBSOLETE while (**ptr)
+// OBSOLETE {
+// OBSOLETE hexValue = hex(**ptr);
+// OBSOLETE if (hexValue < 0)
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE *intValue = (*intValue << 4) | hexValue;
+// OBSOLETE numChars ++;
+// OBSOLETE
+// OBSOLETE (*ptr)++;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE return (numChars);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * This function does all command procesing for interfacing to gdb. It
+// OBSOLETE * returns 1 if you should skip the instruction at the trap address, 0
+// OBSOLETE * otherwise.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE handle_exception (unsigned long *registers)
+// OBSOLETE {
+// OBSOLETE int tt; /* Trap type */
+// OBSOLETE int sigval;
+// OBSOLETE int addr;
+// OBSOLETE int length;
+// OBSOLETE char *ptr;
+// OBSOLETE unsigned long *sp;
+// OBSOLETE unsigned long dsr;
+// OBSOLETE
+// OBSOLETE /* First, we must force all of the windows to be spilled out */
+// OBSOLETE
+// OBSOLETE asm("
+// OBSOLETE ! Ugh. sparclet has broken save
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE !save %sp, -64, %sp
+// OBSOLETE save
+// OBSOLETE add %fp,-64,%sp
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE restore
+// OBSOLETE ");
+// OBSOLETE
+// OBSOLETE if (registers[PC] == (unsigned long)breakinst)
+// OBSOLETE {
+// OBSOLETE registers[PC] = registers[NPC];
+// OBSOLETE registers[NPC] += 4;
+// OBSOLETE }
+// OBSOLETE sp = (unsigned long *)registers[SP];
+// OBSOLETE
+// OBSOLETE tt = (registers[TBR] >> 4) & 0xff;
+// OBSOLETE
+// OBSOLETE /* reply to host that an exception has occurred */
+// OBSOLETE sigval = computeSignal(tt);
+// OBSOLETE ptr = remcomOutBuffer;
+// OBSOLETE
+// OBSOLETE *ptr++ = 'T';
+// OBSOLETE *ptr++ = hexchars[sigval >> 4];
+// OBSOLETE *ptr++ = hexchars[sigval & 0xf];
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[PC >> 4];
+// OBSOLETE *ptr++ = hexchars[PC & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)®isters[PC], ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[FP >> 4];
+// OBSOLETE *ptr++ = hexchars[FP & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex(sp + 8 + 6, ptr, 4, 0); /* FP */
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[SP >> 4];
+// OBSOLETE *ptr++ = hexchars[SP & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)&sp, ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[NPC >> 4];
+// OBSOLETE *ptr++ = hexchars[NPC & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)®isters[NPC], ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = hexchars[O7 >> 4];
+// OBSOLETE *ptr++ = hexchars[O7 & 0xf];
+// OBSOLETE *ptr++ = ':';
+// OBSOLETE ptr = mem2hex((char *)®isters[O7], ptr, 4, 0);
+// OBSOLETE *ptr++ = ';';
+// OBSOLETE
+// OBSOLETE *ptr++ = 0;
+// OBSOLETE
+// OBSOLETE putpacket(remcomOutBuffer);
+// OBSOLETE
+// OBSOLETE while (1)
+// OBSOLETE {
+// OBSOLETE remcomOutBuffer[0] = 0;
+// OBSOLETE
+// OBSOLETE ptr = getpacket();
+// OBSOLETE switch (*ptr++)
+// OBSOLETE {
+// OBSOLETE case '?':
+// OBSOLETE remcomOutBuffer[0] = 'S';
+// OBSOLETE remcomOutBuffer[1] = hexchars[sigval >> 4];
+// OBSOLETE remcomOutBuffer[2] = hexchars[sigval & 0xf];
+// OBSOLETE remcomOutBuffer[3] = 0;
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'd':
+// OBSOLETE remote_debug = !(remote_debug); /* toggle debug flag */
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'g': /* return the value of the CPU registers */
+// OBSOLETE {
+// OBSOLETE ptr = remcomOutBuffer;
+// OBSOLETE ptr = mem2hex((char *)registers, ptr, 16 * 4, 0); /* G & O regs */
+// OBSOLETE ptr = mem2hex(sp + 0, ptr, 16 * 4, 0); /* L & I regs */
+// OBSOLETE memset(ptr, '0', 32 * 8); /* Floating point */
+// OBSOLETE ptr = mem2hex((char *)®isters[Y],
+// OBSOLETE ptr + 32 * 4 * 2,
+// OBSOLETE 8 * 4,
+// OBSOLETE 0); /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
+// OBSOLETE ptr = mem2hex((char *)®isters[CCSR],
+// OBSOLETE ptr,
+// OBSOLETE 8 * 4,
+// OBSOLETE 0); /* CCSR, CCPR, CCCRCR, CCOR, CCOBR, CCIBR, CCIR */
+// OBSOLETE ptr = mem2hex((char *)®isters[ASR1],
+// OBSOLETE ptr,
+// OBSOLETE 8 * 4,
+// OBSOLETE 0); /* ASR1,ASR15,ASR17,ASR18,ASR19,ASR20,ASR21,ASR22 */
+// OBSOLETE #if 0 /* not implemented */
+// OBSOLETE ptr = mem2hex((char *) ®isters[AWR0],
+// OBSOLETE ptr,
+// OBSOLETE 32 * 4,
+// OBSOLETE 0); /* Alternate Window Registers */
+// OBSOLETE #endif
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'G': /* set value of all the CPU registers - return OK */
+// OBSOLETE case 'P': /* set value of one CPU register - return OK */
+// OBSOLETE {
+// OBSOLETE unsigned long *newsp, psr;
+// OBSOLETE
+// OBSOLETE psr = registers[PSR];
+// OBSOLETE
+// OBSOLETE if (ptr[-1] == 'P') /* do a single register */
+// OBSOLETE {
+// OBSOLETE int regno;
+// OBSOLETE
+// OBSOLETE if (hexToInt (&ptr, ®no)
+// OBSOLETE && *ptr++ == '=')
+// OBSOLETE if (regno >= L0 && regno <= I7)
+// OBSOLETE hex2mem (ptr, sp + regno - L0, 4, 0);
+// OBSOLETE else
+// OBSOLETE hex2mem (ptr, (char *)®isters[regno], 4, 0);
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE strcpy (remcomOutBuffer, "E01");
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE hex2mem(ptr, (char *)registers, 16 * 4, 0); /* G & O regs */
+// OBSOLETE hex2mem(ptr + 16 * 4 * 2, sp + 0, 16 * 4, 0); /* L & I regs */
+// OBSOLETE hex2mem(ptr + 64 * 4 * 2, (char *)®isters[Y],
+// OBSOLETE 8 * 4, 0); /* Y,PSR,WIM,TBR,PC,NPC,FPSR,CPSR */
+// OBSOLETE hex2mem(ptr + 72 * 4 * 2, (char *)®isters[CCSR],
+// OBSOLETE 8 * 4, 0); /* CCSR,CCPR,CCCRCR,CCOR,CCOBR,CCIBR,CCIR */
+// OBSOLETE hex2mem(ptr + 80 * 4 * 2, (char *)®isters[ASR1],
+// OBSOLETE 8 * 4, 0); /* ASR1 ... ASR22 */
+// OBSOLETE #if 0 /* not implemented */
+// OBSOLETE hex2mem(ptr + 88 * 4 * 2, (char *)®isters[AWR0],
+// OBSOLETE 8 * 4, 0); /* Alternate Window Registers */
+// OBSOLETE #endif
+// OBSOLETE }
+// OBSOLETE /* See if the stack pointer has moved. If so, then copy the saved
+// OBSOLETE locals and ins to the new location. This keeps the window
+// OBSOLETE overflow and underflow routines happy. */
+// OBSOLETE
+// OBSOLETE newsp = (unsigned long *)registers[SP];
+// OBSOLETE if (sp != newsp)
+// OBSOLETE sp = memcpy(newsp, sp, 16 * 4);
+// OBSOLETE
+// OBSOLETE /* Don't allow CWP to be modified. */
+// OBSOLETE
+// OBSOLETE if (psr != registers[PSR])
+// OBSOLETE registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f);
+// OBSOLETE
+// OBSOLETE strcpy(remcomOutBuffer,"OK");
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
+// OBSOLETE /* Try to read %x,%x. */
+// OBSOLETE
+// OBSOLETE if (hexToInt(&ptr, &addr)
+// OBSOLETE && *ptr++ == ','
+// OBSOLETE && hexToInt(&ptr, &length))
+// OBSOLETE {
+// OBSOLETE if (mem2hex((char *)addr, remcomOutBuffer, length, 1))
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE strcpy (remcomOutBuffer, "E03");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE strcpy(remcomOutBuffer,"E01");
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
+// OBSOLETE /* Try to read '%x,%x:'. */
+// OBSOLETE
+// OBSOLETE if (hexToInt(&ptr, &addr)
+// OBSOLETE && *ptr++ == ','
+// OBSOLETE && hexToInt(&ptr, &length)
+// OBSOLETE && *ptr++ == ':')
+// OBSOLETE {
+// OBSOLETE if (hex2mem(ptr, (char *)addr, length, 1))
+// OBSOLETE strcpy(remcomOutBuffer, "OK");
+// OBSOLETE else
+// OBSOLETE strcpy(remcomOutBuffer, "E03");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE strcpy(remcomOutBuffer, "E02");
+// OBSOLETE break;
+// OBSOLETE
+// OBSOLETE case 'c': /* cAA..AA Continue at address AA..AA(optional) */
+// OBSOLETE /* try to read optional parameter, pc unchanged if no parm */
+// OBSOLETE
+// OBSOLETE if (hexToInt(&ptr, &addr))
+// OBSOLETE {
+// OBSOLETE registers[PC] = addr;
+// OBSOLETE registers[NPC] = addr + 4;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Need to flush the instruction cache here, as we may have deposited a
+// OBSOLETE breakpoint, and the icache probably has no way of knowing that a data ref to
+// OBSOLETE some location may have changed something that is in the instruction cache.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE flush_i_cache();
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE /* kill the program */
+// OBSOLETE case 'k' : /* do nothing */
+// OBSOLETE break;
+// OBSOLETE #if 0
+// OBSOLETE case 't': /* Test feature */
+// OBSOLETE asm (" std %f30,[%sp]");
+// OBSOLETE break;
+// OBSOLETE #endif
+// OBSOLETE case 'r': /* Reset */
+// OBSOLETE asm ("call 0
+// OBSOLETE nop ");
+// OBSOLETE break;
+// OBSOLETE } /* switch */
+// OBSOLETE
+// OBSOLETE /* reply to the request */
+// OBSOLETE putpacket(remcomOutBuffer);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* This function will generate a breakpoint exception. It is used at the
+// OBSOLETE beginning of a program to sync up with a debugger and can be used
+// OBSOLETE otherwise as a quick means to stop program execution and "break" into
+// OBSOLETE the debugger. */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE breakpoint (void)
+// OBSOLETE {
+// OBSOLETE if (!initialized)
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE asm(" .globl _breakinst
+// OBSOLETE
+// OBSOLETE _breakinst: ta 1
+// OBSOLETE ");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE static void
+// OBSOLETE hw_breakpoint (void)
+// OBSOLETE {
+// OBSOLETE asm("
+// OBSOLETE ta 127
+// OBSOLETE ");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #if 0 /* experimental and never finished, left here for reference */
+// OBSOLETE static void
+// OBSOLETE splet_temp(void)
+// OBSOLETE {
+// OBSOLETE asm(" sub %sp,(16+1+6+1+121)*4,%sp ! Make room for input & locals
+// OBSOLETE ! + hidden arg + arg spill
+// OBSOLETE ! + doubleword alignment
+// OBSOLETE ! + registers[121]
+// OBSOLETE
+// OBSOLETE ! Leave a trail of breadcrumbs! (save register save area for debugging)
+// OBSOLETE mov %sp, %l0
+// OBSOLETE add %l0, 24*4, %l0
+// OBSOLETE sethi %hi(_debug_registers), %l1
+// OBSOLETE st %l0, [%lo(_debug_registers) + %l1]
+// OBSOLETE
+// OBSOLETE ! Save the Alternate Register Set: (not implemented yet)
+// OBSOLETE ! To save the Alternate Register set, we must:
+// OBSOLETE ! 1) Save the current SP in some global location.
+// OBSOLETE ! 2) Swap the register sets.
+// OBSOLETE ! 3) Save the Alternate SP in the Y register
+// OBSOLETE ! 4) Fetch the SP that we saved in step 1.
+// OBSOLETE ! 5) Use that to save the rest of the regs (not forgetting ASP in Y)
+// OBSOLETE ! 6) Restore the Alternate SP from Y
+// OBSOLETE ! 7) Swap the registers back.
+// OBSOLETE
+// OBSOLETE ! 1) Copy the current stack pointer to global _SAVED_STACK_POINTER:
+// OBSOLETE sethi %hi(_saved_stack_pointer), %l0
+// OBSOLETE st %sp, [%lo(_saved_stack_pointer) + %l0]
+// OBSOLETE
+// OBSOLETE ! 2) Swap the register sets:
+// OBSOLETE mov %psr, %l1
+// OBSOLETE sethi %hi(0x10000), %l2
+// OBSOLETE xor %l1, %l2, %l1
+// OBSOLETE mov %l1, %psr
+// OBSOLETE nop ! 3 nops after write to %psr (needed?)
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE
+// OBSOLETE ! 3) Save Alternate L0 in Y
+// OBSOLETE wr %l0, 0, %y
+// OBSOLETE
+// OBSOLETE ! 4) Load former SP into alternate SP, using L0
+// OBSOLETE sethi %hi(_saved_stack_pointer), %l0
+// OBSOLETE or %lo(_saved_stack_pointer), %l0, %l0
+// OBSOLETE swap [%l0], %sp
+// OBSOLETE
+// OBSOLETE ! 4.5) Restore alternate L0
+// OBSOLETE rd %y, %l0
+// OBSOLETE
+// OBSOLETE ! 5) Save the Alternate Window Registers
+// OBSOLETE st %r0, [%sp + (24 + 88) * 4] ! AWR0
+// OBSOLETE st %r1, [%sp + (24 + 89) * 4] ! AWR1
+// OBSOLETE st %r2, [%sp + (24 + 90) * 4] ! AWR2
+// OBSOLETE st %r3, [%sp + (24 + 91) * 4] ! AWR3
+// OBSOLETE st %r4, [%sp + (24 + 92) * 4] ! AWR4
+// OBSOLETE st %r5, [%sp + (24 + 93) * 4] ! AWR5
+// OBSOLETE st %r6, [%sp + (24 + 94) * 4] ! AWR6
+// OBSOLETE st %r7, [%sp + (24 + 95) * 4] ! AWR7
+// OBSOLETE st %r8, [%sp + (24 + 96) * 4] ! AWR8
+// OBSOLETE st %r9, [%sp + (24 + 97) * 4] ! AWR9
+// OBSOLETE st %r10, [%sp + (24 + 98) * 4] ! AWR10
+// OBSOLETE st %r11, [%sp + (24 + 99) * 4] ! AWR11
+// OBSOLETE st %r12, [%sp + (24 + 100) * 4] ! AWR12
+// OBSOLETE st %r13, [%sp + (24 + 101) * 4] ! AWR13
+// OBSOLETE ! st %r14, [%sp + (24 + 102) * 4] ! AWR14 (SP)
+// OBSOLETE st %r15, [%sp + (24 + 103) * 4] ! AWR15
+// OBSOLETE st %r16, [%sp + (24 + 104) * 4] ! AWR16
+// OBSOLETE st %r17, [%sp + (24 + 105) * 4] ! AWR17
+// OBSOLETE st %r18, [%sp + (24 + 106) * 4] ! AWR18
+// OBSOLETE st %r19, [%sp + (24 + 107) * 4] ! AWR19
+// OBSOLETE st %r20, [%sp + (24 + 108) * 4] ! AWR20
+// OBSOLETE st %r21, [%sp + (24 + 109) * 4] ! AWR21
+// OBSOLETE st %r22, [%sp + (24 + 110) * 4] ! AWR22
+// OBSOLETE st %r23, [%sp + (24 + 111) * 4] ! AWR23
+// OBSOLETE st %r24, [%sp + (24 + 112) * 4] ! AWR24
+// OBSOLETE st %r25, [%sp + (24 + 113) * 4] ! AWR25
+// OBSOLETE st %r26, [%sp + (24 + 114) * 4] ! AWR26
+// OBSOLETE st %r27, [%sp + (24 + 115) * 4] ! AWR27
+// OBSOLETE st %r28, [%sp + (24 + 116) * 4] ! AWR28
+// OBSOLETE st %r29, [%sp + (24 + 117) * 4] ! AWR29
+// OBSOLETE st %r30, [%sp + (24 + 118) * 4] ! AWR30
+// OBSOLETE st %r31, [%sp + (24 + 119) * 4] ! AWR21
+// OBSOLETE
+// OBSOLETE ! Get the Alternate PSR (I hope...)
+// OBSOLETE
+// OBSOLETE rd %psr, %l2
+// OBSOLETE st %l2, [%sp + (24 + 120) * 4] ! APSR
+// OBSOLETE
+// OBSOLETE ! Don't forget the alternate stack pointer
+// OBSOLETE
+// OBSOLETE rd %y, %l3
+// OBSOLETE st %l3, [%sp + (24 + 102) * 4] ! AWR14 (SP)
+// OBSOLETE
+// OBSOLETE ! 6) Restore the Alternate SP (saved in Y)
+// OBSOLETE
+// OBSOLETE rd %y, %o6
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE ! 7) Swap the registers back:
+// OBSOLETE
+// OBSOLETE mov %psr, %l1
+// OBSOLETE sethi %hi(0x10000), %l2
+// OBSOLETE xor %l1, %l2, %l1
+// OBSOLETE mov %l1, %psr
+// OBSOLETE nop ! 3 nops after write to %psr (needed?)
+// OBSOLETE nop
+// OBSOLETE nop
+// OBSOLETE ");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #endif
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct serial;
+
void load_srec (struct serial *desc, const char *file, bfd_vma load_offset,
int maxrecsize, int flags, int hashmark,
int (*waitack) (void));
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct objfile;
+
/* Definitions, prototypes, etc for stabs debugging format support
functions.
/* This file requires that you first include "bfd.h". */
/* Opaque declarations. */
-
+struct objfile;
struct obstack;
struct block;
-/* Sequent Symmetry host interface, for GDB when running under Unix.
-
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1999,
- 2000, 2001, 2003 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* FIXME, some 387-specific items of use taken from i387-tdep.c -- ought to be
- merged back in. */
-
-#include "defs.h"
-#include "frame.h"
-#include "inferior.h"
-#include "symtab.h"
-#include "target.h"
-#include "regcache.h"
-
-/* FIXME: What is the _INKERNEL define for? */
-#define _INKERNEL
-#include <signal.h>
-#undef _INKERNEL
-#include "gdb_wait.h"
-#include <sys/param.h>
-#include <sys/user.h>
-#include <sys/proc.h>
-#include <sys/dir.h>
-#include <sys/ioctl.h>
-#include "gdb_stat.h"
-#ifdef _SEQUENT_
-#include <sys/ptrace.h>
-#else
-/* Dynix has only machine/ptrace.h, which is already included by sys/user.h */
-/* Dynix has no mptrace call */
-#define mptrace ptrace
-#endif
-#include "gdbcore.h"
-#include <fcntl.h>
-#include <sgtty.h>
-#define TERMINAL struct sgttyb
-
-#include "gdbcore.h"
-
-void
-store_inferior_registers (int regno)
-{
- struct pt_regset regs;
- int i;
-
- /* FIXME: Fetching the registers is a kludge to initialize all elements
- in the fpu and fpa status. This works for normal debugging, but
- might cause problems when calling functions in the inferior.
- At least fpu_control and fpa_pcr (probably more) should be added
- to the registers array to solve this properly. */
- mptrace (XPT_RREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regs, 0);
-
- regs.pr_eax = *(int *) &deprecated_registers[REGISTER_BYTE (0)];
- regs.pr_ebx = *(int *) &deprecated_registers[REGISTER_BYTE (5)];
- regs.pr_ecx = *(int *) &deprecated_registers[REGISTER_BYTE (2)];
- regs.pr_edx = *(int *) &deprecated_registers[REGISTER_BYTE (1)];
- regs.pr_esi = *(int *) &deprecated_registers[REGISTER_BYTE (6)];
- regs.pr_edi = *(int *) &deprecated_registers[REGISTER_BYTE (7)];
- regs.pr_esp = *(int *) &deprecated_registers[REGISTER_BYTE (14)];
- regs.pr_ebp = *(int *) &deprecated_registers[REGISTER_BYTE (15)];
- regs.pr_eip = *(int *) &deprecated_registers[REGISTER_BYTE (16)];
- regs.pr_flags = *(int *) &deprecated_registers[REGISTER_BYTE (17)];
- for (i = 0; i < 31; i++)
- {
- regs.pr_fpa.fpa_regs[i] =
- *(int *) &deprecated_registers[REGISTER_BYTE (FP1_REGNUM + i)];
- }
- memcpy (regs.pr_fpu.fpu_stack[0], &deprecated_registers[REGISTER_BYTE (ST0_REGNUM)], 10);
- memcpy (regs.pr_fpu.fpu_stack[1], &deprecated_registers[REGISTER_BYTE (ST1_REGNUM)], 10);
- memcpy (regs.pr_fpu.fpu_stack[2], &deprecated_registers[REGISTER_BYTE (ST2_REGNUM)], 10);
- memcpy (regs.pr_fpu.fpu_stack[3], &deprecated_registers[REGISTER_BYTE (ST3_REGNUM)], 10);
- memcpy (regs.pr_fpu.fpu_stack[4], &deprecated_registers[REGISTER_BYTE (ST4_REGNUM)], 10);
- memcpy (regs.pr_fpu.fpu_stack[5], &deprecated_registers[REGISTER_BYTE (ST5_REGNUM)], 10);
- memcpy (regs.pr_fpu.fpu_stack[6], &deprecated_registers[REGISTER_BYTE (ST6_REGNUM)], 10);
- memcpy (regs.pr_fpu.fpu_stack[7], &deprecated_registers[REGISTER_BYTE (ST7_REGNUM)], 10);
- mptrace (XPT_WREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regs, 0);
-}
-
-void
-fetch_inferior_registers (int regno)
-{
- int i;
- struct pt_regset regs;
-
- deprecated_registers_fetched ();
-
- mptrace (XPT_RREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regs, 0);
- *(int *) &deprecated_registers[REGISTER_BYTE (EAX_REGNUM)] = regs.pr_eax;
- *(int *) &rdeprecated_egisters[REGISTER_BYTE (EBX_REGNUM)] = regs.pr_ebx;
- *(int *) &deprecated_registers[REGISTER_BYTE (ECX_REGNUM)] = regs.pr_ecx;
- *(int *) &deprecated_registers[REGISTER_BYTE (EDX_REGNUM)] = regs.pr_edx;
- *(int *) &deprecated_registers[REGISTER_BYTE (ESI_REGNUM)] = regs.pr_esi;
- *(int *) &deprecated_registers[REGISTER_BYTE (EDI_REGNUM)] = regs.pr_edi;
- *(int *) &deprecated_registers[REGISTER_BYTE (EBP_REGNUM)] = regs.pr_ebp;
- *(int *) &deprecated_registers[REGISTER_BYTE (ESP_REGNUM)] = regs.pr_esp;
- *(int *) &deprecated_registers[REGISTER_BYTE (EIP_REGNUM)] = regs.pr_eip;
- *(int *) &deprecated_registers[REGISTER_BYTE (EFLAGS_REGNUM)] = regs.pr_flags;
- for (i = 0; i < FPA_NREGS; i++)
- {
- *(int *) &deprecated_registers[REGISTER_BYTE (FP1_REGNUM + i)] =
- regs.pr_fpa.fpa_regs[i];
- }
- memcpy (&deprecated_registers[REGISTER_BYTE (ST0_REGNUM)], regs.pr_fpu.fpu_stack[0], 10);
- memcpy (&deprecated_registers[REGISTER_BYTE (ST1_REGNUM)], regs.pr_fpu.fpu_stack[1], 10);
- memcpy (&deprecated_registers[REGISTER_BYTE (ST2_REGNUM)], regs.pr_fpu.fpu_stack[2], 10);
- memcpy (&deprecated_registers[REGISTER_BYTE (ST3_REGNUM)], regs.pr_fpu.fpu_stack[3], 10);
- memcpy (&deprecated_registers[REGISTER_BYTE (ST4_REGNUM)], regs.pr_fpu.fpu_stack[4], 10);
- memcpy (&deprecated_registers[REGISTER_BYTE (ST5_REGNUM)], regs.pr_fpu.fpu_stack[5], 10);
- memcpy (&deprecated_registers[REGISTER_BYTE (ST6_REGNUM)], regs.pr_fpu.fpu_stack[6], 10);
- memcpy (&deprecated_registers[REGISTER_BYTE (ST7_REGNUM)], regs.pr_fpu.fpu_stack[7], 10);
-}
-\f
-/* FIXME: This should be merged with i387-tdep.c as well. */
-static
-print_fpu_status (struct pt_regset ep)
-{
- int i;
- int bothstatus;
- int top;
- int fpreg;
- unsigned char *p;
-
- printf_unfiltered ("80387:");
- if (ep.pr_fpu.fpu_ip == 0)
- {
- printf_unfiltered (" not in use.\n");
- return;
- }
- else
- {
- printf_unfiltered ("\n");
- }
- if (ep.pr_fpu.fpu_status != 0)
- {
- print_387_status_word (ep.pr_fpu.fpu_status);
- }
- print_387_control_word (ep.pr_fpu.fpu_control);
- printf_unfiltered ("last exception: ");
- printf_unfiltered ("opcode 0x%x; ", ep.pr_fpu.fpu_rsvd4);
- printf_unfiltered ("pc 0x%x:0x%x; ", ep.pr_fpu.fpu_cs, ep.pr_fpu.fpu_ip);
- printf_unfiltered ("operand 0x%x:0x%x\n", ep.pr_fpu.fpu_data_offset, ep.pr_fpu.fpu_op_sel);
-
- top = (ep.pr_fpu.fpu_status >> 11) & 7;
-
- printf_unfiltered ("regno tag msb lsb value\n");
- for (fpreg = 7; fpreg >= 0; fpreg--)
- {
- double val;
-
- printf_unfiltered ("%s %d: ", fpreg == top ? "=>" : " ", fpreg);
-
- switch ((ep.pr_fpu.fpu_tag >> (fpreg * 2)) & 3)
- {
- case 0:
- printf_unfiltered ("valid ");
- break;
- case 1:
- printf_unfiltered ("zero ");
- break;
- case 2:
- printf_unfiltered ("trap ");
- break;
- case 3:
- printf_unfiltered ("empty ");
- break;
- }
- for (i = 9; i >= 0; i--)
- printf_unfiltered ("%02x", ep.pr_fpu.fpu_stack[fpreg][i]);
-
- i387_to_double ((char *) ep.pr_fpu.fpu_stack[fpreg], (char *) &val);
- printf_unfiltered (" %g\n", val);
- }
- if (ep.pr_fpu.fpu_rsvd1)
- warning ("rsvd1 is 0x%x\n", ep.pr_fpu.fpu_rsvd1);
- if (ep.pr_fpu.fpu_rsvd2)
- warning ("rsvd2 is 0x%x\n", ep.pr_fpu.fpu_rsvd2);
- if (ep.pr_fpu.fpu_rsvd3)
- warning ("rsvd3 is 0x%x\n", ep.pr_fpu.fpu_rsvd3);
- if (ep.pr_fpu.fpu_rsvd5)
- warning ("rsvd5 is 0x%x\n", ep.pr_fpu.fpu_rsvd5);
-}
-
-
-print_1167_control_word (unsigned int pcr)
-{
- int pcr_tmp;
-
- pcr_tmp = pcr & FPA_PCR_MODE;
- printf_unfiltered ("\tMODE= %#x; RND= %#x ", pcr_tmp, pcr_tmp & 12);
- switch (pcr_tmp & 12)
- {
- case 0:
- printf_unfiltered ("RN (Nearest Value)");
- break;
- case 1:
- printf_unfiltered ("RZ (Zero)");
- break;
- case 2:
- printf_unfiltered ("RP (Positive Infinity)");
- break;
- case 3:
- printf_unfiltered ("RM (Negative Infinity)");
- break;
- }
- printf_unfiltered ("; IRND= %d ", pcr_tmp & 2);
- if (0 == pcr_tmp & 2)
- {
- printf_unfiltered ("(same as RND)\n");
- }
- else
- {
- printf_unfiltered ("(toward zero)\n");
- }
- pcr_tmp = pcr & FPA_PCR_EM;
- printf_unfiltered ("\tEM= %#x", pcr_tmp);
- if (pcr_tmp & FPA_PCR_EM_DM)
- printf_unfiltered (" DM");
- if (pcr_tmp & FPA_PCR_EM_UOM)
- printf_unfiltered (" UOM");
- if (pcr_tmp & FPA_PCR_EM_PM)
- printf_unfiltered (" PM");
- if (pcr_tmp & FPA_PCR_EM_UM)
- printf_unfiltered (" UM");
- if (pcr_tmp & FPA_PCR_EM_OM)
- printf_unfiltered (" OM");
- if (pcr_tmp & FPA_PCR_EM_ZM)
- printf_unfiltered (" ZM");
- if (pcr_tmp & FPA_PCR_EM_IM)
- printf_unfiltered (" IM");
- printf_unfiltered ("\n");
- pcr_tmp = FPA_PCR_CC;
- printf_unfiltered ("\tCC= %#x", pcr_tmp);
- if (pcr_tmp & FPA_PCR_20MHZ)
- printf_unfiltered (" 20MHZ");
- if (pcr_tmp & FPA_PCR_CC_Z)
- printf_unfiltered (" Z");
- if (pcr_tmp & FPA_PCR_CC_C2)
- printf_unfiltered (" C2");
-
- /* Dynix defines FPA_PCR_CC_C0 to 0x100 and ptx defines
- FPA_PCR_CC_C1 to 0x100. Use whichever is defined and assume
- the OS knows what it is doing. */
-#ifdef FPA_PCR_CC_C1
- if (pcr_tmp & FPA_PCR_CC_C1)
- printf_unfiltered (" C1");
-#else
- if (pcr_tmp & FPA_PCR_CC_C0)
- printf_unfiltered (" C0");
-#endif
-
- switch (pcr_tmp)
- {
- case FPA_PCR_CC_Z:
- printf_unfiltered (" (Equal)");
- break;
-#ifdef FPA_PCR_CC_C1
- case FPA_PCR_CC_C1:
-#else
- case FPA_PCR_CC_C0:
-#endif
- printf_unfiltered (" (Less than)");
- break;
- case 0:
- printf_unfiltered (" (Greater than)");
- break;
- case FPA_PCR_CC_Z |
-#ifdef FPA_PCR_CC_C1
- FPA_PCR_CC_C1
-#else
- FPA_PCR_CC_C0
-#endif
- | FPA_PCR_CC_C2:
- printf_unfiltered (" (Unordered)");
- break;
- default:
- printf_unfiltered (" (Undefined)");
- break;
- }
- printf_unfiltered ("\n");
- pcr_tmp = pcr & FPA_PCR_AE;
- printf_unfiltered ("\tAE= %#x", pcr_tmp);
- if (pcr_tmp & FPA_PCR_AE_DE)
- printf_unfiltered (" DE");
- if (pcr_tmp & FPA_PCR_AE_UOE)
- printf_unfiltered (" UOE");
- if (pcr_tmp & FPA_PCR_AE_PE)
- printf_unfiltered (" PE");
- if (pcr_tmp & FPA_PCR_AE_UE)
- printf_unfiltered (" UE");
- if (pcr_tmp & FPA_PCR_AE_OE)
- printf_unfiltered (" OE");
- if (pcr_tmp & FPA_PCR_AE_ZE)
- printf_unfiltered (" ZE");
- if (pcr_tmp & FPA_PCR_AE_EE)
- printf_unfiltered (" EE");
- if (pcr_tmp & FPA_PCR_AE_IE)
- printf_unfiltered (" IE");
- printf_unfiltered ("\n");
-}
-
-print_1167_regs (long regs[FPA_NREGS])
-{
- int i;
-
- union
- {
- double d;
- long l[2];
- }
- xd;
- union
- {
- float f;
- long l;
- }
- xf;
-
-
- for (i = 0; i < FPA_NREGS; i++)
- {
- xf.l = regs[i];
- printf_unfiltered ("%%fp%d: raw= %#x, single= %f", i + 1, regs[i], xf.f);
- if (!(i & 1))
- {
- printf_unfiltered ("\n");
- }
- else
- {
- xd.l[1] = regs[i];
- xd.l[0] = regs[i + 1];
- printf_unfiltered (", double= %f\n", xd.d);
- }
- }
-}
-
-print_fpa_status (struct pt_regset ep)
-{
-
- printf_unfiltered ("WTL 1167:");
- if (ep.pr_fpa.fpa_pcr != 0)
- {
- printf_unfiltered ("\n");
- print_1167_control_word (ep.pr_fpa.fpa_pcr);
- print_1167_regs (ep.pr_fpa.fpa_regs);
- }
- else
- {
- printf_unfiltered (" not in use.\n");
- }
-}
-
-#if 0 /* disabled because it doesn't go through the target vector. */
-i386_float_info (void)
-{
- char ubuf[UPAGES * NBPG];
- struct pt_regset regset;
-
- if (have_inferior_p ())
- {
- PTRACE_READ_REGS (PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regset);
- }
- else
- {
- int corechan = bfd_cache_lookup (core_bfd);
- if (lseek (corechan, 0, 0) < 0)
- {
- perror ("seek on core file");
- }
- if (myread (corechan, ubuf, UPAGES * NBPG) < 0)
- {
- perror ("read on core file");
- }
- /* only interested in the floating point registers */
- regset.pr_fpu = ((struct user *) ubuf)->u_fpusave;
- regset.pr_fpa = ((struct user *) ubuf)->u_fpasave;
- }
- print_fpu_status (regset);
- print_fpa_status (regset);
-}
-#endif
-
-static volatile int got_sigchld;
-
-/*ARGSUSED */
-/* This will eventually be more interesting. */
-void
-sigchld_handler (int signo)
-{
- got_sigchld++;
-}
-
-/*
- * Signals for which the default action does not cause the process
- * to die. See <sys/signal.h> for where this came from (alas, we
- * can't use those macros directly)
- */
-#ifndef sigmask
-#define sigmask(s) (1 << ((s) - 1))
-#endif
-#define SIGNALS_DFL_SAFE sigmask(SIGSTOP) | sigmask(SIGTSTP) | \
- sigmask(SIGTTIN) | sigmask(SIGTTOU) | sigmask(SIGCHLD) | \
- sigmask(SIGCONT) | sigmask(SIGWINCH) | sigmask(SIGPWR) | \
- sigmask(SIGURG) | sigmask(SIGPOLL)
-
-#ifdef ATTACH_DETACH
-/*
- * Thanks to XPT_MPDEBUGGER, we have to mange child_wait().
- */
-ptid_t
-child_wait (ptid_t ptid, struct target_waitstatus *status)
-{
- int save_errno, rv, xvaloff, saoff, sa_hand;
- struct pt_stop pt;
- struct user u;
- sigset_t set;
- /* Host signal number for a signal which the inferior terminates with, or
- 0 if it hasn't terminated due to a signal. */
- static int death_by_signal = 0;
-#ifdef SVR4_SHARED_LIBS /* use this to distinguish ptx 2 vs ptx 4 */
- prstatus_t pstatus;
-#endif
- int pid = PIDGET (ptid);
-
- do
- {
- set_sigint_trap (); /* Causes SIGINT to be passed on to the
- attached process. */
- save_errno = errno;
-
- got_sigchld = 0;
-
- sigemptyset (&set);
-
- while (got_sigchld == 0)
- {
- sigsuspend (&set);
- }
-
- clear_sigint_trap ();
-
- rv = mptrace (XPT_STOPSTAT, 0, (char *) &pt, 0);
- if (-1 == rv)
- {
- printf ("XPT_STOPSTAT: errno %d\n", errno); /* DEBUG */
- continue;
- }
-
- pid = pt.ps_pid;
-
- if (pid != PIDGET (inferior_ptid))
- {
- /* NOTE: the mystery fork in csh/tcsh needs to be ignored.
- * We should not return new children for the initial run
- * of a process until it has done the exec.
- */
- /* inferior probably forked; send it on its way */
- rv = mptrace (XPT_UNDEBUG, pid, 0, 0);
- if (-1 == rv)
- {
- printf ("child_wait: XPT_UNDEBUG: pid %d: %s\n", pid,
- safe_strerror (errno));
- }
- continue;
- }
- /* FIXME: Do we deal with fork notification correctly? */
- switch (pt.ps_reason)
- {
- case PTS_FORK:
- /* multi proc: treat like PTS_EXEC */
- /*
- * Pretend this didn't happen, since gdb isn't set up
- * to deal with stops on fork.
- */
- rv = ptrace (PT_CONTSIG, pid, 1, 0);
- if (-1 == rv)
- {
- printf ("PTS_FORK: PT_CONTSIG: error %d\n", errno);
- }
- continue;
- case PTS_EXEC:
- /*
- * Pretend this is a SIGTRAP.
- */
- status->kind = TARGET_WAITKIND_STOPPED;
- status->value.sig = TARGET_SIGNAL_TRAP;
- break;
- case PTS_EXIT:
- /*
- * Note: we stop before the exit actually occurs. Extract
- * the exit code from the uarea. If we're stopped in the
- * exit() system call, the exit code will be in
- * u.u_ap[0]. An exit due to an uncaught signal will have
- * something else in here, see the comment in the default:
- * case, below. Finally,let the process exit.
- */
- if (death_by_signal)
- {
- status->kind = TARGET_WAITKIND_SIGNALED;
- status->value.sig = target_signal_from_host (death_by_signal);
- death_by_signal = 0;
- break;
- }
- xvaloff = (unsigned long) &u.u_ap[0] - (unsigned long) &u;
- errno = 0;
- rv = ptrace (PT_RUSER, pid, (char *) xvaloff, 0);
- status->kind = TARGET_WAITKIND_EXITED;
- status->value.integer = rv;
- /*
- * addr & data to mptrace() don't matter here, since
- * the process is already dead.
- */
- rv = mptrace (XPT_UNDEBUG, pid, 0, 0);
- if (-1 == rv)
- {
- printf ("child_wait: PTS_EXIT: XPT_UNDEBUG: pid %d error %d\n", pid,
- errno);
- }
- break;
- case PTS_WATCHPT_HIT:
- internal_error (__FILE__, __LINE__,
- "PTS_WATCHPT_HIT\n");
- break;
- default:
- /* stopped by signal */
- status->kind = TARGET_WAITKIND_STOPPED;
- status->value.sig = target_signal_from_host (pt.ps_reason);
- death_by_signal = 0;
-
- if (0 == (SIGNALS_DFL_SAFE & sigmask (pt.ps_reason)))
- {
- break;
- }
- /* else default action of signal is to die */
-#ifdef SVR4_SHARED_LIBS
- rv = ptrace (PT_GET_PRSTATUS, pid, (char *) &pstatus, 0);
- if (-1 == rv)
- error ("child_wait: signal %d PT_GET_PRSTATUS: %s\n",
- pt.ps_reason, safe_strerror (errno));
- if (pstatus.pr_cursig != pt.ps_reason)
- {
- printf ("pstatus signal %d, pt signal %d\n",
- pstatus.pr_cursig, pt.ps_reason);
- }
- sa_hand = (int) pstatus.pr_action.sa_handler;
-#else
- saoff = (unsigned long) &u.u_sa[0] - (unsigned long) &u;
- saoff += sizeof (struct sigaction) * (pt.ps_reason - 1);
- errno = 0;
- sa_hand = ptrace (PT_RUSER, pid, (char *) saoff, 0);
- if (errno)
- error ("child_wait: signal %d: RUSER: %s\n",
- pt.ps_reason, safe_strerror (errno));
-#endif
- if ((int) SIG_DFL == sa_hand)
- {
- /* we will be dying */
- death_by_signal = pt.ps_reason;
- }
- break;
- }
-
- }
- while (pid != PIDGET (inferior_ptid)); /* Some other child died or stopped */
-
- return pid_to_ptid (pid);
-}
-#else /* !ATTACH_DETACH */
-/*
- * Simple child_wait() based on inftarg.c child_wait() for use until
- * the MPDEBUGGER child_wait() works properly. This will go away when
- * that is fixed.
- */
-ptid_t
-child_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
-{
- int save_errno;
- int status;
- int pid = PIDGET (ptid);
-
- do
- {
- pid = wait (&status);
- save_errno = errno;
-
- if (pid == -1)
- {
- if (save_errno == EINTR)
- continue;
- fprintf (stderr, "Child process unexpectedly missing: %s.\n",
- safe_strerror (save_errno));
- ourstatus->kind = TARGET_WAITKIND_SIGNALLED;
- ourstatus->value.sig = TARGET_SIGNAL_UNKNOWN;
- return pid_to_ptid (-1);
- }
- }
- while (pid != PIDGET (inferior_ptid)); /* Some other child died or stopped */
- store_waitstatus (ourstatus, status);
- return pid_to_ptid (pid);
-}
-#endif /* ATTACH_DETACH */
-\f
-
-
-/* This function simply calls ptrace with the given arguments.
- It exists so that all calls to ptrace are isolated in this
- machine-dependent file. */
-int
-call_ptrace (int request, int pid, PTRACE_ARG3_TYPE addr, int data)
-{
- return ptrace (request, pid, addr, data);
-}
-
-int
-call_mptrace (int request, int pid, PTRACE_ARG3_TYPE addr, int data)
-{
- return mptrace (request, pid, addr, data);
-}
-
-#if defined (DEBUG_PTRACE)
-/* For the rest of the file, use an extra level of indirection */
-/* This lets us breakpoint usefully on call_ptrace. */
-#define ptrace call_ptrace
-#define mptrace call_mptrace
-#endif
-
-void
-kill_inferior (void)
-{
- if (ptid_equal (inferior_ptid, null_ptid))
- return;
-
- /* For MPDEBUGGER, don't use PT_KILL, since the child will stop
- again with a PTS_EXIT. Just hit him with SIGKILL (so he stops)
- and detach. */
-
- kill (PIDGET (inferior_ptid), SIGKILL);
-#ifdef ATTACH_DETACH
- detach (SIGKILL);
-#else /* ATTACH_DETACH */
- ptrace (PT_KILL, PIDGET (inferior_ptid), 0, 0);
- wait ((int *) NULL);
-#endif /* ATTACH_DETACH */
- target_mourn_inferior ();
-}
-
-/* Resume execution of the inferior process.
- If STEP is nonzero, single-step it.
- If SIGNAL is nonzero, give it that signal. */
-
-void
-child_resume (ptid_t ptid, int step, enum target_signal signal)
-{
- int pid = PIDGET (ptid);
-
- errno = 0;
-
- if (pid == -1)
- pid = PIDGET (inferior_ptid);
-
- /* An address of (PTRACE_ARG3_TYPE)1 tells ptrace to continue from where
- it was. (If GDB wanted it to start some other way, we have already
- written a new PC value to the child.)
-
- If this system does not support PT_SSTEP, a higher level function will
- have called single_step() to transmute the step request into a
- continue request (by setting breakpoints on all possible successor
- instructions), so we don't have to worry about that here. */
-
- if (step)
- ptrace (PT_SSTEP, pid, (PTRACE_ARG3_TYPE) 1, signal);
- else
- ptrace (PT_CONTSIG, pid, (PTRACE_ARG3_TYPE) 1, signal);
-
- if (errno)
- perror_with_name ("ptrace");
-}
-\f
-#ifdef ATTACH_DETACH
-/* Start debugging the process whose number is PID. */
-int
-attach (int pid)
-{
- sigset_t set;
- int rv;
-
- rv = mptrace (XPT_DEBUG, pid, 0, 0);
- if (-1 == rv)
- {
- error ("mptrace(XPT_DEBUG): %s", safe_strerror (errno));
- }
- rv = mptrace (XPT_SIGNAL, pid, 0, SIGSTOP);
- if (-1 == rv)
- {
- error ("mptrace(XPT_SIGNAL): %s", safe_strerror (errno));
- }
- attach_flag = 1;
- return pid;
-}
-
-void
-detach (int signo)
-{
- int rv;
-
- rv = mptrace (XPT_UNDEBUG, PIDGET (inferior_ptid), 1, signo);
- if (-1 == rv)
- {
- error ("mptrace(XPT_UNDEBUG): %s", safe_strerror (errno));
- }
- attach_flag = 0;
-}
-
-#endif /* ATTACH_DETACH */
-\f
-/* Default the type of the ptrace transfer to int. */
-#ifndef PTRACE_XFER_TYPE
-#define PTRACE_XFER_TYPE int
-#endif
-\f
-
-/* NOTE! I tried using PTRACE_READDATA, etc., to read and write memory
- in the NEW_SUN_PTRACE case.
- It ought to be straightforward. But it appears that writing did
- not write the data that I specified. I cannot understand where
- it got the data that it actually did write. */
-
-/* Copy LEN bytes to or from inferior's memory starting at MEMADDR
- to debugger memory starting at MYADDR. Copy to inferior if
- WRITE is nonzero. TARGET is ignored.
-
- Returns the length copied, which is either the LEN argument or zero.
- This xfer function does not do partial moves, since child_ops
- doesn't allow memory operations to cross below us in the target stack
- anyway. */
-
-int
-child_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write,
- struct mem_attrib *attrib,
- struct target_ops *target)
-{
- register int i;
- /* Round starting address down to longword boundary. */
- register CORE_ADDR addr = memaddr & -(CORE_ADDR) sizeof (PTRACE_XFER_TYPE);
- /* Round ending address up; get number of longwords that makes. */
- register int count
- = (((memaddr + len) - addr) + sizeof (PTRACE_XFER_TYPE) - 1)
- / sizeof (PTRACE_XFER_TYPE);
- /* Allocate buffer of that many longwords. */
- /* FIXME (alloca): This code, cloned from infptrace.c, is unsafe
- because it uses alloca to allocate a buffer of arbitrary size.
- For very large xfers, this could crash GDB's stack. */
- register PTRACE_XFER_TYPE *buffer
- = (PTRACE_XFER_TYPE *) alloca (count * sizeof (PTRACE_XFER_TYPE));
-
- if (write)
- {
- /* Fill start and end extra bytes of buffer with existing memory data. */
-
- if (addr != memaddr || len < (int) sizeof (PTRACE_XFER_TYPE))
- {
- /* Need part of initial word -- fetch it. */
- buffer[0] = ptrace (PT_RTEXT, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) addr,
- 0);
- }
-
- if (count > 1) /* FIXME, avoid if even boundary */
- {
- buffer[count - 1]
- = ptrace (PT_RTEXT, PIDGET (inferior_ptid),
- ((PTRACE_ARG3_TYPE)
- (addr + (count - 1) * sizeof (PTRACE_XFER_TYPE))),
- 0);
- }
-
- /* Copy data to be written over corresponding part of buffer */
-
- memcpy ((char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)),
- myaddr,
- len);
-
- /* Write the entire buffer. */
-
- for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE))
- {
- errno = 0;
- ptrace (PT_WDATA, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) addr,
- buffer[i]);
- if (errno)
- {
- /* Using the appropriate one (I or D) is necessary for
- Gould NP1, at least. */
- errno = 0;
- ptrace (PT_WTEXT, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) addr,
- buffer[i]);
- }
- if (errno)
- return 0;
- }
- }
- else
- {
- /* Read all the longwords */
- for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE))
- {
- errno = 0;
- buffer[i] = ptrace (PT_RTEXT, PIDGET (inferior_ptid),
- (PTRACE_ARG3_TYPE) addr, 0);
- if (errno)
- return 0;
- QUIT;
- }
-
- /* Copy appropriate bytes out of the buffer. */
- memcpy (myaddr,
- (char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)),
- len);
- }
- return len;
-}
-
-
-void
-_initialize_symm_nat (void)
-{
-#ifdef ATTACH_DETACH
-/*
- * the MPDEBUGGER is necessary for process tree debugging and attach
- * to work, but it alters the behavior of debugged processes, so other
- * things (at least child_wait()) will have to change to accomodate
- * that.
- *
- * Note that attach is not implemented in dynix 3, and not in ptx
- * until version 2.1 of the OS.
- */
- int rv;
- sigset_t set;
- struct sigaction sact;
-
- rv = mptrace (XPT_MPDEBUGGER, 0, 0, 0);
- if (-1 == rv)
- {
- internal_error (__FILE__, __LINE__,
- "_initialize_symm_nat(): mptrace(XPT_MPDEBUGGER): %s",
- safe_strerror (errno));
- }
-
- /*
- * Under MPDEBUGGER, we get SIGCLHD when a traced process does
- * anything of interest.
- */
-
- /*
- * Block SIGCHLD. We leave it blocked all the time, and then
- * call sigsuspend() in child_wait() to wait for the child
- * to do something. None of these ought to fail, but check anyway.
- */
- sigemptyset (&set);
- rv = sigaddset (&set, SIGCHLD);
- if (-1 == rv)
- {
- internal_error (__FILE__, __LINE__,
- "_initialize_symm_nat(): sigaddset(SIGCHLD): %s",
- safe_strerror (errno));
- }
- rv = sigprocmask (SIG_BLOCK, &set, (sigset_t *) NULL);
- if (-1 == rv)
- {
- internal_error (__FILE__, __LINE__,
- "_initialize_symm_nat(): sigprocmask(SIG_BLOCK): %s",
- safe_strerror (errno));
- }
-
- sact.sa_handler = sigchld_handler;
- sigemptyset (&sact.sa_mask);
- sact.sa_flags = SA_NOCLDWAIT; /* keep the zombies away */
- rv = sigaction (SIGCHLD, &sact, (struct sigaction *) NULL);
- if (-1 == rv)
- {
- internal_error (__FILE__, __LINE__,
- "_initialize_symm_nat(): sigaction(SIGCHLD): %s",
- safe_strerror (errno));
- }
-#endif
-}
+// OBSOLETE /* Sequent Symmetry host interface, for GDB when running under Unix.
+// OBSOLETE
+// OBSOLETE Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1999,
+// OBSOLETE 2000, 2001, 2003 Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /* FIXME, some 387-specific items of use taken from i387-tdep.c -- ought to be
+// OBSOLETE merged back in. */
+// OBSOLETE
+// OBSOLETE #include "defs.h"
+// OBSOLETE #include "frame.h"
+// OBSOLETE #include "inferior.h"
+// OBSOLETE #include "symtab.h"
+// OBSOLETE #include "target.h"
+// OBSOLETE #include "regcache.h"
+// OBSOLETE
+// OBSOLETE /* FIXME: What is the _INKERNEL define for? */
+// OBSOLETE #define _INKERNEL
+// OBSOLETE #include <signal.h>
+// OBSOLETE #undef _INKERNEL
+// OBSOLETE #include "gdb_wait.h"
+// OBSOLETE #include <sys/param.h>
+// OBSOLETE #include <sys/user.h>
+// OBSOLETE #include <sys/proc.h>
+// OBSOLETE #include <sys/dir.h>
+// OBSOLETE #include <sys/ioctl.h>
+// OBSOLETE #include "gdb_stat.h"
+// OBSOLETE #ifdef _SEQUENT_
+// OBSOLETE #include <sys/ptrace.h>
+// OBSOLETE #else
+// OBSOLETE /* Dynix has only machine/ptrace.h, which is already included by sys/user.h */
+// OBSOLETE /* Dynix has no mptrace call */
+// OBSOLETE #define mptrace ptrace
+// OBSOLETE #endif
+// OBSOLETE #include "gdbcore.h"
+// OBSOLETE #include <fcntl.h>
+// OBSOLETE #include <sgtty.h>
+// OBSOLETE #define TERMINAL struct sgttyb
+// OBSOLETE
+// OBSOLETE #include "gdbcore.h"
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE store_inferior_registers (int regno)
+// OBSOLETE {
+// OBSOLETE struct pt_regset regs;
+// OBSOLETE int i;
+// OBSOLETE
+// OBSOLETE /* FIXME: Fetching the registers is a kludge to initialize all elements
+// OBSOLETE in the fpu and fpa status. This works for normal debugging, but
+// OBSOLETE might cause problems when calling functions in the inferior.
+// OBSOLETE At least fpu_control and fpa_pcr (probably more) should be added
+// OBSOLETE to the registers array to solve this properly. */
+// OBSOLETE mptrace (XPT_RREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regs, 0);
+// OBSOLETE
+// OBSOLETE regs.pr_eax = *(int *) &deprecated_registers[REGISTER_BYTE (0)];
+// OBSOLETE regs.pr_ebx = *(int *) &deprecated_registers[REGISTER_BYTE (5)];
+// OBSOLETE regs.pr_ecx = *(int *) &deprecated_registers[REGISTER_BYTE (2)];
+// OBSOLETE regs.pr_edx = *(int *) &deprecated_registers[REGISTER_BYTE (1)];
+// OBSOLETE regs.pr_esi = *(int *) &deprecated_registers[REGISTER_BYTE (6)];
+// OBSOLETE regs.pr_edi = *(int *) &deprecated_registers[REGISTER_BYTE (7)];
+// OBSOLETE regs.pr_esp = *(int *) &deprecated_registers[REGISTER_BYTE (14)];
+// OBSOLETE regs.pr_ebp = *(int *) &deprecated_registers[REGISTER_BYTE (15)];
+// OBSOLETE regs.pr_eip = *(int *) &deprecated_registers[REGISTER_BYTE (16)];
+// OBSOLETE regs.pr_flags = *(int *) &deprecated_registers[REGISTER_BYTE (17)];
+// OBSOLETE for (i = 0; i < 31; i++)
+// OBSOLETE {
+// OBSOLETE regs.pr_fpa.fpa_regs[i] =
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (FP1_REGNUM + i)];
+// OBSOLETE }
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[0], &deprecated_registers[REGISTER_BYTE (ST0_REGNUM)], 10);
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[1], &deprecated_registers[REGISTER_BYTE (ST1_REGNUM)], 10);
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[2], &deprecated_registers[REGISTER_BYTE (ST2_REGNUM)], 10);
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[3], &deprecated_registers[REGISTER_BYTE (ST3_REGNUM)], 10);
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[4], &deprecated_registers[REGISTER_BYTE (ST4_REGNUM)], 10);
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[5], &deprecated_registers[REGISTER_BYTE (ST5_REGNUM)], 10);
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[6], &deprecated_registers[REGISTER_BYTE (ST6_REGNUM)], 10);
+// OBSOLETE memcpy (regs.pr_fpu.fpu_stack[7], &deprecated_registers[REGISTER_BYTE (ST7_REGNUM)], 10);
+// OBSOLETE mptrace (XPT_WREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regs, 0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE fetch_inferior_registers (int regno)
+// OBSOLETE {
+// OBSOLETE int i;
+// OBSOLETE struct pt_regset regs;
+// OBSOLETE
+// OBSOLETE deprecated_registers_fetched ();
+// OBSOLETE
+// OBSOLETE mptrace (XPT_RREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regs, 0);
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (EAX_REGNUM)] = regs.pr_eax;
+// OBSOLETE *(int *) &rdeprecated_egisters[REGISTER_BYTE (EBX_REGNUM)] = regs.pr_ebx;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (ECX_REGNUM)] = regs.pr_ecx;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (EDX_REGNUM)] = regs.pr_edx;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (ESI_REGNUM)] = regs.pr_esi;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (EDI_REGNUM)] = regs.pr_edi;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (EBP_REGNUM)] = regs.pr_ebp;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (ESP_REGNUM)] = regs.pr_esp;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (EIP_REGNUM)] = regs.pr_eip;
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (EFLAGS_REGNUM)] = regs.pr_flags;
+// OBSOLETE for (i = 0; i < FPA_NREGS; i++)
+// OBSOLETE {
+// OBSOLETE *(int *) &deprecated_registers[REGISTER_BYTE (FP1_REGNUM + i)] =
+// OBSOLETE regs.pr_fpa.fpa_regs[i];
+// OBSOLETE }
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST0_REGNUM)], regs.pr_fpu.fpu_stack[0], 10);
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST1_REGNUM)], regs.pr_fpu.fpu_stack[1], 10);
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST2_REGNUM)], regs.pr_fpu.fpu_stack[2], 10);
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST3_REGNUM)], regs.pr_fpu.fpu_stack[3], 10);
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST4_REGNUM)], regs.pr_fpu.fpu_stack[4], 10);
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST5_REGNUM)], regs.pr_fpu.fpu_stack[5], 10);
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST6_REGNUM)], regs.pr_fpu.fpu_stack[6], 10);
+// OBSOLETE memcpy (&deprecated_registers[REGISTER_BYTE (ST7_REGNUM)], regs.pr_fpu.fpu_stack[7], 10);
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE /* FIXME: This should be merged with i387-tdep.c as well. */
+// OBSOLETE static
+// OBSOLETE print_fpu_status (struct pt_regset ep)
+// OBSOLETE {
+// OBSOLETE int i;
+// OBSOLETE int bothstatus;
+// OBSOLETE int top;
+// OBSOLETE int fpreg;
+// OBSOLETE unsigned char *p;
+// OBSOLETE
+// OBSOLETE printf_unfiltered ("80387:");
+// OBSOLETE if (ep.pr_fpu.fpu_ip == 0)
+// OBSOLETE {
+// OBSOLETE printf_unfiltered (" not in use.\n");
+// OBSOLETE return;
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("\n");
+// OBSOLETE }
+// OBSOLETE if (ep.pr_fpu.fpu_status != 0)
+// OBSOLETE {
+// OBSOLETE print_387_status_word (ep.pr_fpu.fpu_status);
+// OBSOLETE }
+// OBSOLETE print_387_control_word (ep.pr_fpu.fpu_control);
+// OBSOLETE printf_unfiltered ("last exception: ");
+// OBSOLETE printf_unfiltered ("opcode 0x%x; ", ep.pr_fpu.fpu_rsvd4);
+// OBSOLETE printf_unfiltered ("pc 0x%x:0x%x; ", ep.pr_fpu.fpu_cs, ep.pr_fpu.fpu_ip);
+// OBSOLETE printf_unfiltered ("operand 0x%x:0x%x\n", ep.pr_fpu.fpu_data_offset, ep.pr_fpu.fpu_op_sel);
+// OBSOLETE
+// OBSOLETE top = (ep.pr_fpu.fpu_status >> 11) & 7;
+// OBSOLETE
+// OBSOLETE printf_unfiltered ("regno tag msb lsb value\n");
+// OBSOLETE for (fpreg = 7; fpreg >= 0; fpreg--)
+// OBSOLETE {
+// OBSOLETE double val;
+// OBSOLETE
+// OBSOLETE printf_unfiltered ("%s %d: ", fpreg == top ? "=>" : " ", fpreg);
+// OBSOLETE
+// OBSOLETE switch ((ep.pr_fpu.fpu_tag >> (fpreg * 2)) & 3)
+// OBSOLETE {
+// OBSOLETE case 0:
+// OBSOLETE printf_unfiltered ("valid ");
+// OBSOLETE break;
+// OBSOLETE case 1:
+// OBSOLETE printf_unfiltered ("zero ");
+// OBSOLETE break;
+// OBSOLETE case 2:
+// OBSOLETE printf_unfiltered ("trap ");
+// OBSOLETE break;
+// OBSOLETE case 3:
+// OBSOLETE printf_unfiltered ("empty ");
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE for (i = 9; i >= 0; i--)
+// OBSOLETE printf_unfiltered ("%02x", ep.pr_fpu.fpu_stack[fpreg][i]);
+// OBSOLETE
+// OBSOLETE i387_to_double ((char *) ep.pr_fpu.fpu_stack[fpreg], (char *) &val);
+// OBSOLETE printf_unfiltered (" %g\n", val);
+// OBSOLETE }
+// OBSOLETE if (ep.pr_fpu.fpu_rsvd1)
+// OBSOLETE warning ("rsvd1 is 0x%x\n", ep.pr_fpu.fpu_rsvd1);
+// OBSOLETE if (ep.pr_fpu.fpu_rsvd2)
+// OBSOLETE warning ("rsvd2 is 0x%x\n", ep.pr_fpu.fpu_rsvd2);
+// OBSOLETE if (ep.pr_fpu.fpu_rsvd3)
+// OBSOLETE warning ("rsvd3 is 0x%x\n", ep.pr_fpu.fpu_rsvd3);
+// OBSOLETE if (ep.pr_fpu.fpu_rsvd5)
+// OBSOLETE warning ("rsvd5 is 0x%x\n", ep.pr_fpu.fpu_rsvd5);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE print_1167_control_word (unsigned int pcr)
+// OBSOLETE {
+// OBSOLETE int pcr_tmp;
+// OBSOLETE
+// OBSOLETE pcr_tmp = pcr & FPA_PCR_MODE;
+// OBSOLETE printf_unfiltered ("\tMODE= %#x; RND= %#x ", pcr_tmp, pcr_tmp & 12);
+// OBSOLETE switch (pcr_tmp & 12)
+// OBSOLETE {
+// OBSOLETE case 0:
+// OBSOLETE printf_unfiltered ("RN (Nearest Value)");
+// OBSOLETE break;
+// OBSOLETE case 1:
+// OBSOLETE printf_unfiltered ("RZ (Zero)");
+// OBSOLETE break;
+// OBSOLETE case 2:
+// OBSOLETE printf_unfiltered ("RP (Positive Infinity)");
+// OBSOLETE break;
+// OBSOLETE case 3:
+// OBSOLETE printf_unfiltered ("RM (Negative Infinity)");
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE printf_unfiltered ("; IRND= %d ", pcr_tmp & 2);
+// OBSOLETE if (0 == pcr_tmp & 2)
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("(same as RND)\n");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("(toward zero)\n");
+// OBSOLETE }
+// OBSOLETE pcr_tmp = pcr & FPA_PCR_EM;
+// OBSOLETE printf_unfiltered ("\tEM= %#x", pcr_tmp);
+// OBSOLETE if (pcr_tmp & FPA_PCR_EM_DM)
+// OBSOLETE printf_unfiltered (" DM");
+// OBSOLETE if (pcr_tmp & FPA_PCR_EM_UOM)
+// OBSOLETE printf_unfiltered (" UOM");
+// OBSOLETE if (pcr_tmp & FPA_PCR_EM_PM)
+// OBSOLETE printf_unfiltered (" PM");
+// OBSOLETE if (pcr_tmp & FPA_PCR_EM_UM)
+// OBSOLETE printf_unfiltered (" UM");
+// OBSOLETE if (pcr_tmp & FPA_PCR_EM_OM)
+// OBSOLETE printf_unfiltered (" OM");
+// OBSOLETE if (pcr_tmp & FPA_PCR_EM_ZM)
+// OBSOLETE printf_unfiltered (" ZM");
+// OBSOLETE if (pcr_tmp & FPA_PCR_EM_IM)
+// OBSOLETE printf_unfiltered (" IM");
+// OBSOLETE printf_unfiltered ("\n");
+// OBSOLETE pcr_tmp = FPA_PCR_CC;
+// OBSOLETE printf_unfiltered ("\tCC= %#x", pcr_tmp);
+// OBSOLETE if (pcr_tmp & FPA_PCR_20MHZ)
+// OBSOLETE printf_unfiltered (" 20MHZ");
+// OBSOLETE if (pcr_tmp & FPA_PCR_CC_Z)
+// OBSOLETE printf_unfiltered (" Z");
+// OBSOLETE if (pcr_tmp & FPA_PCR_CC_C2)
+// OBSOLETE printf_unfiltered (" C2");
+// OBSOLETE
+// OBSOLETE /* Dynix defines FPA_PCR_CC_C0 to 0x100 and ptx defines
+// OBSOLETE FPA_PCR_CC_C1 to 0x100. Use whichever is defined and assume
+// OBSOLETE the OS knows what it is doing. */
+// OBSOLETE #ifdef FPA_PCR_CC_C1
+// OBSOLETE if (pcr_tmp & FPA_PCR_CC_C1)
+// OBSOLETE printf_unfiltered (" C1");
+// OBSOLETE #else
+// OBSOLETE if (pcr_tmp & FPA_PCR_CC_C0)
+// OBSOLETE printf_unfiltered (" C0");
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE switch (pcr_tmp)
+// OBSOLETE {
+// OBSOLETE case FPA_PCR_CC_Z:
+// OBSOLETE printf_unfiltered (" (Equal)");
+// OBSOLETE break;
+// OBSOLETE #ifdef FPA_PCR_CC_C1
+// OBSOLETE case FPA_PCR_CC_C1:
+// OBSOLETE #else
+// OBSOLETE case FPA_PCR_CC_C0:
+// OBSOLETE #endif
+// OBSOLETE printf_unfiltered (" (Less than)");
+// OBSOLETE break;
+// OBSOLETE case 0:
+// OBSOLETE printf_unfiltered (" (Greater than)");
+// OBSOLETE break;
+// OBSOLETE case FPA_PCR_CC_Z |
+// OBSOLETE #ifdef FPA_PCR_CC_C1
+// OBSOLETE FPA_PCR_CC_C1
+// OBSOLETE #else
+// OBSOLETE FPA_PCR_CC_C0
+// OBSOLETE #endif
+// OBSOLETE | FPA_PCR_CC_C2:
+// OBSOLETE printf_unfiltered (" (Unordered)");
+// OBSOLETE break;
+// OBSOLETE default:
+// OBSOLETE printf_unfiltered (" (Undefined)");
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE printf_unfiltered ("\n");
+// OBSOLETE pcr_tmp = pcr & FPA_PCR_AE;
+// OBSOLETE printf_unfiltered ("\tAE= %#x", pcr_tmp);
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_DE)
+// OBSOLETE printf_unfiltered (" DE");
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_UOE)
+// OBSOLETE printf_unfiltered (" UOE");
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_PE)
+// OBSOLETE printf_unfiltered (" PE");
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_UE)
+// OBSOLETE printf_unfiltered (" UE");
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_OE)
+// OBSOLETE printf_unfiltered (" OE");
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_ZE)
+// OBSOLETE printf_unfiltered (" ZE");
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_EE)
+// OBSOLETE printf_unfiltered (" EE");
+// OBSOLETE if (pcr_tmp & FPA_PCR_AE_IE)
+// OBSOLETE printf_unfiltered (" IE");
+// OBSOLETE printf_unfiltered ("\n");
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE print_1167_regs (long regs[FPA_NREGS])
+// OBSOLETE {
+// OBSOLETE int i;
+// OBSOLETE
+// OBSOLETE union
+// OBSOLETE {
+// OBSOLETE double d;
+// OBSOLETE long l[2];
+// OBSOLETE }
+// OBSOLETE xd;
+// OBSOLETE union
+// OBSOLETE {
+// OBSOLETE float f;
+// OBSOLETE long l;
+// OBSOLETE }
+// OBSOLETE xf;
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE for (i = 0; i < FPA_NREGS; i++)
+// OBSOLETE {
+// OBSOLETE xf.l = regs[i];
+// OBSOLETE printf_unfiltered ("%%fp%d: raw= %#x, single= %f", i + 1, regs[i], xf.f);
+// OBSOLETE if (!(i & 1))
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("\n");
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE xd.l[1] = regs[i];
+// OBSOLETE xd.l[0] = regs[i + 1];
+// OBSOLETE printf_unfiltered (", double= %f\n", xd.d);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE print_fpa_status (struct pt_regset ep)
+// OBSOLETE {
+// OBSOLETE
+// OBSOLETE printf_unfiltered ("WTL 1167:");
+// OBSOLETE if (ep.pr_fpa.fpa_pcr != 0)
+// OBSOLETE {
+// OBSOLETE printf_unfiltered ("\n");
+// OBSOLETE print_1167_control_word (ep.pr_fpa.fpa_pcr);
+// OBSOLETE print_1167_regs (ep.pr_fpa.fpa_regs);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE printf_unfiltered (" not in use.\n");
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #if 0 /* disabled because it doesn't go through the target vector. */
+// OBSOLETE i386_float_info (void)
+// OBSOLETE {
+// OBSOLETE char ubuf[UPAGES * NBPG];
+// OBSOLETE struct pt_regset regset;
+// OBSOLETE
+// OBSOLETE if (have_inferior_p ())
+// OBSOLETE {
+// OBSOLETE PTRACE_READ_REGS (PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) & regset);
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE int corechan = bfd_cache_lookup (core_bfd);
+// OBSOLETE if (lseek (corechan, 0, 0) < 0)
+// OBSOLETE {
+// OBSOLETE perror ("seek on core file");
+// OBSOLETE }
+// OBSOLETE if (myread (corechan, ubuf, UPAGES * NBPG) < 0)
+// OBSOLETE {
+// OBSOLETE perror ("read on core file");
+// OBSOLETE }
+// OBSOLETE /* only interested in the floating point registers */
+// OBSOLETE regset.pr_fpu = ((struct user *) ubuf)->u_fpusave;
+// OBSOLETE regset.pr_fpa = ((struct user *) ubuf)->u_fpasave;
+// OBSOLETE }
+// OBSOLETE print_fpu_status (regset);
+// OBSOLETE print_fpa_status (regset);
+// OBSOLETE }
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE static volatile int got_sigchld;
+// OBSOLETE
+// OBSOLETE /*ARGSUSED */
+// OBSOLETE /* This will eventually be more interesting. */
+// OBSOLETE void
+// OBSOLETE sigchld_handler (int signo)
+// OBSOLETE {
+// OBSOLETE got_sigchld++;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Signals for which the default action does not cause the process
+// OBSOLETE * to die. See <sys/signal.h> for where this came from (alas, we
+// OBSOLETE * can't use those macros directly)
+// OBSOLETE */
+// OBSOLETE #ifndef sigmask
+// OBSOLETE #define sigmask(s) (1 << ((s) - 1))
+// OBSOLETE #endif
+// OBSOLETE #define SIGNALS_DFL_SAFE sigmask(SIGSTOP) | sigmask(SIGTSTP) | \
+// OBSOLETE sigmask(SIGTTIN) | sigmask(SIGTTOU) | sigmask(SIGCHLD) | \
+// OBSOLETE sigmask(SIGCONT) | sigmask(SIGWINCH) | sigmask(SIGPWR) | \
+// OBSOLETE sigmask(SIGURG) | sigmask(SIGPOLL)
+// OBSOLETE
+// OBSOLETE #ifdef ATTACH_DETACH
+// OBSOLETE /*
+// OBSOLETE * Thanks to XPT_MPDEBUGGER, we have to mange child_wait().
+// OBSOLETE */
+// OBSOLETE ptid_t
+// OBSOLETE child_wait (ptid_t ptid, struct target_waitstatus *status)
+// OBSOLETE {
+// OBSOLETE int save_errno, rv, xvaloff, saoff, sa_hand;
+// OBSOLETE struct pt_stop pt;
+// OBSOLETE struct user u;
+// OBSOLETE sigset_t set;
+// OBSOLETE /* Host signal number for a signal which the inferior terminates with, or
+// OBSOLETE 0 if it hasn't terminated due to a signal. */
+// OBSOLETE static int death_by_signal = 0;
+// OBSOLETE #ifdef SVR4_SHARED_LIBS /* use this to distinguish ptx 2 vs ptx 4 */
+// OBSOLETE prstatus_t pstatus;
+// OBSOLETE #endif
+// OBSOLETE int pid = PIDGET (ptid);
+// OBSOLETE
+// OBSOLETE do
+// OBSOLETE {
+// OBSOLETE set_sigint_trap (); /* Causes SIGINT to be passed on to the
+// OBSOLETE attached process. */
+// OBSOLETE save_errno = errno;
+// OBSOLETE
+// OBSOLETE got_sigchld = 0;
+// OBSOLETE
+// OBSOLETE sigemptyset (&set);
+// OBSOLETE
+// OBSOLETE while (got_sigchld == 0)
+// OBSOLETE {
+// OBSOLETE sigsuspend (&set);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE clear_sigint_trap ();
+// OBSOLETE
+// OBSOLETE rv = mptrace (XPT_STOPSTAT, 0, (char *) &pt, 0);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE printf ("XPT_STOPSTAT: errno %d\n", errno); /* DEBUG */
+// OBSOLETE continue;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE pid = pt.ps_pid;
+// OBSOLETE
+// OBSOLETE if (pid != PIDGET (inferior_ptid))
+// OBSOLETE {
+// OBSOLETE /* NOTE: the mystery fork in csh/tcsh needs to be ignored.
+// OBSOLETE * We should not return new children for the initial run
+// OBSOLETE * of a process until it has done the exec.
+// OBSOLETE */
+// OBSOLETE /* inferior probably forked; send it on its way */
+// OBSOLETE rv = mptrace (XPT_UNDEBUG, pid, 0, 0);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE printf ("child_wait: XPT_UNDEBUG: pid %d: %s\n", pid,
+// OBSOLETE safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE continue;
+// OBSOLETE }
+// OBSOLETE /* FIXME: Do we deal with fork notification correctly? */
+// OBSOLETE switch (pt.ps_reason)
+// OBSOLETE {
+// OBSOLETE case PTS_FORK:
+// OBSOLETE /* multi proc: treat like PTS_EXEC */
+// OBSOLETE /*
+// OBSOLETE * Pretend this didn't happen, since gdb isn't set up
+// OBSOLETE * to deal with stops on fork.
+// OBSOLETE */
+// OBSOLETE rv = ptrace (PT_CONTSIG, pid, 1, 0);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE printf ("PTS_FORK: PT_CONTSIG: error %d\n", errno);
+// OBSOLETE }
+// OBSOLETE continue;
+// OBSOLETE case PTS_EXEC:
+// OBSOLETE /*
+// OBSOLETE * Pretend this is a SIGTRAP.
+// OBSOLETE */
+// OBSOLETE status->kind = TARGET_WAITKIND_STOPPED;
+// OBSOLETE status->value.sig = TARGET_SIGNAL_TRAP;
+// OBSOLETE break;
+// OBSOLETE case PTS_EXIT:
+// OBSOLETE /*
+// OBSOLETE * Note: we stop before the exit actually occurs. Extract
+// OBSOLETE * the exit code from the uarea. If we're stopped in the
+// OBSOLETE * exit() system call, the exit code will be in
+// OBSOLETE * u.u_ap[0]. An exit due to an uncaught signal will have
+// OBSOLETE * something else in here, see the comment in the default:
+// OBSOLETE * case, below. Finally,let the process exit.
+// OBSOLETE */
+// OBSOLETE if (death_by_signal)
+// OBSOLETE {
+// OBSOLETE status->kind = TARGET_WAITKIND_SIGNALED;
+// OBSOLETE status->value.sig = target_signal_from_host (death_by_signal);
+// OBSOLETE death_by_signal = 0;
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE xvaloff = (unsigned long) &u.u_ap[0] - (unsigned long) &u;
+// OBSOLETE errno = 0;
+// OBSOLETE rv = ptrace (PT_RUSER, pid, (char *) xvaloff, 0);
+// OBSOLETE status->kind = TARGET_WAITKIND_EXITED;
+// OBSOLETE status->value.integer = rv;
+// OBSOLETE /*
+// OBSOLETE * addr & data to mptrace() don't matter here, since
+// OBSOLETE * the process is already dead.
+// OBSOLETE */
+// OBSOLETE rv = mptrace (XPT_UNDEBUG, pid, 0, 0);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE printf ("child_wait: PTS_EXIT: XPT_UNDEBUG: pid %d error %d\n", pid,
+// OBSOLETE errno);
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE case PTS_WATCHPT_HIT:
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "PTS_WATCHPT_HIT\n");
+// OBSOLETE break;
+// OBSOLETE default:
+// OBSOLETE /* stopped by signal */
+// OBSOLETE status->kind = TARGET_WAITKIND_STOPPED;
+// OBSOLETE status->value.sig = target_signal_from_host (pt.ps_reason);
+// OBSOLETE death_by_signal = 0;
+// OBSOLETE
+// OBSOLETE if (0 == (SIGNALS_DFL_SAFE & sigmask (pt.ps_reason)))
+// OBSOLETE {
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE /* else default action of signal is to die */
+// OBSOLETE #ifdef SVR4_SHARED_LIBS
+// OBSOLETE rv = ptrace (PT_GET_PRSTATUS, pid, (char *) &pstatus, 0);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE error ("child_wait: signal %d PT_GET_PRSTATUS: %s\n",
+// OBSOLETE pt.ps_reason, safe_strerror (errno));
+// OBSOLETE if (pstatus.pr_cursig != pt.ps_reason)
+// OBSOLETE {
+// OBSOLETE printf ("pstatus signal %d, pt signal %d\n",
+// OBSOLETE pstatus.pr_cursig, pt.ps_reason);
+// OBSOLETE }
+// OBSOLETE sa_hand = (int) pstatus.pr_action.sa_handler;
+// OBSOLETE #else
+// OBSOLETE saoff = (unsigned long) &u.u_sa[0] - (unsigned long) &u;
+// OBSOLETE saoff += sizeof (struct sigaction) * (pt.ps_reason - 1);
+// OBSOLETE errno = 0;
+// OBSOLETE sa_hand = ptrace (PT_RUSER, pid, (char *) saoff, 0);
+// OBSOLETE if (errno)
+// OBSOLETE error ("child_wait: signal %d: RUSER: %s\n",
+// OBSOLETE pt.ps_reason, safe_strerror (errno));
+// OBSOLETE #endif
+// OBSOLETE if ((int) SIG_DFL == sa_hand)
+// OBSOLETE {
+// OBSOLETE /* we will be dying */
+// OBSOLETE death_by_signal = pt.ps_reason;
+// OBSOLETE }
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE }
+// OBSOLETE while (pid != PIDGET (inferior_ptid)); /* Some other child died or stopped */
+// OBSOLETE
+// OBSOLETE return pid_to_ptid (pid);
+// OBSOLETE }
+// OBSOLETE #else /* !ATTACH_DETACH */
+// OBSOLETE /*
+// OBSOLETE * Simple child_wait() based on inftarg.c child_wait() for use until
+// OBSOLETE * the MPDEBUGGER child_wait() works properly. This will go away when
+// OBSOLETE * that is fixed.
+// OBSOLETE */
+// OBSOLETE ptid_t
+// OBSOLETE child_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
+// OBSOLETE {
+// OBSOLETE int save_errno;
+// OBSOLETE int status;
+// OBSOLETE int pid = PIDGET (ptid);
+// OBSOLETE
+// OBSOLETE do
+// OBSOLETE {
+// OBSOLETE pid = wait (&status);
+// OBSOLETE save_errno = errno;
+// OBSOLETE
+// OBSOLETE if (pid == -1)
+// OBSOLETE {
+// OBSOLETE if (save_errno == EINTR)
+// OBSOLETE continue;
+// OBSOLETE fprintf (stderr, "Child process unexpectedly missing: %s.\n",
+// OBSOLETE safe_strerror (save_errno));
+// OBSOLETE ourstatus->kind = TARGET_WAITKIND_SIGNALLED;
+// OBSOLETE ourstatus->value.sig = TARGET_SIGNAL_UNKNOWN;
+// OBSOLETE return pid_to_ptid (-1);
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE while (pid != PIDGET (inferior_ptid)); /* Some other child died or stopped */
+// OBSOLETE store_waitstatus (ourstatus, status);
+// OBSOLETE return pid_to_ptid (pid);
+// OBSOLETE }
+// OBSOLETE #endif /* ATTACH_DETACH */
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE /* This function simply calls ptrace with the given arguments.
+// OBSOLETE It exists so that all calls to ptrace are isolated in this
+// OBSOLETE machine-dependent file. */
+// OBSOLETE int
+// OBSOLETE call_ptrace (int request, int pid, PTRACE_ARG3_TYPE addr, int data)
+// OBSOLETE {
+// OBSOLETE return ptrace (request, pid, addr, data);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE call_mptrace (int request, int pid, PTRACE_ARG3_TYPE addr, int data)
+// OBSOLETE {
+// OBSOLETE return mptrace (request, pid, addr, data);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #if defined (DEBUG_PTRACE)
+// OBSOLETE /* For the rest of the file, use an extra level of indirection */
+// OBSOLETE /* This lets us breakpoint usefully on call_ptrace. */
+// OBSOLETE #define ptrace call_ptrace
+// OBSOLETE #define mptrace call_mptrace
+// OBSOLETE #endif
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE kill_inferior (void)
+// OBSOLETE {
+// OBSOLETE if (ptid_equal (inferior_ptid, null_ptid))
+// OBSOLETE return;
+// OBSOLETE
+// OBSOLETE /* For MPDEBUGGER, don't use PT_KILL, since the child will stop
+// OBSOLETE again with a PTS_EXIT. Just hit him with SIGKILL (so he stops)
+// OBSOLETE and detach. */
+// OBSOLETE
+// OBSOLETE kill (PIDGET (inferior_ptid), SIGKILL);
+// OBSOLETE #ifdef ATTACH_DETACH
+// OBSOLETE detach (SIGKILL);
+// OBSOLETE #else /* ATTACH_DETACH */
+// OBSOLETE ptrace (PT_KILL, PIDGET (inferior_ptid), 0, 0);
+// OBSOLETE wait ((int *) NULL);
+// OBSOLETE #endif /* ATTACH_DETACH */
+// OBSOLETE target_mourn_inferior ();
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Resume execution of the inferior process.
+// OBSOLETE If STEP is nonzero, single-step it.
+// OBSOLETE If SIGNAL is nonzero, give it that signal. */
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE child_resume (ptid_t ptid, int step, enum target_signal signal)
+// OBSOLETE {
+// OBSOLETE int pid = PIDGET (ptid);
+// OBSOLETE
+// OBSOLETE errno = 0;
+// OBSOLETE
+// OBSOLETE if (pid == -1)
+// OBSOLETE pid = PIDGET (inferior_ptid);
+// OBSOLETE
+// OBSOLETE /* An address of (PTRACE_ARG3_TYPE)1 tells ptrace to continue from where
+// OBSOLETE it was. (If GDB wanted it to start some other way, we have already
+// OBSOLETE written a new PC value to the child.)
+// OBSOLETE
+// OBSOLETE If this system does not support PT_SSTEP, a higher level function will
+// OBSOLETE have called single_step() to transmute the step request into a
+// OBSOLETE continue request (by setting breakpoints on all possible successor
+// OBSOLETE instructions), so we don't have to worry about that here. */
+// OBSOLETE
+// OBSOLETE if (step)
+// OBSOLETE ptrace (PT_SSTEP, pid, (PTRACE_ARG3_TYPE) 1, signal);
+// OBSOLETE else
+// OBSOLETE ptrace (PT_CONTSIG, pid, (PTRACE_ARG3_TYPE) 1, signal);
+// OBSOLETE
+// OBSOLETE if (errno)
+// OBSOLETE perror_with_name ("ptrace");
+// OBSOLETE }
+// OBSOLETE \f
+// OBSOLETE #ifdef ATTACH_DETACH
+// OBSOLETE /* Start debugging the process whose number is PID. */
+// OBSOLETE int
+// OBSOLETE attach (int pid)
+// OBSOLETE {
+// OBSOLETE sigset_t set;
+// OBSOLETE int rv;
+// OBSOLETE
+// OBSOLETE rv = mptrace (XPT_DEBUG, pid, 0, 0);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE error ("mptrace(XPT_DEBUG): %s", safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE rv = mptrace (XPT_SIGNAL, pid, 0, SIGSTOP);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE error ("mptrace(XPT_SIGNAL): %s", safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE attach_flag = 1;
+// OBSOLETE return pid;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE detach (int signo)
+// OBSOLETE {
+// OBSOLETE int rv;
+// OBSOLETE
+// OBSOLETE rv = mptrace (XPT_UNDEBUG, PIDGET (inferior_ptid), 1, signo);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE error ("mptrace(XPT_UNDEBUG): %s", safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE attach_flag = 0;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE #endif /* ATTACH_DETACH */
+// OBSOLETE \f
+// OBSOLETE /* Default the type of the ptrace transfer to int. */
+// OBSOLETE #ifndef PTRACE_XFER_TYPE
+// OBSOLETE #define PTRACE_XFER_TYPE int
+// OBSOLETE #endif
+// OBSOLETE \f
+// OBSOLETE
+// OBSOLETE /* NOTE! I tried using PTRACE_READDATA, etc., to read and write memory
+// OBSOLETE in the NEW_SUN_PTRACE case.
+// OBSOLETE It ought to be straightforward. But it appears that writing did
+// OBSOLETE not write the data that I specified. I cannot understand where
+// OBSOLETE it got the data that it actually did write. */
+// OBSOLETE
+// OBSOLETE /* Copy LEN bytes to or from inferior's memory starting at MEMADDR
+// OBSOLETE to debugger memory starting at MYADDR. Copy to inferior if
+// OBSOLETE WRITE is nonzero. TARGET is ignored.
+// OBSOLETE
+// OBSOLETE Returns the length copied, which is either the LEN argument or zero.
+// OBSOLETE This xfer function does not do partial moves, since child_ops
+// OBSOLETE doesn't allow memory operations to cross below us in the target stack
+// OBSOLETE anyway. */
+// OBSOLETE
+// OBSOLETE int
+// OBSOLETE child_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write,
+// OBSOLETE struct mem_attrib *attrib,
+// OBSOLETE struct target_ops *target)
+// OBSOLETE {
+// OBSOLETE register int i;
+// OBSOLETE /* Round starting address down to longword boundary. */
+// OBSOLETE register CORE_ADDR addr = memaddr & -(CORE_ADDR) sizeof (PTRACE_XFER_TYPE);
+// OBSOLETE /* Round ending address up; get number of longwords that makes. */
+// OBSOLETE register int count
+// OBSOLETE = (((memaddr + len) - addr) + sizeof (PTRACE_XFER_TYPE) - 1)
+// OBSOLETE / sizeof (PTRACE_XFER_TYPE);
+// OBSOLETE /* Allocate buffer of that many longwords. */
+// OBSOLETE /* FIXME (alloca): This code, cloned from infptrace.c, is unsafe
+// OBSOLETE because it uses alloca to allocate a buffer of arbitrary size.
+// OBSOLETE For very large xfers, this could crash GDB's stack. */
+// OBSOLETE register PTRACE_XFER_TYPE *buffer
+// OBSOLETE = (PTRACE_XFER_TYPE *) alloca (count * sizeof (PTRACE_XFER_TYPE));
+// OBSOLETE
+// OBSOLETE if (write)
+// OBSOLETE {
+// OBSOLETE /* Fill start and end extra bytes of buffer with existing memory data. */
+// OBSOLETE
+// OBSOLETE if (addr != memaddr || len < (int) sizeof (PTRACE_XFER_TYPE))
+// OBSOLETE {
+// OBSOLETE /* Need part of initial word -- fetch it. */
+// OBSOLETE buffer[0] = ptrace (PT_RTEXT, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) addr,
+// OBSOLETE 0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE if (count > 1) /* FIXME, avoid if even boundary */
+// OBSOLETE {
+// OBSOLETE buffer[count - 1]
+// OBSOLETE = ptrace (PT_RTEXT, PIDGET (inferior_ptid),
+// OBSOLETE ((PTRACE_ARG3_TYPE)
+// OBSOLETE (addr + (count - 1) * sizeof (PTRACE_XFER_TYPE))),
+// OBSOLETE 0);
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Copy data to be written over corresponding part of buffer */
+// OBSOLETE
+// OBSOLETE memcpy ((char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)),
+// OBSOLETE myaddr,
+// OBSOLETE len);
+// OBSOLETE
+// OBSOLETE /* Write the entire buffer. */
+// OBSOLETE
+// OBSOLETE for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE))
+// OBSOLETE {
+// OBSOLETE errno = 0;
+// OBSOLETE ptrace (PT_WDATA, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) addr,
+// OBSOLETE buffer[i]);
+// OBSOLETE if (errno)
+// OBSOLETE {
+// OBSOLETE /* Using the appropriate one (I or D) is necessary for
+// OBSOLETE Gould NP1, at least. */
+// OBSOLETE errno = 0;
+// OBSOLETE ptrace (PT_WTEXT, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) addr,
+// OBSOLETE buffer[i]);
+// OBSOLETE }
+// OBSOLETE if (errno)
+// OBSOLETE return 0;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE /* Read all the longwords */
+// OBSOLETE for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE))
+// OBSOLETE {
+// OBSOLETE errno = 0;
+// OBSOLETE buffer[i] = ptrace (PT_RTEXT, PIDGET (inferior_ptid),
+// OBSOLETE (PTRACE_ARG3_TYPE) addr, 0);
+// OBSOLETE if (errno)
+// OBSOLETE return 0;
+// OBSOLETE QUIT;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /* Copy appropriate bytes out of the buffer. */
+// OBSOLETE memcpy (myaddr,
+// OBSOLETE (char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)),
+// OBSOLETE len);
+// OBSOLETE }
+// OBSOLETE return len;
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE _initialize_symm_nat (void)
+// OBSOLETE {
+// OBSOLETE #ifdef ATTACH_DETACH
+// OBSOLETE /*
+// OBSOLETE * the MPDEBUGGER is necessary for process tree debugging and attach
+// OBSOLETE * to work, but it alters the behavior of debugged processes, so other
+// OBSOLETE * things (at least child_wait()) will have to change to accomodate
+// OBSOLETE * that.
+// OBSOLETE *
+// OBSOLETE * Note that attach is not implemented in dynix 3, and not in ptx
+// OBSOLETE * until version 2.1 of the OS.
+// OBSOLETE */
+// OBSOLETE int rv;
+// OBSOLETE sigset_t set;
+// OBSOLETE struct sigaction sact;
+// OBSOLETE
+// OBSOLETE rv = mptrace (XPT_MPDEBUGGER, 0, 0, 0);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "_initialize_symm_nat(): mptrace(XPT_MPDEBUGGER): %s",
+// OBSOLETE safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Under MPDEBUGGER, we get SIGCLHD when a traced process does
+// OBSOLETE * anything of interest.
+// OBSOLETE */
+// OBSOLETE
+// OBSOLETE /*
+// OBSOLETE * Block SIGCHLD. We leave it blocked all the time, and then
+// OBSOLETE * call sigsuspend() in child_wait() to wait for the child
+// OBSOLETE * to do something. None of these ought to fail, but check anyway.
+// OBSOLETE */
+// OBSOLETE sigemptyset (&set);
+// OBSOLETE rv = sigaddset (&set, SIGCHLD);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "_initialize_symm_nat(): sigaddset(SIGCHLD): %s",
+// OBSOLETE safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE rv = sigprocmask (SIG_BLOCK, &set, (sigset_t *) NULL);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "_initialize_symm_nat(): sigprocmask(SIG_BLOCK): %s",
+// OBSOLETE safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE
+// OBSOLETE sact.sa_handler = sigchld_handler;
+// OBSOLETE sigemptyset (&sact.sa_mask);
+// OBSOLETE sact.sa_flags = SA_NOCLDWAIT; /* keep the zombies away */
+// OBSOLETE rv = sigaction (SIGCHLD, &sact, (struct sigaction *) NULL);
+// OBSOLETE if (-1 == rv)
+// OBSOLETE {
+// OBSOLETE internal_error (__FILE__, __LINE__,
+// OBSOLETE "_initialize_symm_nat(): sigaction(SIGCHLD): %s",
+// OBSOLETE safe_strerror (errno));
+// OBSOLETE }
+// OBSOLETE #endif
+// OBSOLETE }
-/* Sequent Symmetry target interface, for GDB.
- Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 2000
- Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-/* many 387-specific items of use taken from i386-dep.c */
-
-#include "defs.h"
-#include "frame.h"
-#include "inferior.h"
-#include "symtab.h"
-
-#include <signal.h>
-#include <sys/param.h>
-#include <sys/user.h>
-#include <sys/dir.h>
-#include <sys/ioctl.h>
-#include "gdb_stat.h"
-#include "gdbcore.h"
-#include <fcntl.h>
-
-void
-symmetry_extract_return_value (struct type *type, char *regbuf, char *valbuf)
-{
- union
- {
- double d;
- int l[2];
- }
- xd;
- struct minimal_symbol *msymbol;
- float f;
-
- if (TYPE_CODE_FLT == TYPE_CODE (type))
- {
- msymbol = lookup_minimal_symbol ("1167_flt", NULL, NULL);
- if (msymbol != NULL)
- {
- /* found "1167_flt" means 1167, %fp2-%fp3 */
- /* float & double; 19= %fp2, 20= %fp3 */
- /* no single precision on 1167 */
- xd.l[1] = *((int *) ®buf[REGISTER_BYTE (19)]);
- xd.l[0] = *((int *) ®buf[REGISTER_BYTE (20)]);
- switch (TYPE_LENGTH (type))
- {
- case 4:
- /* FIXME: broken for cross-debugging. */
- f = (float) xd.d;
- memcpy (valbuf, &f, TYPE_LENGTH (type));
- break;
- case 8:
- /* FIXME: broken for cross-debugging. */
- memcpy (valbuf, &xd.d, TYPE_LENGTH (type));
- break;
- default:
- error ("Unknown floating point size");
- break;
- }
- }
- else
- {
- /* 387 %st(0), gcc uses this */
- i387_to_double (((int *) ®buf[REGISTER_BYTE (3)]),
- &xd.d);
- switch (TYPE_LENGTH (type))
- {
- case 4: /* float */
- f = (float) xd.d;
- /* FIXME: broken for cross-debugging. */
- memcpy (valbuf, &f, 4);
- break;
- case 8: /* double */
- /* FIXME: broken for cross-debugging. */
- memcpy (valbuf, &xd.d, 8);
- break;
- default:
- error ("Unknown floating point size");
- break;
- }
- }
- }
- else
- {
- memcpy (valbuf, regbuf, TYPE_LENGTH (type));
- }
-}
+// OBSOLETE /* Sequent Symmetry target interface, for GDB.
+// OBSOLETE Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 2000
+// OBSOLETE Free Software Foundation, Inc.
+// OBSOLETE
+// OBSOLETE This file is part of GDB.
+// OBSOLETE
+// OBSOLETE This program is free software; you can redistribute it and/or modify
+// OBSOLETE it under the terms of the GNU General Public License as published by
+// OBSOLETE the Free Software Foundation; either version 2 of the License, or
+// OBSOLETE (at your option) any later version.
+// OBSOLETE
+// OBSOLETE This program is distributed in the hope that it will be useful,
+// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
+// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// OBSOLETE GNU General Public License for more details.
+// OBSOLETE
+// OBSOLETE You should have received a copy of the GNU General Public License
+// OBSOLETE along with this program; if not, write to the Free Software
+// OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330,
+// OBSOLETE Boston, MA 02111-1307, USA. */
+// OBSOLETE
+// OBSOLETE /* many 387-specific items of use taken from i386-dep.c */
+// OBSOLETE
+// OBSOLETE #include "defs.h"
+// OBSOLETE #include "frame.h"
+// OBSOLETE #include "inferior.h"
+// OBSOLETE #include "symtab.h"
+// OBSOLETE
+// OBSOLETE #include <signal.h>
+// OBSOLETE #include <sys/param.h>
+// OBSOLETE #include <sys/user.h>
+// OBSOLETE #include <sys/dir.h>
+// OBSOLETE #include <sys/ioctl.h>
+// OBSOLETE #include "gdb_stat.h"
+// OBSOLETE #include "gdbcore.h"
+// OBSOLETE #include <fcntl.h>
+// OBSOLETE
+// OBSOLETE void
+// OBSOLETE symmetry_extract_return_value (struct type *type, char *regbuf, char *valbuf)
+// OBSOLETE {
+// OBSOLETE union
+// OBSOLETE {
+// OBSOLETE double d;
+// OBSOLETE int l[2];
+// OBSOLETE }
+// OBSOLETE xd;
+// OBSOLETE struct minimal_symbol *msymbol;
+// OBSOLETE float f;
+// OBSOLETE
+// OBSOLETE if (TYPE_CODE_FLT == TYPE_CODE (type))
+// OBSOLETE {
+// OBSOLETE msymbol = lookup_minimal_symbol ("1167_flt", NULL, NULL);
+// OBSOLETE if (msymbol != NULL)
+// OBSOLETE {
+// OBSOLETE /* found "1167_flt" means 1167, %fp2-%fp3 */
+// OBSOLETE /* float & double; 19= %fp2, 20= %fp3 */
+// OBSOLETE /* no single precision on 1167 */
+// OBSOLETE xd.l[1] = *((int *) ®buf[REGISTER_BYTE (19)]);
+// OBSOLETE xd.l[0] = *((int *) ®buf[REGISTER_BYTE (20)]);
+// OBSOLETE switch (TYPE_LENGTH (type))
+// OBSOLETE {
+// OBSOLETE case 4:
+// OBSOLETE /* FIXME: broken for cross-debugging. */
+// OBSOLETE f = (float) xd.d;
+// OBSOLETE memcpy (valbuf, &f, TYPE_LENGTH (type));
+// OBSOLETE break;
+// OBSOLETE case 8:
+// OBSOLETE /* FIXME: broken for cross-debugging. */
+// OBSOLETE memcpy (valbuf, &xd.d, TYPE_LENGTH (type));
+// OBSOLETE break;
+// OBSOLETE default:
+// OBSOLETE error ("Unknown floating point size");
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE /* 387 %st(0), gcc uses this */
+// OBSOLETE i387_to_double (((int *) ®buf[REGISTER_BYTE (3)]),
+// OBSOLETE &xd.d);
+// OBSOLETE switch (TYPE_LENGTH (type))
+// OBSOLETE {
+// OBSOLETE case 4: /* float */
+// OBSOLETE f = (float) xd.d;
+// OBSOLETE /* FIXME: broken for cross-debugging. */
+// OBSOLETE memcpy (valbuf, &f, 4);
+// OBSOLETE break;
+// OBSOLETE case 8: /* double */
+// OBSOLETE /* FIXME: broken for cross-debugging. */
+// OBSOLETE memcpy (valbuf, &xd.d, 8);
+// OBSOLETE break;
+// OBSOLETE default:
+// OBSOLETE error ("Unknown floating point size");
+// OBSOLETE break;
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE }
+// OBSOLETE else
+// OBSOLETE {
+// OBSOLETE memcpy (valbuf, regbuf, TYPE_LENGTH (type));
+// OBSOLETE }
+// OBSOLETE }
#include "language.h"
#include "bcache.h"
#include "block.h"
+#include "gdb_regex.h"
#include "gdb_string.h"
#include <readline/readline.h>
immediate_quit--;
}
+
+/* List all the symbol tables. */
+void
+maintenance_list_symtabs (char *regexp, int from_tty)
+{
+ struct objfile *objfile;
+
+ if (regexp)
+ re_comp (regexp);
+
+ ALL_OBJFILES (objfile)
+ {
+ struct symtab *symtab;
+
+ /* We don't want to print anything for this objfile until we
+ actually find a symtab whose name matches. */
+ int printed_objfile_start = 0;
+
+ ALL_OBJFILE_SYMTABS (objfile, symtab)
+ if (! regexp
+ || re_exec (symtab->filename))
+ {
+ if (! printed_objfile_start)
+ {
+ printf_filtered ("{ objfile %s ", objfile->name);
+ wrap_here (" ");
+ printf_filtered ("((struct objfile *) %p)\n", objfile);
+ printed_objfile_start = 1;
+ }
+
+ printf_filtered (" { symtab %s ", symtab->filename);
+ wrap_here (" ");
+ printf_filtered ("((struct symtab *) %p)\n", symtab);
+ printf_filtered (" dirname %s\n",
+ symtab->dirname ? symtab->dirname : "(null)");
+ printf_filtered (" fullname %s\n",
+ symtab->fullname ? symtab->fullname : "(null)");
+ printf_filtered (" blockvector ((struct blockvector *) %p)%s\n",
+ symtab->blockvector,
+ symtab->primary ? " (primary)" : "");
+ printf_filtered (" debugformat %s\n", symtab->debugformat);
+ printf_filtered (" }\n");
+ }
+
+ if (printed_objfile_start)
+ printf_filtered ("}\n");
+ }
+}
+
+
+/* List all the partial symbol tables. */
+void
+maintenance_list_psymtabs (char *regexp, int from_tty)
+{
+ struct objfile *objfile;
+
+ if (regexp)
+ re_comp (regexp);
+
+ ALL_OBJFILES (objfile)
+ {
+ struct partial_symtab *psymtab;
+
+ /* We don't want to print anything for this objfile until we
+ actually find a symtab whose name matches. */
+ int printed_objfile_start = 0;
+
+ ALL_OBJFILE_PSYMTABS (objfile, psymtab)
+ if (! regexp
+ || re_exec (psymtab->filename))
+ {
+ if (! printed_objfile_start)
+ {
+ printf_filtered ("{ objfile %s ", objfile->name);
+ wrap_here (" ");
+ printf_filtered ("((struct objfile *) %p)\n", objfile);
+ printed_objfile_start = 1;
+ }
+
+ printf_filtered (" { psymtab %s ", psymtab->filename);
+ wrap_here (" ");
+ printf_filtered ("((struct partial_symtab *) %p)\n", psymtab);
+ printf_filtered (" readin %s\n",
+ psymtab->readin ? "yes" : "no");
+ printf_filtered (" fullname %s\n",
+ psymtab->fullname ? psymtab->fullname : "(null)");
+ printf_filtered (" text addresses ");
+ print_address_numeric (psymtab->textlow, 1, gdb_stdout);
+ printf_filtered (" -- ");
+ print_address_numeric (psymtab->texthigh, 1, gdb_stdout);
+ printf_filtered ("\n");
+ printf_filtered (" globals ");
+ if (psymtab->n_global_syms)
+ {
+ printf_filtered ("(* (struct partial_symbol **) %p @ %d)\n",
+ (psymtab->objfile->global_psymbols.list
+ + psymtab->globals_offset),
+ psymtab->n_global_syms);
+ }
+ else
+ printf_filtered ("(none)\n");
+ printf_filtered (" statics ");
+ if (psymtab->n_static_syms)
+ {
+ printf_filtered ("(* (struct partial_symbol **) %p @ %d)\n",
+ (psymtab->objfile->static_psymbols.list
+ + psymtab->statics_offset),
+ psymtab->n_static_syms);
+ }
+ else
+ printf_filtered ("(none)\n");
+ printf_filtered (" dependencies ");
+ if (psymtab->number_of_dependencies)
+ {
+ int i;
+
+ printf_filtered ("{\n");
+ for (i = 0; i < psymtab->number_of_dependencies; i++)
+ {
+ struct partial_symtab *dep = psymtab->dependencies[i];
+
+ /* Note the string concatenation there --- no comma. */
+ printf_filtered (" psymtab %s "
+ "((struct partial_symtab *) %p)\n",
+ dep->filename, dep);
+ }
+ printf_filtered (" }\n");
+ }
+ else
+ printf_filtered ("(none)\n");
+ printf_filtered (" }\n");
+ }
+
+ if (printed_objfile_start)
+ printf_filtered ("}\n");
+ }
+}
+
+
/* Check consistency of psymtabs and symtabs. */
void
return NULL;
}
-/* Set both the mangled and demangled (if any) names for GSYMBOL based on
- NAME and LEN. The hash table corresponding to OBJFILE is used, and the
- memory comes from that objfile's symbol_obstack. NAME is copied, so the
- pointer can be discarded after calling this function. */
+/* Set both the mangled and demangled (if any) names for GSYMBOL based
+ on LINKAGE_NAME and LEN. The hash table corresponding to OBJFILE
+ is used, and the memory comes from that objfile's symbol_obstack.
+ LINKAGE_NAME is copied, so the pointer can be discarded after
+ calling this function. */
+
+/* We have to be careful when dealing with Java names: when we run
+ into a Java minimal symbol, we don't know it's a Java symbol, so it
+ gets demangled as a C++ name. This is unfortunate, but there's not
+ much we can do about it: but when demangling partial symbols and
+ regular symbols, we'd better not reuse the wrong demangled name.
+ (See PR gdb/1039.) We solve this by putting a distinctive prefix
+ on Java names when storing them in the hash table. */
+
+/* FIXME: carlton/2003-03-13: This is an unfortunate situation. I
+ don't mind the Java prefix so much: different languages have
+ different demangling requirements, so it's only natural that we
+ need to keep language data around in our demangling cache. But
+ it's not good that the minimal symbol has the wrong demangled name.
+ Unfortunately, I can't think of any easy solution to that
+ problem. */
+
+#define JAVA_PREFIX "##JAVA$$"
+#define JAVA_PREFIX_LEN 8
void
symbol_set_names (struct general_symbol_info *gsymbol,
- const char *name, int len, struct objfile *objfile)
+ const char *linkage_name, int len, struct objfile *objfile)
{
char **slot;
- const char *tmpname;
+ /* A 0-terminated copy of the linkage name. */
+ const char *linkage_name_copy;
+ /* A copy of the linkage name that might have a special Java prefix
+ added to it, for use when looking names up in the hash table. */
+ const char *lookup_name;
+ /* The length of lookup_name. */
+ int lookup_len;
if (objfile->demangled_names_hash == NULL)
create_demangled_names_hash (objfile);
- /* The stabs reader generally provides names that are not NULL-terminated;
- most of the other readers don't do this, so we can just use the given
- copy. */
- if (name[len] != 0)
+ /* The stabs reader generally provides names that are not
+ NUL-terminated; most of the other readers don't do this, so we
+ can just use the given copy, unless we're in the Java case. */
+ if (gsymbol->language == language_java)
+ {
+ char *alloc_name;
+ lookup_len = len + JAVA_PREFIX_LEN;
+
+ alloc_name = alloca (lookup_len + 1);
+ memcpy (alloc_name, JAVA_PREFIX, JAVA_PREFIX_LEN);
+ memcpy (alloc_name + JAVA_PREFIX_LEN, linkage_name, len);
+ alloc_name[lookup_len] = '\0';
+
+ lookup_name = alloc_name;
+ linkage_name_copy = alloc_name + JAVA_PREFIX_LEN;
+ }
+ else if (linkage_name[len] != '\0')
{
- char *alloc_name = alloca (len + 1);
- memcpy (alloc_name, name, len);
- alloc_name[len] = 0;
- tmpname = alloc_name;
+ char *alloc_name;
+ lookup_len = len;
+
+ alloc_name = alloca (lookup_len + 1);
+ memcpy (alloc_name, linkage_name, len);
+ alloc_name[lookup_len] = '\0';
+
+ lookup_name = alloc_name;
+ linkage_name_copy = alloc_name;
}
else
- tmpname = name;
+ {
+ lookup_len = len;
+ lookup_name = linkage_name;
+ linkage_name_copy = linkage_name;
+ }
- slot = (char **) htab_find_slot (objfile->demangled_names_hash, tmpname, INSERT);
+ slot = (char **) htab_find_slot (objfile->demangled_names_hash,
+ lookup_name, INSERT);
/* If this name is not in the hash table, add it. */
if (*slot == NULL)
{
- char *demangled_name = symbol_find_demangled_name (gsymbol, tmpname);
+ char *demangled_name = symbol_find_demangled_name (gsymbol,
+ linkage_name_copy);
int demangled_len = demangled_name ? strlen (demangled_name) : 0;
/* If there is a demangled name, place it right after the mangled name.
Otherwise, just place a second zero byte after the end of the mangled
name. */
*slot = obstack_alloc (&objfile->symbol_obstack,
- len + demangled_len + 2);
- memcpy (*slot, tmpname, len + 1);
- if (demangled_name)
+ lookup_len + demangled_len + 2);
+ memcpy (*slot, lookup_name, lookup_len + 1);
+ if (demangled_name != NULL)
{
- memcpy (*slot + len + 1, demangled_name, demangled_len + 1);
+ memcpy (*slot + lookup_len + 1, demangled_name, demangled_len + 1);
xfree (demangled_name);
}
else
- (*slot)[len + 1] = 0;
+ (*slot)[lookup_len + 1] = '\0';
}
- gsymbol->name = *slot;
- if ((*slot)[len + 1])
+ gsymbol->name = *slot + lookup_len - len;
+ if ((*slot)[lookup_len + 1] != '\0')
gsymbol->language_specific.cplus_specific.demangled_name
- = &(*slot)[len + 1];
+ = &(*slot)[lookup_len + 1];
else
gsymbol->language_specific.cplus_specific.demangled_name = NULL;
}
#define SYMTAB_H 1
/* Opaque declarations. */
-
+struct ui_file;
+struct frame_info;
+struct symbol;
struct obstack;
struct objfile;
struct block;
extern void symbol_init_demangled_name (struct general_symbol_info *symbol,
struct obstack *obstack);
-#define SYMBOL_SET_NAMES(symbol,name,len,objfile) \
- symbol_set_names (&(symbol)->ginfo, name, len, objfile)
+#define SYMBOL_SET_NAMES(symbol,linkage_name,len,objfile) \
+ symbol_set_names (&(symbol)->ginfo, linkage_name, len, objfile)
extern void symbol_set_names (struct general_symbol_info *symbol,
- const char *name, int len,
+ const char *linkage_name, int len,
struct objfile *objfile);
/* Now come lots of name accessor macros. Short version as to when to
void maintenance_print_objfiles (char *, int);
+void maintenance_list_symtabs (char *, int);
+
+void maintenance_list_psymtabs (char *, int);
+
void maintenance_check_symtabs (char *, int);
/* maint.c */
#if !defined (TARGET_H)
#define TARGET_H
+struct objfile;
+struct ui_file;
+struct mem_attrib;
+
/* This include file defines the interface between the main part
of the debugger, and the part which is target-specific, or
specific to the communications interface between us and the
+2003-04-16 Kevin Buettner <kevinb@redhat.com>
+
+ * gdb.base/args.exp: Invoke gdb_load for simulator targets.
+
+2003-04-16 Elena Zannoni <ezannoni@redhat.com>
+
+ * gdb.base/completion.exp: Make 'info func mark' complete on 'info
+ func marke' instead. Update test name.
+
+2003-04-15 David Carlton <carlton@math.stanford.edu>
+
+ * gdb.c++/maint.exp: New file.
+
+2003-04-14 Elena Zannoni <ezannoni@redhat.com>
+
+ * gdb.threads/schedlock.c: Change type of thread function argument
+ to long, to avoid warnings on 64-bit platforms.
+
+2003-04-14 Elena Zannoni <ezannoni@redhat.com>
+
+ * gdb.base/attach.exp: Add new message from ptrace in case of
+ attaching to nonexistent process.
+
+2003-04-11 Jim Blandy <jimb@redhat.com>
+
+ * gdb.c++/derivation.exp, gdb.c++/overload.exp,
+ gdb.c++/userdef.cc: Place comments on the lines to which the
+ marker function might return.
+ * gdb.c++/derivation.exp, gdb.c++/overload.exp,
+ gdb.c++/userdef.exp: Look for those comments to check that we've
+ returned to the right place, instead of checking line numbers.
+
+2003-04-11 Elena Zannoni <ezannoni@redhat.com>
+
+ * gdb.threads/pthreads.exp (test_startup): When setting a breakpoint
+ match on sourcefile name, instead of directory name.
+
+2003-04-10 Elena Zannoni <ezannoni@redhat.com>
+
+ * gdb.base/completion.exp: Use string_to_regexp to match the
+ working directory name.
+
+2003-04-09 Jim Blandy <jimb@redhat.com>
+
+ * gdb.c++/derivation.exp, gdb.c++/overload.exp,
+ gdb.c++/userdef.exp: If GDB fails to restore the selected frame
+ after an inferior function call, report the failure, but allow the
+ test to continue.
+
2003-04-05 Stephane Carrez <stcarrez@nerim.fr>
* gdb.base/break.exp: marker4() is defined at line 46 when compiled
return;
}
+# No loading needs to be done when the target is `exec'. Some targets
+# require that the program be loaded, however.
+proc args_load {} {
+ global binfile
+ if [target_info exists is_simulator] {
+ gdb_load ${binfile}
+ }
+}
+
set testfile "args"
set srcfile ${testfile}.c
set binfile ${objdir}/${subdir}/${testfile}
gdb_exit
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
+args_load
gdb_test "run" \
"Starting program.*args(\\.exe)? 1 3.*3\r\n.*args\r\n1\r\n3.*Program exited normally." \
"correct args printed"
gdb_exit
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
+args_load
gdb_test "run" \
"Starting program.*args(\\.exe)? 1 \\\\'\\\\' 3.*4\r\n.*args\r\n1\r\n''\r\n3.*Program exited normally." \
"correct args printed, one empty"
gdb_exit
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
+args_load
gdb_test "run" \
"Starting program.*args(\\.exe)? 1 \\\\'\\\\' \\\\'\\\\' 3.*5\r\n.*args\r\n1\r\n''\r\n''\r\n3.*Program exited normally." \
"correct args printed, two empty"
}
-re "Attaching to.*, process 0.*denied.*$gdb_prompt $"\
{pass "attach to nonexistent process is prohibited"}
+ -re "Attaching to.*, process 0.*Operation not permitted.*$gdb_prompt $"\
+ {pass "attach to nonexistent process is prohibited"}
-re "Attaching to.*, process .*couldn't open /proc file.*$gdb_prompt $"\
{
# Response expected from /proc-based systems.
set fullsrcdir [pwd]
cd ${mydir}
-gdb_test "cd ${fullsrcdir}" "Working directory ${fullsrcdir}.*" "cd to \${srcdir}"
+# If the directory name contains a '+' we must escape it, adding a backslash.
+# If not, the test below will fail because it will interpret the '+' as a
+# regexp operator. We use string_to_regexp for this purpose.
+
+gdb_test "cd ${fullsrcdir}" \
+ "Working directory [string_to_regexp ${fullsrcdir}].*" \
+ "cd to \${srcdir}"
+
send_gdb "file ./gdb.base/compl\t"
sleep 1
gdb_expect {
timeout { fail "(timeout) complete 'file ./gdb.base/compl'" }
}
-send_gdb "info func mark\t"
+send_gdb "info func marke\t"
sleep 1
gdb_expect {
- -re "^info func mark.*er$"\
+ -re "^info func marke.*r$"\
{
send_gdb "\t\t"
sleep 3
{ send_gdb "\n"
gdb_expect {
-re "All functions matching regular expression \"marker\":.*File.*break.c:\r\nint marker1\\((void|)\\);\r\nint marker2\\(int\\).*marker3\\(char.*char.*\\).*marker4\\(long int\\);.*$gdb_prompt $"\
- { pass "complete 'info func mar'"}
- -re ".*$gdb_prompt $" { fail "complete 'info func mar'"}
- timeout {fail "(timeout) complete 'info func mar'"}
+ { pass "complete 'info func marke'"}
+ -re ".*$gdb_prompt $" { fail "complete 'info func marke'"}
+ timeout {fail "(timeout) complete 'info func marke'"}
}
}
- -re ".*$gdb_prompt $" { fail "complete 'info func mar'"}
- timeout {fail "(timeout) complete 'info func mar'"}
+ -re ".*$gdb_prompt $" { fail "complete 'info func marke'"}
+ timeout {fail "(timeout) complete 'info func marke'"}
}
}
- -re ".*$gdb_prompt $" { fail "complete 'info func mar'" }
- timeout { fail "(timeout) complete 'info func mar'" }
+ -re ".*$gdb_prompt $" { fail "complete 'info func marke'" }
+ timeout { fail "(timeout) complete 'info func marke'" }
}
#endif
- marker1();
+ marker1(); // marker1-returns-here
- a_instance.a = 20;
+ a_instance.a = 20; // marker1-returns-here
a_instance.aa = 21;
b_instance.b = 22;
b_instance.bb = 23;
timeout { fail "(timeout) print value of g_instance.afoo()" }
}
+
+# If GDB fails to restore the selected frame properly after the
+# inferior function call above (see GDB PR 1155 for an explanation of
+# why this might happen), all the subsequent tests will fail. We
+# should detect report that failure, but let the marker call finish so
+# that the rest of the tests can run undisturbed.
+gdb_test_multiple "frame" "re-selected 'main' frame after inferior call" {
+ -re "#0 marker1.*$gdb_prompt $" {
+ setup_kfail "gdb/1155" s390-*-linux-gnu
+ fail "re-selected 'main' frame after inferior call"
+ gdb_test "finish" ".*main.*at .*derivation.cc:.*// marker1-returns-here.*" \
+ "finish call to marker1"
+ }
+ -re "#1 ($hex in )?main.*$gdb_prompt $" {
+ pass "re-selected 'main' frame after inferior call"
+ }
+}
+
send_gdb "print g_instance.bfoo()\n"
gdb_expect {
-re ".\[0-9\]* = 2.*$gdb_prompt $" {
--- /dev/null
+# Copyright 2003 Free Software Foundation Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Please email any bugs, comments, and/or additions to this file to:
+# bug-gdb@prep.ai.mit.edu
+
+
+# This file tests C++-specific maintenance commands and help on those.
+
+# Currently, no source file is used.
+
+if $tracelevel then {
+ strace $tracelevel
+ }
+
+# Test the help messages.
+
+proc test_help {} {
+ gdb_test "help maintenance cplus" "C\\+\\+ maintenance commands.\r\n\r\nList of maintenance cplus subcommands:\r\n\r\nmaintenance cplus first_component -- Print the first class/namespace component of NAME\r\n\r\nType \"help maintenance cplus\" followed by maintenance cplus subcommand name for full documentation.\r\nCommand name abbreviations are allowed if unambiguous."
+
+ gdb_test "help maint cp" "C\\+\\+ maintenance commands.\r\n\r\nList of maintenance cplus subcommands:\r\n\r\nmaintenance cplus first_component -- Print the first class/namespace component of NAME\r\n\r\nType \"help maintenance cplus\" followed by maintenance cplus subcommand name for full documentation.\r\nCommand name abbreviations are allowed if unambiguous."
+
+ gdb_test "maint cp" "\"maintenance cplus\" must be followed by the name of a command.\r\nList of maintenance cplus subcommands:\r\n\r\nmaintenance cplus first_component -- Print the first class/namespace component of NAME\r\n\r\nType \"help maintenance cplus\" followed by maintenance cplus subcommand name for full documentation.\r\nCommand name abbreviations are allowed if unambiguous."
+
+ gdb_test "help maint cp first_component" "Print the first class/namespace component of NAME."
+}
+
+# This is used when NAME should contain only a single component. Be
+# careful to make sure that parentheses get escaped properly.
+proc test_single_component {name} {
+ set matchname [string_to_regexp "$name"]
+ gdb_test "maint cp first_component $name" "$matchname"
+}
+
+proc test_first_component {} {
+ test_single_component "foo"
+ test_single_component "operator<<"
+ test_single_component "operator>>"
+ test_single_component "operator ->"
+ test_single_component "operator()"
+ test_single_component "operator>"
+ test_single_component "operator<"
+ test_single_component "operator ->"
+ test_single_component "operator ->"
+
+ test_single_component "foo()"
+ test_single_component "foo(int)"
+ test_single_component "foo(X::Y)"
+ test_single_component "foo(X::Y, A::B)"
+ test_single_component "foo(std::basic_streambuf<wchar_t,std::char_traits<wchar_t> >)"
+ test_single_component "operator>(X::Y)"
+
+ gdb_test "maint cp first_component foo::bar" "foo"
+ gdb_test "maint cp first_component foo::bar::baz" "foo"
+ gdb_test "maint cp first_component C<A>::bar" "C<A>"
+ gdb_test "maint cp first_component C<std::basic_streambuf<wchar_t,std::char_traits<wchar_t> > >::bar" "C<std::basic_streambuf<wchar_t,std::char_traits<wchar_t> > >"
+}
+
+gdb_exit
+gdb_start
+
+test_help
+test_first_component
+
+gdb_exit
+return 0
// Verify that intToChar should work:
intToChar(1);
- marker1();
- return 0;
+ marker1(); // marker1-returns-here
+ return 0; // marker1-returns-here
}
foo::foo (int i) { ifoo = i; ccpfoo = NULL; }
}
+# If GDB fails to restore the selected frame properly after the
+# inferior function call above (see GDB PR 1155 for an explanation of
+# why this might happen), all the subsequent tests will fail. We
+# should detect and report that failure, but let the marker call
+# finish so that the rest of the tests can run undisturbed.
+gdb_test_multiple "frame" "re-selected 'main' frame after inferior call" {
+ -re "#0 marker1.*$gdb_prompt $" {
+ setup_kfail "gdb/1155" s390-*-linux-gnu
+ fail "re-selected 'main' frame after inferior call"
+ gdb_test "finish" ".*main.*at .*overload.cc:.*// marker1-returns-here.*" \
+ "finish call to marker1"
+ }
+ -re "#1 ($hex in )?main.*$gdb_prompt $" {
+ pass "re-selected 'main' frame after inferior call"
+ }
+}
+
+
send_gdb "print foo_instance1.overloadargs(1, 2)\n"
gdb_expect {
-re ".\[0-9\]* = 2\r\n$gdb_prompt $" {
A1 three(0,0);
int val;
- marker1();
- cout << one;
+ marker1(); // marker1-returns-here
+ cout << one; // marker1-returns-here
cout << two;
three = one + two;
cout << "+ " << three;
gdb_test "print one + two" "\\\$\[0-9\]* = {x = 6, y = 8}"
+# If GDB fails to restore the selected frame properly after the
+# inferior function call above (see GDB PR 1155 for an explanation of
+# why this might happen), all the subsequent tests will fail. We
+# should detect report that failure, but let the marker call finish so
+# that the rest of the tests can run undisturbed.
+gdb_test_multiple "frame" "re-selected 'main' frame after inferior call" {
+ -re "#0 marker1.*$gdb_prompt $" {
+ setup_kfail "gdb/1155" s390-*-linux-gnu
+ fail "re-selected 'main' frame after inferior call"
+ gdb_test "finish" ".*main.*at .*userdef.cc:.*// marker1-returns-here.*" \
+ "finish call to marker1"
+ }
+ -re "#1 ($hex in )?main.*$gdb_prompt $" {
+ pass "re-selected 'main' frame after inferior call"
+ }
+}
+
gdb_test "print one - two" "\\\$\[0-9\]* = {x = -2, y = -2}"
gdb_test "print one * two" "\\\$\[0-9\]* = {x = 8, y = 15}"
+2003-04-08 Andrew Cagney <cagney@redhat.com>
+
+ * gdb792.exp: Skip when C++.
+
2003-02-23 Stephane Carrez <stcarrez@nerim.fr>
* mi-syn-frame.exp: Don't run this test when gdb,nosignals is set.
# test gdb/792
#
+if { [skip_cplus_tests] } { continue }
+
load_lib mi-support.exp
set MIFLAGS "-i=mi"
set main_id $expect_out(1,string)
# Check that we can continue and create the first thread.
- gdb_test "break thread1" "Breakpoint .* file .*$srcdir.*"
+ gdb_test "break thread1" "Breakpoint .* file .*$srcfile.*"
gdb_test "continue" \
"Continuing.*Breakpoint .*, thread1 \\(arg=0xfeedface\\).*at.*$srcfile.*" \
"Continue to creation of first thread"
# Check that we can continue and create the second thread,
# ignoring the first thread for the moment.
- gdb_test "break thread2" "Breakpoint .* file .*$srcdir.*"
+ gdb_test "break thread2" "Breakpoint .* file .*$srcfile.*"
gdb_test "continue" \
"Continuing.*Breakpoint .*, thread2 \\(arg=0xdeadbeef\\).*at.*$srcfile.*" \
"Continue to creation of second thread"
int res;
pthread_t threads[NUM];
void *thread_result;
- int i;
+ long i;
for (i = 0; i < NUM; i++)
{
args[i] = 1;
- res = pthread_create(&threads[i], NULL, thread_function, (void *)i);
+ res = pthread_create(&threads[i],
+ NULL,
+ thread_function,
+ (void *) i);
}
/* schedlock.exp: last thread start. */
}
void *thread_function(void *arg) {
- int my_number = (int) arg;
+ int my_number = (long) arg;
int *myp = &args[my_number];
/* Don't run forever. Run just short of it :) */
static struct target_ops *target_beneath;
/* Pointer to the next function on the objfile event chain. */
-static void (*target_new_objfile_chain) (struct objfile *objfile);
+static void (*target_new_objfile_chain) (struct objfile * objfile);
/* Non-zero if we're using this module's target vector. */
static int using_thread_db;
static td_err_e (*td_init_p) (void);
-static td_err_e (*td_ta_new_p) (struct ps_prochandle *ps, td_thragent_t **ta);
+static td_err_e (*td_ta_new_p) (struct ps_prochandle * ps,
+ td_thragent_t **ta);
static td_err_e (*td_ta_map_id2thr_p) (const td_thragent_t *ta, thread_t pt,
td_thrhandle_t *__th);
-static td_err_e (*td_ta_map_lwp2thr_p) (const td_thragent_t *ta, lwpid_t lwpid,
- td_thrhandle_t *th);
+static td_err_e (*td_ta_map_lwp2thr_p) (const td_thragent_t *ta,
+ lwpid_t lwpid, td_thrhandle_t *th);
static td_err_e (*td_ta_thr_iter_p) (const td_thragent_t *ta,
- td_thr_iter_f *callback,
- void *cbdata_p, td_thr_state_e state,
- int ti_pri, sigset_t *ti_sigmask_p,
+ td_thr_iter_f *callback, void *cbdata_p,
+ td_thr_state_e state, int ti_pri,
+ sigset_t *ti_sigmask_p,
unsigned int ti_user_flags);
static td_err_e (*td_ta_event_addr_p) (const td_thragent_t *ta,
td_event_e event, td_notify_t *ptr);
const gdb_prfpregset_t *fpregs);
static td_err_e (*td_thr_setgregs_p) (const td_thrhandle_t *th,
prgregset_t gregs);
-static td_err_e (*td_thr_event_enable_p) (const td_thrhandle_t *th, int event);
+static td_err_e (*td_thr_event_enable_p) (const td_thrhandle_t *th,
+ int event);
static td_err_e (*td_thr_tls_get_addr_p) (const td_thrhandle_t *th,
- void *map_address,
- size_t offset,
- void **address);
+ void *map_address,
+ size_t offset, void **address);
/* Location of the thread creation event breakpoint. The code at this
location in the child process will be called by the pthread library
struct private_thread_info
{
/* Cached thread state. */
- unsigned int th_valid : 1;
- unsigned int ti_valid : 1;
+ unsigned int th_valid:1;
+ unsigned int ti_valid:1;
td_thrhandle_t th;
td_thrinfo_t ti;
err = td_thr_get_info_p (thp, &ti);
if (err != TD_OK)
- error ("thread_get_info_callback: cannot get thread info: %s",
+ error ("thread_get_info_callback: cannot get thread info: %s",
thread_db_err_str (err));
/* Fill the cache. */
{
if (fatal)
error ("Cannot find thread %ld: %s",
- (long) GET_THREAD (thread_info->ptid), thread_db_err_str (err));
+ (long) GET_THREAD (thread_info->ptid),
+ thread_db_err_str (err));
}
else
thread_info->private->th_valid = 1;
if (thread_info->private->ti_valid)
return &thread_info->private->ti;
- if (! thread_info->private->th_valid)
+ if (!thread_info->private->th_valid)
thread_db_map_id2thr (thread_info, 1);
- err = td_thr_get_info_p (&thread_info->private->th, &thread_info->private->ti);
+ err =
+ td_thr_get_info_p (&thread_info->private->th, &thread_info->private->ti);
if (err != TD_OK)
- error ("thread_db_get_info: cannot get thread info: %s",
+ error ("thread_db_get_info: cannot get thread info: %s",
thread_db_err_str (err));
thread_info->private->ti_valid = 1;
handle = dlopen (LIBTHREAD_DB_SO, RTLD_NOW);
if (handle == NULL)
{
- fprintf_filtered (gdb_stderr, "\n\ndlopen failed on '%s' - %s\n",
+ fprintf_filtered (gdb_stderr, "\n\ndlopen failed on '%s' - %s\n",
LIBTHREAD_DB_SO, dlerror ());
- fprintf_filtered (gdb_stderr,
+ fprintf_filtered (gdb_stderr,
"GDB will not be able to debug pthreads.\n\n");
return 0;
}
break;
}
- quit:
+quit:
if (target_new_objfile_chain)
target_new_objfile_chain (objfile);
}
/* ...and perform the remaining initialization steps. */
enable_thread_event_reporting ();
- thread_db_find_new_threads();
+ thread_db_find_new_threads ();
}
static void
err = td_thr_get_info_p (msg.th_p, &ti);
if (err != TD_OK)
- error ("check_event: cannot get thread info: %s",
+ error ("check_event: cannot get thread info: %s",
thread_db_err_str (err));
ptid = BUILD_THREAD (ti.ti_tid, GET_PID (ptid));
static int
thread_db_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write,
- struct mem_attrib *attrib,
- struct target_ops *target)
+ struct mem_attrib *attrib, struct target_ops *target)
{
struct cleanup *old_chain = save_inferior_ptid ();
int xfer;
inferior_ptid = lwp_from_thread (inferior_ptid);
}
- xfer = target_beneath->to_xfer_memory (memaddr, myaddr, len, write, attrib, target);
+ xfer =
+ target_beneath->to_xfer_memory (memaddr, myaddr, len, write, attrib,
+ target);
do_cleanups (old_chain);
return xfer;
thread_info = find_thread_pid (ptid);
thread_db_map_id2thr (thread_info, 0);
- if (! thread_info->private->th_valid)
+ if (!thread_info->private->th_valid)
return 0;
err = td_thr_validate_p (&thread_info->private->th);
if (err != TD_OK)
return 0;
- if (! thread_info->private->ti_valid)
+ if (!thread_info->private->ti_valid)
{
- err = td_thr_get_info_p (&thread_info->private->th, &thread_info->private->ti);
+ err =
+ td_thr_get_info_p (&thread_info->private->th,
+ &thread_info->private->ti);
if (err != TD_OK)
return 0;
thread_info->private->ti_valid = 1;
err = td_thr_get_info_p (th_p, &ti);
if (err != TD_OK)
- error ("find_new_threads_callback: cannot get thread info: %s",
+ error ("find_new_threads_callback: cannot get thread info: %s",
thread_db_err_str (err));
if (ti.ti_state == TD_THR_UNKNOWN || ti.ti_state == TD_THR_ZOMBIE)
thread_info = find_thread_pid (ptid);
thread_db_map_id2thr (thread_info, 0);
- if (! thread_info->private->th_valid)
+ if (!thread_info->private->th_valid)
{
- snprintf (buf, sizeof (buf), "Thread %ld (Missing)", GET_THREAD (ptid));
+ snprintf (buf, sizeof (buf), "Thread %ld (Missing)",
+ GET_THREAD (ptid));
return buf;
}
else
{
snprintf (buf, sizeof (buf), "Thread %ld (%s)",
- (long) ti_p->ti_tid, thread_db_state_str (ti_p->ti_state));
+ (long) ti_p->ti_tid,
+ thread_db_state_str (ti_p->ti_state));
}
return buf;
static CORE_ADDR
thread_db_get_thread_local_address (ptid_t ptid, struct objfile *objfile,
- CORE_ADDR offset)
+ CORE_ADDR offset)
{
if (is_thread (ptid))
{
struct thread_info *thread_info;
/* glibc doesn't provide the needed interface. */
- if (! td_thr_tls_get_addr_p)
- error ("Cannot find thread-local variables in this thread library.");
+ if (!td_thr_tls_get_addr_p)
+ error ("Cannot find thread-local variables in this thread library.");
/* Get the address of the link map for this objfile. */
lm = svr4_fetch_objfile_link_map (objfile);
/* Whoops, we couldn't find one. Bail out. */
if (!lm)
- {
- if (objfile_is_library)
- error ("Cannot find shared library `%s' link_map in dynamic"
+ {
+ if (objfile_is_library)
+ error ("Cannot find shared library `%s' link_map in dynamic"
" linker's module list", objfile->name);
else
- error ("Cannot find executable file `%s' link_map in dynamic"
+ error ("Cannot find executable file `%s' link_map in dynamic"
" linker's module list", objfile->name);
}
#ifdef THREAD_DB_HAS_TD_NOTALLOC
/* The memory hasn't been allocated, yet. */
if (err == TD_NOTALLOC)
- {
- /* Now, if libthread_db provided the initialization image's
- address, we *could* try to build a non-lvalue value from
- the initialization image. */
- if (objfile_is_library)
- error ("The inferior has not yet allocated storage for"
- " thread-local variables in\n"
- "the shared library `%s'\n"
- "for the thread %ld",
+ {
+ /* Now, if libthread_db provided the initialization image's
+ address, we *could* try to build a non-lvalue value from
+ the initialization image. */
+ if (objfile_is_library)
+ error ("The inferior has not yet allocated storage for"
+ " thread-local variables in\n"
+ "the shared library `%s'\n"
+ "for the thread %ld",
objfile->name, (long) GET_THREAD (ptid));
- else
- error ("The inferior has not yet allocated storage for"
- " thread-local variables in\n"
- "the executable `%s'\n"
- "for the thread %ld",
+ else
+ error ("The inferior has not yet allocated storage for"
+ " thread-local variables in\n"
+ "the executable `%s'\n"
+ "for the thread %ld",
objfile->name, (long) GET_THREAD (ptid));
}
#endif
error ("Cannot find thread-local storage for thread %ld, "
"shared library %s:\n%s",
(long) GET_THREAD (ptid),
- objfile->name,
- thread_db_err_str (err));
+ objfile->name, thread_db_err_str (err));
else
error ("Cannot find thread-local storage for thread %ld, "
"executable file %s:\n%s",
(long) GET_THREAD (ptid),
- objfile->name,
- thread_db_err_str (err));
+ objfile->name, thread_db_err_str (err));
}
/* Cast assuming host == target. Joy. */
}
if (target_beneath->to_get_thread_local_address)
- return target_beneath->to_get_thread_local_address (ptid, objfile, offset);
+ return target_beneath->to_get_thread_local_address (ptid, objfile,
+ offset);
error ("Cannot find thread-local values on this target.");
}
void
load_infrun_state (ptid_t ptid,
CORE_ADDR *prev_pc,
- CORE_ADDR *prev_func_start,
char **prev_func_name,
int *trap_expected,
struct breakpoint **step_resume_breakpoint,
return;
*prev_pc = tp->prev_pc;
- *prev_func_start = tp->prev_func_start;
*prev_func_name = tp->prev_func_name;
*trap_expected = tp->trap_expected;
*step_resume_breakpoint = tp->step_resume_breakpoint;
void
save_infrun_state (ptid_t ptid,
CORE_ADDR prev_pc,
- CORE_ADDR prev_func_start,
char *prev_func_name,
int trap_expected,
struct breakpoint *step_resume_breakpoint,
return;
tp->prev_pc = prev_pc;
- tp->prev_func_start = prev_func_start;
tp->prev_func_name = prev_func_name;
tp->trap_expected = trap_expected;
tp->step_resume_breakpoint = step_resume_breakpoint;
#ifndef TYPEPRINT_H
#define TYPEPRINT_H
+struct ui_file;
+
void print_type_scalar (struct type * type, LONGEST, struct ui_file *);
void c_type_print_varspec_suffix (struct type *, struct ui_file *, int,
{
void *val;
+ /* See libiberty/xmalloc.c. This function need's to match that's
+ semantics. It never returns NULL. */
if (size == 0)
- {
- val = NULL;
- }
- else
- {
- val = mmalloc (md, size);
- if (val == NULL)
- nomem (size);
- }
+ size = 1;
+
+ val = mmalloc (md, size);
+ if (val == NULL)
+ nomem (size);
+
return (val);
}
{
void *val;
+ /* See libiberty/xmalloc.c. This function need's to match that's
+ semantics. It never returns NULL. */
if (size == 0)
- {
- if (ptr != NULL)
- mfree (md, ptr);
- val = NULL;
- }
+ size = 1;
+
+ if (ptr != NULL)
+ val = mrealloc (md, ptr, size);
else
- {
- if (ptr != NULL)
- {
- val = mrealloc (md, ptr, size);
- }
- else
- {
- val = mmalloc (md, size);
- }
- if (val == NULL)
- {
- nomem (size);
- }
- }
+ val = mmalloc (md, size);
+ if (val == NULL)
+ nomem (size);
+
return (val);
}
xmcalloc (void *md, size_t number, size_t size)
{
void *mem;
+
+ /* See libiberty/xmalloc.c. This function need's to match that's
+ semantics. It never returns NULL. */
if (number == 0 || size == 0)
- mem = NULL;
- else
{
- mem = mcalloc (md, number, size);
- if (mem == NULL)
- nomem (number * size);
+ number = 1;
+ size = 1;
}
+
+ mem = mcalloc (md, number, size);
+ if (mem == NULL)
+ nomem (number * size);
+
return mem;
}
/* Print a host address. */
void
-gdb_print_host_address (void *addr, struct ui_file *stream)
+gdb_print_host_address (const void *addr, struct ui_file *stream)
{
/* We could use the %p conversion specifier to fprintf if we had any
set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, v850_frame_init_saved_regs);
set_gdbarch_deprecated_init_extra_frame_info (gdbarch, v850_init_extra_frame_info);
set_gdbarch_deprecated_frame_chain (gdbarch, v850_frame_chain);
- set_gdbarch_saved_pc_after_call (gdbarch, v850_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, v850_saved_pc_after_call);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, v850_frame_saved_pc);
set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue);
extern unsigned int print_max; /* Max # of chars for strings/vectors */
+/* Flag to low-level print routines that this value is being printed
+ in an epoch window. We'd like to pass this as a parameter, but
+ every routine would need to take it. Perhaps we can encapsulate
+ this in the I/O stream once we have GNU stdio. */
+extern int inspect_it;
+
/* Print repeat counts if there are more than this many repetitions of an
element in an array. Referenced by the low level language dependent
print routines. */
#if !defined (VALUE_H)
#define VALUE_H 1
+struct ui_file;
+struct expression;
+struct symbol;
+struct type;
struct regcache;
struct block;
val = allocate_value (valtype);
CHECK_TYPEDEF (valtype);
- EXTRACT_RETURN_VALUE (valtype, retbuf, VALUE_CONTENTS_RAW (val));
+ /* If the function returns void, don't bother fetching the return value. */
+ if (TYPE_CODE (valtype) != TYPE_CODE_VOID)
+ EXTRACT_RETURN_VALUE (valtype, retbuf, VALUE_CONTENTS_RAW (val));
return val;
}
static gdbarch_register_virtual_type_ftype vax_register_virtual_type;
static gdbarch_skip_prologue_ftype vax_skip_prologue;
-static gdbarch_saved_pc_after_call_ftype vax_saved_pc_after_call;
static gdbarch_frame_num_args_ftype vax_frame_num_args;
static gdbarch_deprecated_frame_chain_ftype vax_frame_chain;
static gdbarch_frame_args_address_ftype vax_frame_args_address;
/* Frame and stack info */
set_gdbarch_skip_prologue (gdbarch, vax_skip_prologue);
- set_gdbarch_saved_pc_after_call (gdbarch, vax_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, vax_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, vax_frame_num_args);
set_gdbarch_frameless_function_invocation (gdbarch,
-2003-04-06-cvs
+2003-04-19-cvs
return x86_64_dwarf2gdb_regno_map[dw_reg];
}
-/* This is the variable that is set with "set disassembly-flavour", and
- its legitimate values. */
-static const char att_flavour[] = "att";
-static const char intel_flavour[] = "intel";
-static const char *valid_flavours[] = {
- att_flavour,
- intel_flavour,
- NULL
-};
-static const char *disassembly_flavour = att_flavour;
-
/* Push the return address (pointing to the call dummy) onto the stack
and return the new value for the stack pointer. */
floating point format used by the FPU. This is probably
not exactly how it would happen on the target itself, but
it is the best we can do. */
- val = extract_floating (valbuf, TYPE_LENGTH (type));
+ val = deprecated_extract_floating (valbuf, TYPE_LENGTH (type));
floatformat_from_doublest (&floatformat_i387_ext, &val, buf);
regcache_cooked_write_part (regcache, FP0_REGNUM,
0, FPU_REG_RAW_SIZE, buf);
}
\f
-
-/* We have two flavours of disassembly. The machinery on this page
- deals with switching between those. */
-
-static int
-gdb_print_insn_x86_64 (bfd_vma memaddr, disassemble_info * info)
-{
- if (disassembly_flavour == att_flavour)
- return print_insn_i386_att (memaddr, info);
- else if (disassembly_flavour == intel_flavour)
- return print_insn_i386_intel (memaddr, info);
- /* Never reached -- disassembly_flavour is always either att_flavour
- or intel_flavour. */
- internal_error (__FILE__, __LINE__, "failed internal consistency check");
-}
-\f
-
/* Store the address of the place in which to copy the structure the
subroutine will return. This is called from call_function. */
void
return pc;
}
-/* Sequence of bytes for breakpoint instruction. */
-static const unsigned char *
-x86_64_breakpoint_from_pc (CORE_ADDR *pc, int *lenptr)
-{
- static unsigned char breakpoint[] = { 0xcc };
- *lenptr = 1;
- return breakpoint;
-}
-
static void
x86_64_save_dummy_frame_tos (CORE_ADDR sp)
{
/* FIXME: kettenis/20021026: These two are GNU/Linux-specific and
should be moved elsewhere. */
set_gdbarch_deprecated_frame_saved_pc (gdbarch, x86_64_linux_frame_saved_pc);
- set_gdbarch_saved_pc_after_call (gdbarch, x86_64_linux_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, x86_64_linux_saved_pc_after_call);
set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
/* FIXME: kettenis/20021026: This one is GNU/Linux-specific too. */
set_gdbarch_pc_in_sigtramp (gdbarch, x86_64_linux_in_sigtramp);
#ifndef X86_64_TDEP_H
#define X86_64_TDEP_H
+struct gdbarch;
+struct frame_info;
+
#include "i386-tdep.h"
extern int x86_64_num_regs;
const char *x86_64_register_name (int reg_nr);
gdbarch_deprecated_frame_saved_pc_ftype x86_64_linux_frame_saved_pc;
-gdbarch_saved_pc_after_call_ftype x86_64_linux_saved_pc_after_call;
+gdbarch_deprecated_saved_pc_after_call_ftype x86_64_linux_saved_pc_after_call;
gdbarch_pc_in_sigtramp_ftype x86_64_linux_in_sigtramp;
CORE_ADDR x86_64_linux_frame_chain (struct frame_info *fi);
CORE_ADDR x86_64_init_frame_pc (int fromleaf, struct frame_info *fi);
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+struct serial;
+
int xmodem_init_xfer (struct serial *desc);
void send_xmodem_packet (struct serial *desc, unsigned char *packet, int len,
int hashmark);
/* Function: xstormy16_frame_saved_pc
Returns the return address for the selected frame.
- Called by frame_info, frame_chain_valid, and sometimes by
- get_prev_frame.
-*/
+ Called by frame_info, legacy_frame_chain_valid, and sometimes by
+ get_prev_frame. */
static CORE_ADDR
xstormy16_frame_saved_pc (struct frame_info *fi)
xstormy16_frame_init_saved_regs);
set_gdbarch_deprecated_frame_chain (gdbarch, xstormy16_frame_chain);
set_gdbarch_deprecated_get_saved_register (gdbarch, xstormy16_get_saved_register);
- set_gdbarch_saved_pc_after_call (gdbarch, xstormy16_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch, xstormy16_saved_pc_after_call);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, xstormy16_frame_saved_pc);
set_gdbarch_skip_prologue (gdbarch, xstormy16_skip_prologue);
set_gdbarch_deprecated_frame_chain_valid (gdbarch, xstormy16_frame_chain_valid);
+2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+ * sh.h: Replace occurrances of 'Hitachi' with 'Renesas'.
+ * h8300.h: Likewise.
+ * h8500.h: Likewise.
+
2003-03-25 Stan Cox <scox@redhat.com>
Nick Clifton <nickc@redhat.com>
-/* coff information for Hitachi H8/300 and H8/300-H
+/* coff information for Renesas H8/300 and H8/300-H
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2001, 2003 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-/* coff information for Hitachi H8/500
+/* coff information for Renesas H8/500
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2001, 2003 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-/* coff information for Hitachi SH
+/* coff information for Renesas SH
- Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2001, 2003 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
+2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+ * common.h: Replace occurrances of 'Hitachi' with 'Renesas'.
+
2003-04-01 Bob Wilson <bob.wilson@acm.org>
* elf/common.h (EM_XTENSA_OLD): Define.
in "UNIX System V Release 4, Programmers Guide: ANSI C and
Programming Support Tools".
-This file is part of BFD, the Binary File Descriptor library.
+ This file is part of BFD, the Binary File Descriptor library.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* This file is part of ELF support for BFD, and contains the portions
that are common to both the internal and external representations.
For example, ELFMAG0 is the byte 0x7F in both the internal (in-memory)
- and external (in-file) representations. */
+ and external (in-file) representations. */
#ifndef _ELF_COMMON_H
#define _ELF_COMMON_H
-/* Fields in e_ident[] */
+/* Fields in e_ident[]. */
#define EI_MAG0 0 /* File identification byte 0 index */
#define ELFMAG0 0x7F /* Magic number byte 0 */
#define EM_RCE 39 /* Old name for MCore */
#define EM_ARM 40 /* ARM */
#define EM_OLD_ALPHA 41 /* Digital Alpha */
-#define EM_SH 42 /* Hitachi SH */
+#define EM_SH 42 /* Renesas (formerly Hitachi) SH */
#define EM_SPARCV9 43 /* SPARC v9 64-bit */
#define EM_TRICORE 44 /* Siemens Tricore embedded processor */
#define EM_ARC 45 /* ARC Cores */
-#define EM_H8_300 46 /* Hitachi H8/300 */
-#define EM_H8_300H 47 /* Hitachi H8/300H */
-#define EM_H8S 48 /* Hitachi H8S */
-#define EM_H8_500 49 /* Hitachi H8/500 */
+#define EM_H8_300 46 /* Renesas (formerly Hitachi) H8/300 */
+#define EM_H8_300H 47 /* Renesas (formerly Hitachi) H8/300H */
+#define EM_H8S 48 /* Renesas (formerly Hitachi) H8S */
+#define EM_H8_500 49 /* Renesas (formerly Hitachi) H8/500 */
#define EM_IA_64 50 /* Intel IA-64 Processor */
#define EM_MIPS_X 51 /* Stanford MIPS-X */
#define EM_COLDFIRE 52 /* Motorola Coldfire */
+2003-04-07 Michael Snyder <msnyder@redhat.com>
+
+ * h8300.h (ldc/stc): Fix up src/dst swaps.
+
+2003-04-09 J. Grant <jg-binutils@jguk.org>
+
+ * mips.h: Correct comment typo.
+
2003-03-21 Martin Schwidefsky <schwidefsky@de.ibm.com>
* s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val.
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR|DST,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR|DST,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR|DST,E}}, {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}}, {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}}, {{PREFIXLDC,0x6,0x9,B30|RSIND,0x0,E}} EOP,
NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR|DST,E}}, {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
- NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+ NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}}, {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RSIND,0x0,E}} EOP,
SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}}, {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP,
SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{ 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP,
NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR|SRC,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RSIND,E}}, {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDIND,E}}, {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDDEC,E}}, {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR|SRC,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
- NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RSIND,E}}, {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+ NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDIND,E}}, {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDDEC,E}}, {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
unsigned long membership;
};
-/* These are the characters which may appears in the args field of an
+/* These are the characters which may appear in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
+2003-04-16 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * configure.in (funcs, AC_CHECK_FUNCS): Add snprintf and
+ vsnprintf.
+ * snprintf.c, vsnprintf.c: New files.
+ * Makefile.in (CFILES): Add snprintf.c and vsnprintf.c.
+ (CONFIGURED_OFILES): Add snprintf.o and vsnprintf.o.
+ Regenerate dependencies.
+
+ * functions.texi, configure, config.in: Regenerated.
+
+2003-04-15 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * mempcpy.c, stpcpy.c, stpncpy.c: New files.
+ * configure.in (funcs, AC_CHECK_FUNCS): Add mempcpy, stpcpy
+ and stpncpy.
+ * Makefile.in (CFILES): Add mempcpy.c, stpcpy.c and stpncpy.c.
+ (CONFIGURED_OFILES): Add mempcpy.o, stpcpy.o and stpncpy.o.
+ Regenerate dependencies.
+
+ * functions.texi, configure, config.in: Regenerated.
+
+2003-04-15 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * argv.c: Fix comments.
+ * calloc.c: Don't unnecessarily include "libiberty.h".
+ (bzero): Add prototype.
+ * floatformat.c: Include "ansidecl.h", rely on ANSI_PROTOTYPES.
+ * getcwd.c (getcwd): Use standard definition to avoid conflicts
+ with system headers.
+ * hashtab.c (htab_traverse): Delete unused variables.
+ * rename.c: Include "ansidecl.h".
+ (rename): Use standard definition to avoid conflicts with system
+ headers.
+ * strsignal.c: Rely on ANSI_PROTOTYPES.
+ * strstr.c: Check GNUC >= 2, not GNUC == 2.
+ * vfprintf.c: Include "ansidecl.h", rely on ANSI_PROTOTYPES.
+ * vprintf.c: Include "ansidecl.h" earlier, rely on
+ ANSI_PROTOTYPES.
+ * vsprintf.c: Include "ansidecl.h" earlier, rely on
+ ANSI_PROTOTYPES and possibly include <stdarg.h>.
+
+ * Makefile.in: Regenerate dependencies.
+
+2003-04-15 DJ Delorie <dj@redhat.com>
+
+ * maint-tool (deps): Scan for headers in $srcdir also.
+
+2003-04-15 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ PR target/10338
+ PR bootstrap/10198
+ PR bootstrap/10140
+ * getopt.c (exchange, _getopt_initialize): Use mempcpy not
+ __mempcpy.
+ * regex.c (regerror): Likewise.
+
+2003-04-14 Roger Sayle <roger@eyesopen.com>
+
+ * argv.c: Use ANSI_PROTOTYPES instead of __STDC__.
+ * memchr.c: Likewise.
+ * strcasecmp.c: Likewise.
+ * strncasecmp.c: Likewise.
+ * strncmp.c: Likewise.
+ * xatexit.c: Likewise.
+ * xmalloc.c: Likewise.
+
+ * copysign.c: Use traditional function declaration instead of DEFUN.
+ * sigsetmask.c: Likewise.
+
+ * memcmp.c: Both of the above, ANSI_PROTOTYPES and DEFUN.
+ * memset.c: Likewise.
+
+ * memcpy.c: ANSI_PROTOTYPES, DEFUN and prototype bcopy.
+ * memmove.c: Likewise.
+
+2003-04-14 Roger Sayle <roger@eyesopen.com>
+
+ * strdup.c (strdup): Tweak implementation to use memcpy.
+
+2003-04-14 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * configure.in (HAVE_UINTPTR_T): Always define.
+ * configure: Regenerated.
+
2003-03-23 Alexandre Oliva <aoliva@redhat.com>
* Makefile.in (MULTIOSDIR): New macro. Use $(CC) $(LIBCFLAGS)
on the number of elements actually used.
(htab_traverse): Call htab_expand when table is too empty.
-2003-12-03 Jan Hubicka <jh@suse.cz>
-
- * hashtab.c (htab_expand): Compute the size of hashtable based
- on the number of elements actually used.
- (htab_traverse): Call htab_expand when table is too empty.
-
2003-03-11 Carlo Wood <carlo@gnu.org>
* cplus-dem.c (demangle_integral_value): Correction to reflect
2003-02-22 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
Richard Earnshaw <rearnsha@arm.com>
Geoffrey Keating <geoffk@apple.com>
-
+
* configure.in: Check for sys/sysctl.h and sysctl.
* physmem.c: Add support for *bsd and darwin.
* Makefile.in: Generate depedency for physmem.o.
2003-02-21 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+ * configure.in: Check for sys/sysmp.h and sysmp.
+ * physmem.c: Pull upstream copy, add support for irix6.
+
+ * config.in, configure: Regenerated.
+
+2003-02-21 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
* physmem.c (physmem_total, physmem_available): De-ANSI-fy.
* configure.in (AC_CHECK_FUNCS): Add pstat_getstatic and
pstat_getdynamic.
-
+
2003-02-20 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* Makefile.in (CFILES): Add physmem.c.
lrealpath.c \
make-relative-prefix.c \
make-temp-file.c md5.c memchr.c memcmp.c memcpy.c memmove.c \
- memset.c mkstemps.c \
+ mempcpy.c memset.c mkstemps.c \
objalloc.c obstack.c \
partition.c \
pex-djgpp.c pex-mpw.c pex-msdos.c pex-os2.c \
pex-unix.c pex-win32.c \
physmem.c putenv.c \
random.c regex.c rename.c rindex.c \
- safe-ctype.c setenv.c sigsetmask.c sort.c spaces.c \
- splay-tree.c strcasecmp.c strchr.c strdup.c strerror.c \
- strncasecmp.c strncmp.c strrchr.c strsignal.c strstr.c \
- strtod.c strtol.c strtoul.c \
+ safe-ctype.c setenv.c sigsetmask.c snprintf.c sort.c spaces.c \
+ splay-tree.c stpcpy.c stpncpy.c strcasecmp.c strchr.c strdup.c \
+ strerror.c strncasecmp.c strncmp.c strrchr.c strsignal.c \
+ strstr.c strtod.c strtol.c strtoul.c \
ternary.c tmpnam.c \
- vasprintf.c vfork.c vfprintf.c vprintf.c vsprintf.c \
+ vasprintf.c vfork.c vfprintf.c vprintf.c vsnprintf.c vsprintf.c \
waitpid.c \
xatexit.c xexit.c xmalloc.c xmemdup.c xstrdup.c xstrerror.c
ffs.o \
getcwd.o getpagesize.o \
index.o insque.o \
- memchr.o memcmp.o memcpy.o memmove.o memset.o mkstemps.o \
+ memchr.o memcmp.o memcpy.o memmove.o mempcpy.o memset.o mkstemps.o \
pex-djgpp.o pex-mpw.o pex-msdos.o pex-os2.o \
pex-unix.o pex-win32.o \
putenv.o \
random.o rename.o rindex.o \
- setenv.o sigsetmask.o strcasecmp.o strchr.o strdup.o \
- strncasecmp.o strncmp.o strrchr.o strstr.o strtod.o strtol.o \
- strtoul.o \
+ setenv.o sigsetmask.o snprintf.o stpcpy.o stpncpy.o strcasecmp.o \
+ strchr.o strdup.o strncasecmp.o strncmp.o strrchr.o strstr.o \
+ strtod.o strtol.o strtoul.o \
tmpnam.o \
- vasprintf.o vfork.o vfprintf.o vprintf.o vsprintf.o \
+ vasprintf.o vfork.o vfprintf.o vprintf.o vsnprintf.o vsprintf.o \
waitpid.o
# These files are installed if the library has been configured to do so.
basename.o: $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
$(INCDIR)/safe-ctype.h
bsearch.o: config.h $(INCDIR)/ansidecl.h
-calloc.o: $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
+calloc.o: $(INCDIR)/ansidecl.h
choose-temp.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
clock.o: config.h
concat.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
cp-demangle.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/demangle.h \
$(INCDIR)/dyn-string.h $(INCDIR)/getopt.h $(INCDIR)/libiberty.h
cplus-dem.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/demangle.h \
- $(INCDIR)/getopt.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
dyn-string.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/dyn-string.h \
$(INCDIR)/libiberty.h
fdmatch.o: $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
lbasename.o: $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
$(INCDIR)/safe-ctype.h
lrealpath.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
-make-relative-prefix.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
+make-relative-prefix.o: config.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/libiberty.h
make-temp-file.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
md5.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/md5.h
memchr.o: $(INCDIR)/ansidecl.h
memcmp.o: $(INCDIR)/ansidecl.h
memcpy.o: $(INCDIR)/ansidecl.h
memmove.o: $(INCDIR)/ansidecl.h
+mempcpy.o: $(INCDIR)/ansidecl.h
memset.o: $(INCDIR)/ansidecl.h
mkstemps.o: config.h $(INCDIR)/ansidecl.h
objalloc.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/objalloc.h
obstack.o: config.h $(INCDIR)/obstack.h
partition.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
$(INCDIR)/partition.h
-pex-djgpp.o: config.h pex-common.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
-pex-mpw.o: config.h pex-common.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
-pex-msdos.o: config.h pex-common.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
- $(INCDIR)/safe-ctype.h
-pex-os2.o: config.h pex-common.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
-pex-unix.o: config.h pex-common.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
-pex-win32.o: config.h pex-common.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
-physmem.o: config.h $(INCDIR)/libiberty.h
+pex-djgpp.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+ $(srcdir)/pex-common.h
+pex-mpw.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+ $(srcdir)/pex-common.h
+pex-msdos.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+ $(srcdir)/pex-common.h $(INCDIR)/safe-ctype.h
+pex-os2.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+ $(srcdir)/pex-common.h
+pex-unix.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+ $(srcdir)/pex-common.h
+pex-win32.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
+ $(srcdir)/pex-common.h
+physmem.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
putenv.o: config.h $(INCDIR)/ansidecl.h
random.o: $(INCDIR)/ansidecl.h
regex.o: config.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-rename.o: config.h
+rename.o: config.h $(INCDIR)/ansidecl.h
safe-ctype.o: $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
setenv.o: config.h $(INCDIR)/ansidecl.h
sigsetmask.o: $(INCDIR)/ansidecl.h
+snprintf.o: $(INCDIR)/ansidecl.h
sort.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
$(INCDIR)/sort.h
spaces.o: $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
splay-tree.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
$(INCDIR)/splay-tree.h
+stpcpy.o: $(INCDIR)/ansidecl.h
+stpncpy.o: $(INCDIR)/ansidecl.h
strcasecmp.o: $(INCDIR)/ansidecl.h
strchr.o: $(INCDIR)/ansidecl.h
+strdup.o: $(INCDIR)/ansidecl.h
strerror.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
strncasecmp.o: $(INCDIR)/ansidecl.h
strncmp.o: $(INCDIR)/ansidecl.h
$(INCDIR)/ternary.h
vasprintf.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
vfork.o: $(INCDIR)/ansidecl.h
+vfprintf.o: $(INCDIR)/ansidecl.h
vprintf.o: $(INCDIR)/ansidecl.h
+vsnprintf.o: config.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
vsprintf.o: $(INCDIR)/ansidecl.h
waitpid.o: config.h
xatexit.o: $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h
/* Routines imported from standard C runtime libraries. */
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#include <string.h>
#include <stdlib.h>
-#else /* !__STDC__ */
+#else /* !ANSI_PROTOTYPES */
#if !defined _WIN32 || defined __GNUC__
extern char *memcpy (); /* Copy memory region */
extern char *strdup (); /* Duplicate a string */
#endif
-#endif /* __STDC__ */
+#endif /* ANSI_PROTOTYPES */
#ifndef NULL
*/
#include "ansidecl.h"
-#include "libiberty.h"
-
#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
/* For systems with larger pointers than ints, this must be declared. */
PTR malloc PARAMS ((size_t));
+void bzero PARAMS ((PTR, size_t));
PTR
calloc (nelem, elsize)
/* Define if you have the memmove function. */
#undef HAVE_MEMMOVE
+/* Define if you have the mempcpy function. */
+#undef HAVE_MEMPCPY
+
/* Define if you have the memset function. */
#undef HAVE_MEMSET
/* Define if you have the sigsetmask function. */
#undef HAVE_SIGSETMASK
+/* Define if you have the snprintf function. */
+#undef HAVE_SNPRINTF
+
+/* Define if you have the stpcpy function. */
+#undef HAVE_STPCPY
+
+/* Define if you have the stpncpy function. */
+#undef HAVE_STPNCPY
+
/* Define if you have the strcasecmp function. */
#undef HAVE_STRCASECMP
/* Define if you have the vprintf function. */
#undef HAVE_VPRINTF
+/* Define if you have the vsnprintf function. */
+#undef HAVE_VSNPRINTF
+
/* Define if you have the vsprintf function. */
#undef HAVE_VSPRINTF
fi
-
-if test $ac_cv_type_uintptr_t = yes
-then
- cat >> confdefs.h <<\EOF
+# Given the above check, we always have uintptr_t or a fallback
+# definition. So define HAVE_UINTPTR_T in case any imported code
+# relies on it.
+cat >> confdefs.h <<\EOF
#define HAVE_UINTPTR_T 1
EOF
-fi
echo $ac_n "checking for pid_t""... $ac_c" 1>&6
-echo "configure:1659: checking for pid_t" >&5
+echo "configure:1658: checking for pid_t" >&5
if eval "test \"`echo '$''{'ac_cv_type_pid_t'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1664 "configure"
+#line 1663 "configure"
#include "confdefs.h"
#include <sys/types.h>
#if STDC_HEADERS
funcs="$funcs memcmp"
funcs="$funcs memcpy"
funcs="$funcs memmove"
+funcs="$funcs mempcpy"
funcs="$funcs memset"
funcs="$funcs mkstemps"
funcs="$funcs putenv"
funcs="$funcs rename"
funcs="$funcs rindex"
funcs="$funcs setenv"
+funcs="$funcs snprintf"
funcs="$funcs sigsetmask"
+funcs="$funcs stpcpy"
+funcs="$funcs stpncpy"
funcs="$funcs strcasecmp"
funcs="$funcs strchr"
funcs="$funcs strdup"
funcs="$funcs vasprintf"
funcs="$funcs vfprintf"
funcs="$funcs vprintf"
+funcs="$funcs vsnprintf"
funcs="$funcs vsprintf"
funcs="$funcs waitpid"
for ac_func in asprintf atexit basename bcmp bcopy bsearch bzero calloc clock
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1751: checking for $ac_func" >&5
+echo "configure:1755: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1756 "configure"
+#line 1760 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:1779: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1783: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
for ac_func in getcwd getpagesize index insque mkstemps memchr memcmp memcpy
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1806: checking for $ac_func" >&5
+echo "configure:1810: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1811 "configure"
+#line 1815 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:1834: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1838: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
fi
done
- for ac_func in memmove memset putenv random rename rindex sigsetmask
+ for ac_func in memmove mempcpy memset putenv random rename rindex sigsetmask
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1861: checking for $ac_func" >&5
+echo "configure:1865: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1866 "configure"
+#line 1870 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:1889: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1893: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
fi
done
- for ac_func in strcasecmp setenv strchr strdup strncasecmp strrchr strstr
+ for ac_func in strcasecmp setenv stpcpy stpncpy strchr strdup strncasecmp strrchr strstr
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1916: checking for $ac_func" >&5
+echo "configure:1920: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1921 "configure"
+#line 1925 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:1944: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1948: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
for ac_func in strtod strtol strtoul tmpnam vasprintf vfprintf vprintf
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1971: checking for $ac_func" >&5
+echo "configure:1975: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 1976 "configure"
+#line 1980 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:1999: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2003: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
for ac_func in vsprintf waitpid getrusage on_exit psignal strerror strsignal
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2026: checking for $ac_func" >&5
+echo "configure:2030: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2031 "configure"
+#line 2035 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2054: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2058: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
fi
done
- for ac_func in sysconf times sbrk gettimeofday ffs
+ for ac_func in sysconf times sbrk gettimeofday ffs snprintf vsnprintf
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2081: checking for $ac_func" >&5
+echo "configure:2085: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2086 "configure"
+#line 2090 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2109: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2113: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
for ac_func in pstat_getstatic pstat_getdynamic sysmp getsysinfo table sysctl
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2136: checking for $ac_func" >&5
+echo "configure:2140: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2141 "configure"
+#line 2145 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2164: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2168: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
for ac_func in realpath canonicalize_file_name
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2191: checking for $ac_func" >&5
+echo "configure:2195: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2196 "configure"
+#line 2200 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2219: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2223: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
# We haven't set the list of objects yet. Use the standard autoconf
# tests. This will only work if the compiler works.
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:2453: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:2457: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
ac_ext=c
# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
cat > conftest.$ac_ext << EOF
-#line 2464 "configure"
+#line 2468 "configure"
#include "confdefs.h"
main(){return(0);}
EOF
-if { (eval echo configure:2469: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2473: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
ac_cv_prog_cc_works=yes
# If we can't run a trivial program, we are probably using a cross compiler.
if (./conftest; exit) 2>/dev/null; then
{ echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:2495: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:2499: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
cross_compiling=$ac_cv_prog_cc_cross
for ac_func in $funcs
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2502: checking for $ac_func" >&5
+echo "configure:2506: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2507 "configure"
+#line 2511 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2530: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2534: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
-echo "configure:2557: checking whether alloca needs Cray hooks" >&5
+echo "configure:2561: checking whether alloca needs Cray hooks" >&5
if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2562 "configure"
+#line 2566 "configure"
#include "confdefs.h"
#if defined(CRAY) && ! defined(CRAY2)
webecray
if test $ac_cv_os_cray = yes; then
for ac_func in _getb67 GETB67 getb67; do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2587: checking for $ac_func" >&5
+echo "configure:2591: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2592 "configure"
+#line 2596 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2615: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2619: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
fi
echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
-echo "configure:2641: checking stack direction for C alloca" >&5
+echo "configure:2645: checking stack direction for C alloca" >&5
if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
ac_cv_c_stack_direction=0
else
cat > conftest.$ac_ext <<EOF
-#line 2649 "configure"
+#line 2653 "configure"
#include "confdefs.h"
find_stack_direction ()
{
exit (find_stack_direction() < 0);
}
EOF
-if { (eval echo configure:2668: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:2672: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_c_stack_direction=1
else
ac_safe=`echo "vfork.h" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for vfork.h""... $ac_c" 1>&6
-echo "configure:2690: checking for vfork.h" >&5
+echo "configure:2694: checking for vfork.h" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2695 "configure"
+#line 2699 "configure"
#include "confdefs.h"
#include <vfork.h>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2700: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2704: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
fi
echo $ac_n "checking for working vfork""... $ac_c" 1>&6
-echo "configure:2725: checking for working vfork" >&5
+echo "configure:2729: checking for working vfork" >&5
if eval "test \"`echo '$''{'ac_cv_func_vfork_works'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
if test "$cross_compiling" = yes; then
echo $ac_n "checking for vfork""... $ac_c" 1>&6
-echo "configure:2731: checking for vfork" >&5
+echo "configure:2735: checking for vfork" >&5
if eval "test \"`echo '$''{'ac_cv_func_vfork'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2736 "configure"
+#line 2740 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char vfork(); below. */
; return 0; }
EOF
-if { (eval echo configure:2759: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2763: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_vfork=yes"
else
ac_cv_func_vfork_works=$ac_cv_func_vfork
else
cat > conftest.$ac_ext <<EOF
-#line 2781 "configure"
+#line 2785 "configure"
#include "confdefs.h"
/* Thanks to Paul Eggert for this test. */
#include <stdio.h>
}
}
EOF
-if { (eval echo configure:2876: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:2880: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_func_vfork_works=yes
else
for ac_func in _doprnt
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2908: checking for $ac_func" >&5
+echo "configure:2912: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2913 "configure"
+#line 2917 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2936: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2940: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
for ac_func in _doprnt
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2966: checking for $ac_func" >&5
+echo "configure:2970: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2971 "configure"
+#line 2975 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:2994: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2998: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
for v in $vars; do
echo $ac_n "checking for $v""... $ac_c" 1>&6
-echo "configure:3022: checking for $v" >&5
+echo "configure:3026: checking for $v" >&5
if eval "test \"`echo '$''{'libiberty_cv_var_$v'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3027 "configure"
+#line 3031 "configure"
#include "confdefs.h"
int *p;
int main() {
extern int $v []; p = $v;
; return 0; }
EOF
-if { (eval echo configure:3034: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3038: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "libiberty_cv_var_$v=yes"
else
for ac_func in $checkfuncs
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3060: checking for $ac_func" >&5
+echo "configure:3064: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3065 "configure"
+#line 3069 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:3088: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3092: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
done
echo $ac_n "checking whether canonicalize_file_name must be declared""... $ac_c" 1>&6
-echo "configure:3113: checking whether canonicalize_file_name must be declared" >&5
+echo "configure:3117: checking whether canonicalize_file_name must be declared" >&5
if eval "test \"`echo '$''{'libiberty_cv_decl_needed_canonicalize_file_name'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3118 "configure"
+#line 3122 "configure"
#include "confdefs.h"
#include "confdefs.h"
char *(*pfn) = (char *(*)) canonicalize_file_name
; return 0; }
EOF
-if { (eval echo configure:3140: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:3144: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
libiberty_cv_decl_needed_canonicalize_file_name=no
else
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:3176: checking for $ac_hdr" >&5
+echo "configure:3180: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3181 "configure"
+#line 3185 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3186: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3190: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
for ac_func in getpagesize
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3215: checking for $ac_func" >&5
+echo "configure:3219: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3220 "configure"
+#line 3224 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
; return 0; }
EOF
-if { (eval echo configure:3243: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3247: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
done
echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:3268: checking for working mmap" >&5
+echo "configure:3272: checking for working mmap" >&5
if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
ac_cv_func_mmap_fixed_mapped=no
else
cat > conftest.$ac_ext <<EOF
-#line 3276 "configure"
+#line 3280 "configure"
#include "confdefs.h"
/* Thanks to Mike Haertel and Jim Avera for this test.
}
EOF
-if { (eval echo configure:3416: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3420: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_func_mmap_fixed_mapped=yes
else
echo $ac_n "checking for working strncmp""... $ac_c" 1>&6
-echo "configure:3440: checking for working strncmp" >&5
+echo "configure:3444: checking for working strncmp" >&5
if eval "test \"`echo '$''{'ac_cv_func_strncmp_works'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
ac_cv_func_strncmp_works=no
else
cat > conftest.$ac_ext <<EOF
-#line 3448 "configure"
+#line 3452 "configure"
#include "confdefs.h"
/* Test by Jim Wilson and Kaveh Ghazi.
}
EOF
-if { (eval echo configure:3512: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3516: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_func_strncmp_works=yes
else
libiberty_AC_DECLARE_ERRNO
AC_CHECK_TYPE(uintptr_t, unsigned long)
-
-if test $ac_cv_type_uintptr_t = yes
-then
- AC_DEFINE(HAVE_UINTPTR_T, 1, [Define if you have the \`uintptr_t' type.])
-fi
+# Given the above check, we always have uintptr_t or a fallback
+# definition. So define HAVE_UINTPTR_T in case any imported code
+# relies on it.
+AC_DEFINE(HAVE_UINTPTR_T, 1, [Define if you have the \`uintptr_t' type.])
AC_TYPE_PID_T
funcs="$funcs memcmp"
funcs="$funcs memcpy"
funcs="$funcs memmove"
+funcs="$funcs mempcpy"
funcs="$funcs memset"
funcs="$funcs mkstemps"
funcs="$funcs putenv"
funcs="$funcs rename"
funcs="$funcs rindex"
funcs="$funcs setenv"
+funcs="$funcs snprintf"
funcs="$funcs sigsetmask"
+funcs="$funcs stpcpy"
+funcs="$funcs stpncpy"
funcs="$funcs strcasecmp"
funcs="$funcs strchr"
funcs="$funcs strdup"
funcs="$funcs vasprintf"
funcs="$funcs vfprintf"
funcs="$funcs vprintf"
+funcs="$funcs vsnprintf"
funcs="$funcs vsprintf"
funcs="$funcs waitpid"
if test "x" = "y"; then
AC_CHECK_FUNCS(asprintf atexit basename bcmp bcopy bsearch bzero calloc clock)
AC_CHECK_FUNCS(getcwd getpagesize index insque mkstemps memchr memcmp memcpy)
- AC_CHECK_FUNCS(memmove memset putenv random rename rindex sigsetmask)
- AC_CHECK_FUNCS(strcasecmp setenv strchr strdup strncasecmp strrchr strstr)
+ AC_CHECK_FUNCS(memmove mempcpy memset putenv random rename rindex sigsetmask)
+ AC_CHECK_FUNCS(strcasecmp setenv stpcpy stpncpy strchr strdup strncasecmp strrchr strstr)
AC_CHECK_FUNCS(strtod strtol strtoul tmpnam vasprintf vfprintf vprintf)
AC_CHECK_FUNCS(vsprintf waitpid getrusage on_exit psignal strerror strsignal)
- AC_CHECK_FUNCS(sysconf times sbrk gettimeofday ffs)
+ AC_CHECK_FUNCS(sysconf times sbrk gettimeofday ffs snprintf vsnprintf)
AC_CHECK_FUNCS(pstat_getstatic pstat_getdynamic sysmp getsysinfo table sysctl)
AC_CHECK_FUNCS(realpath canonicalize_file_name)
AC_DEFINE(HAVE_SYS_ERRLIST, 1, [Define if you have the sys_errlist variable.])
#if defined(__IEEE_BIG_ENDIAN) || defined(__IEEE_LITTLE_ENDIAN)
-double DEFUN(copysign, (x, y), double x AND double y)
+double
+copysign (x, y)
+ double x, y;
{
__ieee_double_shape_type a,b;
b.value = y;
#else
-double DEFUN(copysign, (x, y), double x AND double y)
+double
+copysign (x, y)
+ double x, y;
{
if ((x < 0 && y > 0) || (x > 0 && y < 0))
return -x;
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+#include "ansidecl.h"
#include "floatformat.h"
#include <math.h> /* ldexp */
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
extern void *memcpy (void *s1, const void *s2, size_t n);
extern void *memset (void *s, int c, size_t n);
Given a pointer to a string containing a pathname, returns a canonical
version of the filename. Symlinks will be resolved, and ``.'' and ``..''
components will be simplified. The returned value will be allocated using
-@code{xmalloc} or @code{malloc}.
+@code{malloc}, or @code{NULL} will be returned on a memory allocation error.
@end deftypefn
@end deftypefn
+@c mempcpy.c:23
+@deftypefn Supplemental void* mempcpy (void *@var{out}, const void *@var{in}, size_t @var{length})
+
+Copies @var{length} bytes from memory region @var{in} to region
+@var{out}. Returns a pointer to @var{out} + @var{length}.
+
+@end deftypefn
+
@c memset.c:6
@deftypefn Supplemental void* memset (void *@var{s}, int @var{c}, size_t @var{count})
@end deftypefn
+@c snprintf.c:28
+@deftypefn Supplemental int snprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, ...)
+
+This function is similar to sprintf, but it will print at most @var{n}
+characters. On error the return value is -1, otherwise it returns the
+number of characters that would have been printed had @var{n} been
+sufficiently large, regardless of the actual value of @var{n}. Note
+some pre-C99 system libraries do not implement this correctly so users
+cannot generally rely on the return value if the system version of
+this function is used.
+
+@end deftypefn
+
@c spaces.c:22
@deftypefn Extension char* spaces (int @var{count})
@end deftypefn
+@c stpcpy.c:23
+@deftypefn Supplemental char* stpcpy (char *@var{dst}, const char *@var{src})
+
+Copies the string @var{src} into @var{dst}. Returns a pointer to
+@var{dst} + strlen(@var{src}).
+
+@end deftypefn
+
+@c stpncpy.c:23
+@deftypefn Supplemental char* stpncpy (char *@var{dst}, const char *@var{src}, size_t @var{len})
+
+Copies the string @var{src} into @var{dst}, copying exactly @var{len}
+and padding with zeros if necessary. If @var{len} < strlen(@var{src})
+then return @var{dst} + @var{len}, otherwise returns @var{dst} +
+strlen(@var{src}).
+
+@end deftypefn
+
@c strcasecmp.c:15
@deftypefn Supplemental int strcasecmp (const char *@var{s1}, const char *@var{s2})
@end deftypefn
+@c vsnprintf.c:28
+@deftypefn Supplemental int vsnprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, va_list @var{ap})
+
+This function is similar to vsprintf, but it will print at most
+@var{n} characters. On error the return value is -1, otherwise it
+returns the number of characters that would have been printed had
+@var{n} been sufficiently large, regardless of the actual value of
+@var{n}. Note some pre-C99 system libraries do not implement this
+correctly so users cannot generally rely on the return value if the
+system version of this function is used.
+
+@end deftypefn
+
@c waitpid.c:3
@deftypefn Supplemental int waitpid (int @var{pid}, int *@var{status}, int)
char *
getcwd (buf, len)
char *buf;
- int len;
+ size_t len;
{
char ourbuf[MAXPATHLEN];
char *result;
nonoption_flags_len = nonoption_flags_max_len = 0;
else
{
- memset (__mempcpy (new_str, __getopt_nonoption_flags,
- nonoption_flags_max_len),
+ memset (mempcpy (new_str, __getopt_nonoption_flags,
+ nonoption_flags_max_len),
'\0', top + 1 - nonoption_flags_max_len);
nonoption_flags_max_len = top + 1;
__getopt_nonoption_flags = new_str;
if (__getopt_nonoption_flags == NULL)
nonoption_flags_max_len = -1;
else
- memset (__mempcpy (__getopt_nonoption_flags, orig_str, len),
+ memset (mempcpy (__getopt_nonoption_flags, orig_str, len),
'\0', nonoption_flags_max_len - len);
}
}
htab_trav callback;
PTR info;
{
- PTR *slot;
- PTR *limit;
-
if ((htab->n_elements - htab->n_deleted) * 8 < htab->size)
htab_expand (htab);
}
$mine{'config.h'} = "config.h";
+ opendir(INC, $srcdir);
+ while ($f = readdir INC) {
+ next unless $f =~ /\.h$/;
+ $mine{$f} = "\$(srcdir)/$f";
+ $deps{$f} = join(' ', &deps_for("$srcdir/$f"));
+ }
+ $mine{'config.h'} = "config.h";
+
open(IN, "$srcdir/Makefile.in");
open(OUT, ">$srcdir/Makefile.tmp");
while (<IN>) {
*/
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
*/
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
#endif
int
-DEFUN(memcmp, (str1, str2, count),
- const PTR str1 AND const PTR str2 AND size_t count)
+memcmp (str1, str2, count)
+ const PTR str1;
+ const PTR str2;
+ size_t count;
{
register const unsigned char *s1 = (const unsigned char*)str1;
register const unsigned char *s2 = (const unsigned char*)str2;
*/
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
#endif
+void bcopy PARAMS((const void*, void*, size_t));
+
PTR
-DEFUN(memcpy, (out, in, length), PTR out AND const PTR in AND size_t length)
+memcpy (out, in, length)
+ PTR out;
+ const PTR in;
+ size_t length;
{
bcopy(in, out, length);
return out;
*/
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
#endif
+void bcopy PARAMS ((const void*, void*, size_t));
+
PTR
memmove (s1, s2, n)
PTR s1;
--- /dev/null
+/* Implement the mempcpy function.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ Written by Kaveh R. Ghazi <ghazi@caip.rutgers.edu>.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB. If
+not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+/*
+
+@deftypefn Supplemental void* mempcpy (void *@var{out}, const void *@var{in}, size_t @var{length})
+
+Copies @var{length} bytes from memory region @var{in} to region
+@var{out}. Returns a pointer to @var{out} + @var{length}.
+
+@end deftypefn
+
+*/
+
+#include <ansidecl.h>
+#ifdef ANSI_PROTOTYPES
+#include <stddef.h>
+#else
+#define size_t unsigned long
+#endif
+
+extern PTR memcpy PARAMS ((PTR, const PTR, size_t));
+
+PTR
+mempcpy (dst, src, len)
+ PTR dst;
+ const PTR src;
+ size_t len;
+{
+ return (char *) memcpy (dst, src, len) + len;
+}
*/
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
#endif
PTR
-DEFUN(memset, (dest, val, len),
- PTR dest AND register int val AND register size_t len)
+memset (dest, val, len)
+ PTR dest;
+ register int val;
+ register size_t len;
{
register unsigned char *ptr = (unsigned char*)dest;
while (len-- > 0)
if (msg_size > errbuf_size)
{
#if defined HAVE_MEMPCPY || defined _LIBC
- *((char *) __mempcpy (errbuf, msg, errbuf_size - 1)) = '\0';
+ *((char *) mempcpy (errbuf, msg, errbuf_size - 1)) = '\0';
#else
memcpy (errbuf, msg, errbuf_size - 1);
errbuf[errbuf_size - 1] = 0;
*/
+#include "ansidecl.h"
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
int
rename (zfrom, zto)
- char *zfrom;
- char *zto;
+ const char *zfrom;
+ const char *zto;
{
if (link (zfrom, zto) < 0)
{
#ifdef SIG_SETMASK
int
-DEFUN(sigsetmask,(set),
- int set)
+sigsetmask (set)
+ int set;
{
sigset_t new;
sigset_t old;
--- /dev/null
+/* Implement the snprintf function.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ Written by Kaveh R. Ghazi <ghazi@caip.rutgers.edu>.
+
+This file is part of the libiberty library. This library is free
+software; you can redistribute it and/or modify it under the
+terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This library is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+As a special exception, if you link this library with files
+compiled with a GNU compiler to produce an executable, this does not cause
+the resulting executable to be covered by the GNU General Public License.
+This exception does not however invalidate any other reasons why
+the executable file might be covered by the GNU General Public License. */
+
+/*
+
+@deftypefn Supplemental int snprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, ...)
+
+This function is similar to sprintf, but it will print at most @var{n}
+characters. On error the return value is -1, otherwise it returns the
+number of characters that would have been printed had @var{n} been
+sufficiently large, regardless of the actual value of @var{n}. Note
+some pre-C99 system libraries do not implement this correctly so users
+cannot generally rely on the return value if the system version of
+this function is used.
+
+@end deftypefn
+
+*/
+
+#include "ansidecl.h"
+
+#ifdef ANSI_PROTOTYPES
+#include <stdarg.h>
+#include <stddef.h>
+#else
+#include <varargs.h>
+#define size_t unsigned long
+#endif
+
+int vsnprintf PARAMS ((char *, size_t, const char *, va_list));
+
+int
+snprintf VPARAMS ((char *s, size_t n, const char *format, ...))
+{
+ int result;
+ VA_OPEN (ap, format);
+ VA_FIXEDARG (ap, char *, s);
+ VA_FIXEDARG (ap, size_t, n);
+ VA_FIXEDARG (ap, const char *, format);
+ result = vsnprintf (s, n, format, ap);
+ VA_CLOSE (ap);
+ return result;
+}
--- /dev/null
+/* Implement the stpcpy function.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ Written by Kaveh R. Ghazi <ghazi@caip.rutgers.edu>.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB. If
+not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+/*
+
+@deftypefn Supplemental char* stpcpy (char *@var{dst}, const char *@var{src})
+
+Copies the string @var{src} into @var{dst}. Returns a pointer to
+@var{dst} + strlen(@var{src}).
+
+@end deftypefn
+
+*/
+
+#include <ansidecl.h>
+#ifdef ANSI_PROTOTYPES
+#include <stddef.h>
+#else
+#define size_t unsigned long
+#endif
+
+extern size_t strlen PARAMS ((const char *));
+extern PTR memcpy PARAMS ((PTR, const PTR, size_t));
+
+char *
+stpcpy (dst, src)
+ char *dst;
+ const char *src;
+{
+ const size_t len = strlen (src);
+ return (char *) memcpy (dst, src, len + 1) + len;
+}
--- /dev/null
+/* Implement the stpncpy function.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ Written by Kaveh R. Ghazi <ghazi@caip.rutgers.edu>.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB. If
+not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+/*
+
+@deftypefn Supplemental char* stpncpy (char *@var{dst}, const char *@var{src}, size_t @var{len})
+
+Copies the string @var{src} into @var{dst}, copying exactly @var{len}
+and padding with zeros if necessary. If @var{len} < strlen(@var{src})
+then return @var{dst} + @var{len}, otherwise returns @var{dst} +
+strlen(@var{src}).
+
+@end deftypefn
+
+*/
+
+#include <ansidecl.h>
+#ifdef ANSI_PROTOTYPES
+#include <stddef.h>
+#else
+#define size_t unsigned long
+#endif
+
+extern size_t strlen PARAMS ((const char *));
+extern char *strncpy PARAMS ((char *, const char *, size_t));
+
+char *
+stpncpy (dst, src, len)
+ char *dst;
+ const char *src;
+ size_t len;
+{
+ size_t n = strlen (src);
+ if (n > len)
+ n = len;
+ return strncpy (dst, src, len) + n;
+}
#endif /* LIBC_SCCS and not lint */
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
*/
+#include <ansidecl.h>
+#ifdef ANSI_PROTOTYPES
+#include <stddef.h>
+#else
+#define size_t unsigned long
+#endif
+
+extern size_t strlen PARAMS ((const char*));
+extern PTR malloc PARAMS ((size_t));
+extern PTR memcpy PARAMS ((PTR, const PTR, size_t));
+
char *
strdup(s)
char *s;
{
- char *result = (char*)malloc(strlen(s) + 1);
- if (result == (char*)0)
- return (char*)0;
- strcpy(result, s);
- return result;
+ size_t len = strlen (s) + 1;
+ char *result = (char*) malloc (len);
+ if (result == (char*) 0)
+ return (char*) 0;
+ return (char*) memcpy (result, s, len);
}
#endif /* LIBC_SCCS and not lint */
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
*/
#include <ansidecl.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
#undef sys_nsig
#ifndef NULL
-# ifdef __STDC__
+# ifdef ANSI_PROTOTYPES
# define NULL (void *) 0
# else
# define NULL 0
register char *p = s1;
extern char *strchr ();
extern int strncmp ();
-#if __GNUC__==2
- extern __SIZE_TYPE__ strlen ();
+#if __GNUC__ >= 2
+ extern __SIZE_TYPE__ strlen (const char *);
#endif
register int len = strlen (s2);
Copyright (C) 1998 Free Software Foundation, Inc.
*/
-#ifdef __STDC__
+#include "ansidecl.h"
+#ifdef ANSI_PROTOTYPES
#include <stdarg.h>
#else
#include <varargs.h>
*/
-#ifdef __STDC__
+#include <ansidecl.h>
+#ifdef ANSI_PROTOTYPES
#include <stdarg.h>
#else
#include <varargs.h>
#endif
#include <stdio.h>
-#include <ansidecl.h>
#undef vprintf
int
vprintf (format, ap)
--- /dev/null
+/* Implement the vsnprintf function.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ Written by Kaveh R. Ghazi <ghazi@caip.rutgers.edu>.
+
+This file is part of the libiberty library. This library is free
+software; you can redistribute it and/or modify it under the
+terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This library is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+As a special exception, if you link this library with files
+compiled with a GNU compiler to produce an executable, this does not cause
+the resulting executable to be covered by the GNU General Public License.
+This exception does not however invalidate any other reasons why
+the executable file might be covered by the GNU General Public License. */
+
+/*
+
+@deftypefn Supplemental int vsnprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, va_list @var{ap})
+
+This function is similar to vsprintf, but it will print at most
+@var{n} characters. On error the return value is -1, otherwise it
+returns the number of characters that would have been printed had
+@var{n} been sufficiently large, regardless of the actual value of
+@var{n}. Note some pre-C99 system libraries do not implement this
+correctly so users cannot generally rely on the return value if the
+system version of this function is used.
+
+@end deftypefn
+
+*/
+
+#include "config.h"
+#include "ansidecl.h"
+
+#ifdef ANSI_PROTOTYPES
+#include <stdarg.h>
+#else
+#include <varargs.h>
+#endif
+#ifdef HAVE_STRING_H
+#include <string.h>
+#endif
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+
+#include "libiberty.h"
+
+/* This implementation relies on a working vasprintf. */
+int
+vsnprintf (s, n, format, ap)
+ char * s;
+ size_t n;
+ const char *format;
+ va_list ap;
+{
+ char *buf = 0;
+ int result = vasprintf (&buf, format, ap);
+
+ if (!buf)
+ return -1;
+ if (result < 0)
+ {
+ free (buf);
+ return -1;
+ }
+
+ result = strlen (buf);
+ if (n > 0)
+ {
+ strncpy (s, buf, n);
+ if (n - 1 < (size_t) result)
+ s[n - 1] = 0;
+ }
+ free (buf);
+ return result;
+}
+
+#ifdef TEST
+/* Set the buffer to a known state. */
+#define CLEAR(BUF) do { memset ((BUF), 'X', sizeof (BUF)); (BUF)[14] = '\0'; } while (0)
+/* For assertions. */
+#define VERIFY(P) do { if (!(P)) abort(); } while (0)
+
+static int ATTRIBUTE_PRINTF_3
+checkit VPARAMS ((char *s, size_t n, const char *format, ...))
+{
+ int result;
+ VA_OPEN (ap, format);
+ VA_FIXEDARG (ap, char *, s);
+ VA_FIXEDARG (ap, size_t, n);
+ VA_FIXEDARG (ap, const char *, format);
+ result = vsnprintf (s, n, format, ap);
+ VA_CLOSE (ap);
+ return result;
+}
+
+extern int main PARAMS ((void));
+int
+main ()
+{
+ char buf[128];
+ int status;
+
+ CLEAR (buf);
+ status = checkit (buf, 10, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "foobar:9") == 0);
+
+ CLEAR (buf);
+ status = checkit (buf, 9, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "foobar:9") == 0);
+
+ CLEAR (buf);
+ status = checkit (buf, 8, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "foobar:") == 0);
+
+ CLEAR (buf);
+ status = checkit (buf, 7, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "foobar") == 0);
+
+ CLEAR (buf);
+ status = checkit (buf, 6, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "fooba") == 0);
+
+ CLEAR (buf);
+ status = checkit (buf, 2, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "f") == 0);
+
+ CLEAR (buf);
+ status = checkit (buf, 1, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "") == 0);
+
+ CLEAR (buf);
+ status = checkit (buf, 0, "%s:%d", "foobar", 9);
+ VERIFY (status==8 && strcmp (buf, "XXXXXXXXXXXXXX") == 0);
+
+ return 0;
+}
+#endif /* TEST */
This exception does not however invalidate any other reasons why
the executable file might be covered by the GNU General Public License. */
+#include <ansidecl.h>
+#ifdef ANSI_PROTOTYPES
+#include <stdarg.h>
+#else
#include <varargs.h>
+#endif
#include <stdio.h>
-#include <ansidecl.h>
#undef vsprintf
#if defined _IOSTRG && defined _IOWRT
#include <stdio.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
#include <stdio.h>
-#ifdef __STDC__
+#ifdef ANSI_PROTOTYPES
#include <stddef.h>
#else
#define size_t unsigned long
# This must be Linux ELF.
linux-gnu*)
case $host_cpu in
- alpha* | hppa* | i*86 | powerpc* | sparc* | ia64* )
+ alpha* | mips* | hppa* | i*86 | powerpc* | sparc* | ia64* )
lt_cv_deplibs_check_method=pass_all ;;
*)
# glibc up to 2.1.1 does not perform some relocations on ARM
+2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+ * h8500-opc.c: Replace occurrances of 'Hitachi' with 'Renesas'.
+
+2003-04-07 James E Wilson <wilson@tuliptree.org>
+
+ * ia64-ic.tbl (fr-readers): Add mem-writers-fp.
+ * ia64-asmtab.c: Regenerate.
+
+2003-04-08 Alexandre Oliva <aoliva@redhat.com>
+
+ * mips-dis.c (mips_gpr_names_newabi): Reverted previous patch.
+
+2003-04-07 Alexandre Oliva <aoliva@redhat.com>
+
+ * mips-dis.c (mips_gpr_names_newabi): $12-$15 are named $t4-$t7.
+
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
* tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and
-/* Instruction opcode header for Hitachi 8500.
+/* Instruction opcode header for Renesas 8500.
-Copyright 2001 Free Software Foundation, Inc.
+ Copyright 2001, 2003 Free Software Foundation, Inc.
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
typedef enum
{
GCCR, GPC,
GSEGC, GSEGD, GSEGE, GSEGT,GLAST
} gdbreg_type;
+
#define O_XORC 1
#define O_XOR 2
#define O_XCH 3
};
static const short dep236[] = {
- 40, 41, 75, 96, 134, 148, 174, 267, 2165, 2166, 2169, 2172, 4135,
+ 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138,
+ 139, 146, 163, 174, 178, 181, 267, 274, 2134, 2135, 2136, 2137, 2138, 2139,
+ 2165, 2166, 2169, 2172, 4135, 16524, 16526, 20613,
};
static const short dep237[] = {
+ 40, 41, 75, 96, 134, 148, 174, 267, 2165, 2166, 2169, 2172, 4135,
+};
+
+static const short dep238[] = {
40, 41, 75, 96, 134, 135, 139, 148, 174, 267, 2165, 2166, 2169, 2172, 4135,
};
-static const short dep238[] = {
+static const short dep239[] = {
40, 41, 75, 96, 134, 148, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172,
2312, 4135, 20613,
};
-static const short dep239[] = {
+static const short dep240[] = {
40, 41, 75, 96, 134, 135, 139, 148, 174, 267, 2137, 2138, 2139, 2165, 2166,
2169, 2172, 2312, 4135, 20613,
};
-static const short dep240[] = {
+static const short dep241[] = {
40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2310, 4135,
16524, 16526, 18746, 18748, 18749, 18751, 20613,
};
-static const short dep241[] = {
+static const short dep242[] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 24, 26, 27, 28, 29, 30, 31, 96, 182, 183, 184, 185, 186, 187, 188, 189,
190, 191, 192, 193, 194, 195, 197, 198, 200, 201, 203, 204, 206, 207, 208,
2312, 28852, 29002,
};
-static const short dep242[] = {
+static const short dep243[] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
22, 24, 25, 26, 28, 29, 30, 31, 40, 41, 96, 134, 171, 174, 182, 183, 184,
185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 197, 198, 200, 201,
{ NELS(dep233), dep233, NELS(dep232), dep232, },
{ NELS(dep234), dep234, NELS(dep232), dep232, },
{ NELS(dep233), dep233, NELS(dep235), dep235, },
- { NELS(dep236), dep236, NELS(dep31), dep31, },
+ { NELS(dep236), dep236, NELS(dep217), dep217, },
{ NELS(dep237), dep237, NELS(dep31), dep31, },
- { NELS(dep238), dep238, NELS(dep0), dep0, },
+ { NELS(dep238), dep238, NELS(dep31), dep31, },
{ NELS(dep239), dep239, NELS(dep0), dep0, },
- { NELS(dep240), dep240, NELS(dep62), dep62, },
+ { NELS(dep240), dep240, NELS(dep0), dep0, },
+ { NELS(dep241), dep241, NELS(dep62), dep62, },
{ 0, NULL, 0, NULL, },
- { NELS(dep242), dep242, NELS(dep241), dep241, },
+ { NELS(dep243), dep243, NELS(dep242), dep242, },
};
static const struct ia64_completer_table
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, 455, -1, 0, 1, 6 },
{ 0x0, 0x0, 0, 518, -1, 0, 1, 17 },
- { 0x0, 0x0, 0, -1, -1, 0, 1, 150 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 151 },
{ 0x0, 0x0, 0, 617, -1, 0, 1, 17 },
{ 0x0, 0x0, 0, 1836, -1, 0, 1, 10 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 9 },
{ 0x0, 0x0, 0, 1181, -1, 0, 1, 33 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 40 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 33 },
- { 0x0, 0x0, 0, -1, -1, 0, 1, 150 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 151 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 77 },
{ 0x0, 0x0, 0, 1216, -1, 0, 1, 124 },
{ 0x0, 0x0, 0, 1225, -1, 0, 1, 124 },
{ 0x0, 0x0, 0, 1419, -1, 0, 1, 140 },
{ 0x0, 0x0, 0, 1425, -1, 0, 1, 140 },
{ 0x0, 0x0, 0, 1431, -1, 0, 1, 140 },
- { 0x0, 0x0, 0, 1435, -1, 0, 1, 145 },
- { 0x0, 0x0, 0, 1439, -1, 0, 1, 147 },
- { 0x0, 0x0, 0, 1443, -1, 0, 1, 147 },
+ { 0x0, 0x0, 0, 1435, -1, 0, 1, 146 },
+ { 0x0, 0x0, 0, 1439, -1, 0, 1, 148 },
+ { 0x0, 0x0, 0, 1443, -1, 0, 1, 148 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 79 },
{ 0x0, 0x0, 0, 253, -1, 0, 1, 40 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 111 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 112 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 113 },
- { 0x0, 0x0, 0, -1, -1, 0, 1, 151 },
- { 0x0, 0x0, 0, -1, -1, 0, 1, 151 },
- { 0x0, 0x0, 0, -1, -1, 0, 1, 151 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 152 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 152 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 152 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 71 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
- { 0x0, 0x0, 0, -1, -1, 0, 1, 150 },
+ { 0x0, 0x0, 0, -1, -1, 0, 1, 151 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, 2394, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, 1723, -1, 0, 1, 138 },
{ 0x0, 0x0, 0, 1726, -1, 0, 1, 131 },
{ 0x0, 0x0, 0, 1729, -1, 0, 1, 138 },
- { 0x0, 0x0, 0, 1732, -1, 0, 1, 131 },
- { 0x0, 0x0, 0, 1733, -1, 0, 1, 131 },
- { 0x0, 0x0, 0, 1734, -1, 0, 1, 131 },
- { 0x0, 0x0, 0, 1735, -1, 0, 1, 131 },
- { 0x0, 0x0, 0, 1736, -1, 0, 1, 131 },
- { 0x0, 0x0, 0, 1737, -1, 0, 1, 131 },
- { 0x0, 0x0, 0, 1738, -1, 0, 1, 131 },
- { 0x0, 0x0, 0, 1739, -1, 0, 1, 131 },
+ { 0x0, 0x0, 0, 1732, -1, 0, 1, 145 },
+ { 0x0, 0x0, 0, 1733, -1, 0, 1, 145 },
+ { 0x0, 0x0, 0, 1734, -1, 0, 1, 145 },
+ { 0x0, 0x0, 0, 1735, -1, 0, 1, 145 },
+ { 0x0, 0x0, 0, 1736, -1, 0, 1, 145 },
+ { 0x0, 0x0, 0, 1737, -1, 0, 1, 145 },
+ { 0x0, 0x0, 0, 1738, -1, 0, 1, 145 },
+ { 0x0, 0x0, 0, 1739, -1, 0, 1, 145 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
{ 0x0, 0x0, 38, 960, -1, 0, 1, 95 },
{ 0x0, 0x0, 38, -1, -1, 0, 1, 104 },
{ 0x0, 0x0, 38, 966, -1, 0, 1, 116 },
- { 0x3, 0x3, 38, -1, -1, 30, 1, 149 },
+ { 0x3, 0x3, 38, -1, -1, 30, 1, 150 },
{ 0x0, 0x0, 38, 967, -1, 0, 1, 40 },
{ 0x0, 0x0, 40, -1, 825, 0, 0, -1 },
{ 0x0, 0x0, 40, -1, 833, 0, 0, -1 },
{ 0x0, 0x0, 44, 942, -1, 0, 1, 0 },
{ 0x0, 0x0, 44, 943, -1, 0, 1, 0 },
{ 0x0, 0x0, 44, 944, -1, 0, 1, 0 },
- { 0x1, 0x1, 45, -1, 1433, 30, 1, 146 },
- { 0x1, 0x1, 45, 815, 1432, 30, 1, 145 },
- { 0x1, 0x1, 45, -1, 1437, 30, 1, 148 },
- { 0x1, 0x1, 45, 816, 1436, 30, 1, 147 },
- { 0x1, 0x1, 45, -1, 1441, 30, 1, 148 },
- { 0x1, 0x1, 45, 817, 1440, 30, 1, 147 },
+ { 0x1, 0x1, 45, -1, 1433, 30, 1, 147 },
+ { 0x1, 0x1, 45, 815, 1432, 30, 1, 146 },
+ { 0x1, 0x1, 45, -1, 1437, 30, 1, 149 },
+ { 0x1, 0x1, 45, 816, 1436, 30, 1, 148 },
+ { 0x1, 0x1, 45, -1, 1441, 30, 1, 149 },
+ { 0x1, 0x1, 45, 817, 1440, 30, 1, 148 },
{ 0x3, 0x3, 46, -1, 978, 3, 1, 22 },
{ 0x1, 0x1, 47, 1889, -1, 30, 1, 137 },
- { 0x1, 0x1, 47, 1920, -1, 30, 1, 149 },
+ { 0x1, 0x1, 47, 1920, -1, 30, 1, 150 },
{ 0x0, 0x0, 49, -1, -1, 0, 1, 40 },
{ 0x0, 0x0, 49, -1, -1, 0, 1, 40 },
{ 0x0, 0x0, 49, -1, -1, 0, 1, 40 },
- { 0x1, 0x1, 56, -1, 1434, 31, 1, 146 },
- { 0x1, 0x1, 56, -1, 1438, 31, 1, 148 },
- { 0x1, 0x1, 56, -1, 1442, 31, 1, 148 },
+ { 0x1, 0x1, 56, -1, 1434, 31, 1, 147 },
+ { 0x1, 0x1, 56, -1, 1438, 31, 1, 149 },
+ { 0x1, 0x1, 56, -1, 1442, 31, 1, 149 },
{ 0x0, 0x0, 56, -1, -1, 0, 1, 94 },
{ 0x2, 0x3, 56, -1, -1, 27, 1, 94 },
{ 0x1, 0x1, 56, -1, -1, 28, 1, 94 },
{ 0x1, 0x1, 171, 1695, -1, 28, 1, 144 },
{ 0x1, 0x1, 171, 1696, -1, 28, 1, 144 },
{ 0x1, 0x1, 171, 1697, -1, 28, 1, 140 },
- { 0x1, 0x1, 171, 1448, -1, 28, 1, 145 },
- { 0x1, 0x1, 171, 1449, -1, 28, 1, 146 },
- { 0x1, 0x1, 171, 1450, -1, 28, 1, 146 },
- { 0x1, 0x1, 171, 1451, -1, 28, 1, 145 },
- { 0x1, 0x1, 171, 1452, -1, 28, 1, 147 },
- { 0x1, 0x1, 171, 1453, -1, 28, 1, 148 },
- { 0x1, 0x1, 171, 1454, -1, 28, 1, 148 },
- { 0x1, 0x1, 171, 1455, -1, 28, 1, 147 },
- { 0x1, 0x1, 171, 1456, -1, 28, 1, 147 },
- { 0x1, 0x1, 171, 1457, -1, 28, 1, 148 },
- { 0x1, 0x1, 171, 1458, -1, 28, 1, 148 },
- { 0x1, 0x1, 171, 1459, -1, 28, 1, 147 },
+ { 0x1, 0x1, 171, 1448, -1, 28, 1, 146 },
+ { 0x1, 0x1, 171, 1449, -1, 28, 1, 147 },
+ { 0x1, 0x1, 171, 1450, -1, 28, 1, 147 },
+ { 0x1, 0x1, 171, 1451, -1, 28, 1, 146 },
+ { 0x1, 0x1, 171, 1452, -1, 28, 1, 148 },
+ { 0x1, 0x1, 171, 1453, -1, 28, 1, 149 },
+ { 0x1, 0x1, 171, 1454, -1, 28, 1, 149 },
+ { 0x1, 0x1, 171, 1455, -1, 28, 1, 148 },
+ { 0x1, 0x1, 171, 1456, -1, 28, 1, 148 },
+ { 0x1, 0x1, 171, 1457, -1, 28, 1, 149 },
+ { 0x1, 0x1, 171, 1458, -1, 28, 1, 149 },
+ { 0x1, 0x1, 171, 1459, -1, 28, 1, 148 },
{ 0x1, 0x1, 171, 1740, -1, 28, 1, 136 },
{ 0x1, 0x1, 171, 1741, -1, 28, 1, 136 },
{ 0x1, 0x1, 171, 1742, -1, 28, 1, 136 },
{ 0x1, 0x1, 171, 1743, -1, 28, 1, 136 },
- { 0x1, 0x1, 172, 1698, -1, 29, 1, 145 },
- { 0x1, 0x1, 172, 1699, -1, 29, 1, 146 },
- { 0x1, 0x1, 172, 1700, -1, 29, 1, 146 },
- { 0x1, 0x1, 172, 1701, -1, 29, 1, 145 },
- { 0x1, 0x1, 172, 1702, -1, 29, 1, 147 },
- { 0x1, 0x1, 172, 1703, -1, 29, 1, 148 },
- { 0x1, 0x1, 172, 1704, -1, 29, 1, 148 },
- { 0x1, 0x1, 172, 1705, -1, 29, 1, 147 },
- { 0x1, 0x1, 172, 1706, -1, 29, 1, 147 },
- { 0x1, 0x1, 172, 1707, -1, 29, 1, 148 },
- { 0x1, 0x1, 172, 1708, -1, 29, 1, 148 },
- { 0x1, 0x1, 172, 1709, -1, 29, 1, 147 },
+ { 0x1, 0x1, 172, 1698, -1, 29, 1, 146 },
+ { 0x1, 0x1, 172, 1699, -1, 29, 1, 147 },
+ { 0x1, 0x1, 172, 1700, -1, 29, 1, 147 },
+ { 0x1, 0x1, 172, 1701, -1, 29, 1, 146 },
+ { 0x1, 0x1, 172, 1702, -1, 29, 1, 148 },
+ { 0x1, 0x1, 172, 1703, -1, 29, 1, 149 },
+ { 0x1, 0x1, 172, 1704, -1, 29, 1, 149 },
+ { 0x1, 0x1, 172, 1705, -1, 29, 1, 148 },
+ { 0x1, 0x1, 172, 1706, -1, 29, 1, 148 },
+ { 0x1, 0x1, 172, 1707, -1, 29, 1, 149 },
+ { 0x1, 0x1, 172, 1708, -1, 29, 1, 149 },
+ { 0x1, 0x1, 172, 1709, -1, 29, 1, 148 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 135 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 135 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 134 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 144 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 144 },
{ 0x3, 0x3, 173, 1919, -1, 28, 1, 140 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 146 },
- { 0x3, 0x3, 173, 803, -1, 28, 1, 146 },
- { 0x3, 0x3, 173, 804, -1, 28, 1, 145 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 147 },
+ { 0x3, 0x3, 173, 803, -1, 28, 1, 147 },
+ { 0x3, 0x3, 173, 804, -1, 28, 1, 146 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 148 },
- { 0x3, 0x3, 173, 805, -1, 28, 1, 148 },
- { 0x3, 0x3, 173, 806, -1, 28, 1, 147 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 147 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 149 },
+ { 0x3, 0x3, 173, 805, -1, 28, 1, 149 },
+ { 0x3, 0x3, 173, 806, -1, 28, 1, 148 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 148 },
- { 0x3, 0x3, 173, 807, -1, 28, 1, 148 },
- { 0x3, 0x3, 173, 808, -1, 28, 1, 147 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 149 },
+ { 0x3, 0x3, 173, 807, -1, 28, 1, 149 },
+ { 0x3, 0x3, 173, 808, -1, 28, 1, 148 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
{ 0x3, 0x3, 173, 1857, -1, 28, 1, 131 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 138 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 138 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 139 },
{ 0x3, 0x3, 173, 1865, -1, 28, 1, 138 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
- { 0x3, 0x3, 173, -1, -1, 28, 1, 131 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
+ { 0x3, 0x3, 173, -1, -1, 28, 1, 145 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 136 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 136 },
{ 0x3, 0x3, 173, -1, -1, 28, 1, 136 },
{ 0x1, 0x1, 219, 250, 1414, 32, 1, 141 },
{ 0x1, 0x1, 219, 251, 1420, 32, 1, 141 },
{ 0x1, 0x1, 219, 252, 1426, 32, 1, 141 },
- { 0x1, 0x1, 219, 710, -1, 31, 1, 149 },
+ { 0x1, 0x1, 219, 710, -1, 31, 1, 150 },
{ 0x0, 0x0, 220, 2012, -1, 0, 1, 65 },
{ 0x0, 0x0, 220, 2013, -1, 0, 1, 28 },
{ 0x0, 0x0, 220, 24, -1, 0, 1, 28 },
{ 0x1, 0x1, 225, -1, -1, 28, 1, 33 },
{ 0x1, 0x1, 225, -1, -1, 28, 1, 33 },
{ 0x0, 0x0, 232, 810, -1, 0, 1, 137 },
- { 0x0, 0x0, 232, 811, -1, 0, 1, 149 },
+ { 0x0, 0x0, 232, 811, -1, 0, 1, 150 },
{ 0x1, 0x1, 233, -1, 1725, 33, 1, 133 },
{ 0x1, 0x1, 233, -1, 1728, 33, 1, 139 },
- { 0x0, 0x0, 233, -1, 1730, 0, 1, 131 },
- { 0x0, 0x0, 233, -1, 1731, 0, 1, 131 },
+ { 0x0, 0x0, 233, -1, 1730, 0, 1, 145 },
+ { 0x0, 0x0, 233, -1, 1731, 0, 1, 145 },
{ 0x0, 0x0, 234, 744, 823, 0, 0, -1 },
{ 0x0, 0x0, 234, 745, 831, 0, 0, -1 },
{ 0x0, 0x0, 234, 746, 827, 0, 0, -1 },
fpcmp-s1; fpcmp[Field(sf)==s1]
fpcmp-s2; fpcmp[Field(sf)==s2]
fpcmp-s3; fpcmp[Field(sf)==s3]
-fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf
+fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf, IC:mem-writers-fp
fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf
gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat
gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt
+2003-04-13 Nick Clifton <nickc@redhat.com>
+
+ * armvirt.c (GetWord): Only call XScale_check_memacc if in XScale
+ mode.
+ (PutWord): Likewise.
+
2003-03-30 Nick Clifton <nickc@redhat.com>
* configure.in (CON_FLAGS): Remove.
ARMword **pagetable;
ARMword *pageptr;
- if (check)
+ if (check && state->is_XScale)
XScale_check_memacc (state, &address, 0);
page = address >> PAGEBITS;
ARMword **pagetable;
ARMword *pageptr;
- if (check)
+ if (check && state->is_XScale)
XScale_check_memacc (state, &address, 1);
page = address >> PAGEBITS;
+2003-04-13 Michael Snyder <msnyder@redhat.com>
+
+ * Make-common.in (sim-events.o, sim-config.o): Depend on sim-main.h.
+
2003-03-01 Andrew Cagney <cagney@redhat.com>
* sim-engine.c (sim_engine_halt): If jmpbuf is invalid, abort.
$(SIM_EXTRA_DEPS)
$(CC) -c $(srccom)/sim-bits.c $(ALL_CFLAGS)
-sim-config.o: $(srccom)/sim-config.c $(sim-config_h) \
+sim-config.o: $(srccom)/sim-config.c $(sim-config_h) sim-main.h \
$(SIM_EXTRA_DEPS)
$(CC) -c $(srccom)/sim-config.c $(ALL_CFLAGS)
sim-engine.o: $(srccom)/sim-engine.c $(sim_main_headers) $(sim-engine_h)
$(CC) -c $(srccom)/sim-engine.c $(ALL_CFLAGS)
-sim-events.o: $(srccom)/sim-events.c $(sim-events_h) \
+sim-events.o: $(srccom)/sim-events.c $(sim-events_h) sim-main.h \
$(SIM_EXTRA_DEPS)
$(CC) -c $(srccom)/sim-events.c $(ALL_CFLAGS)
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
# OBSOLETE fr30-*-*) sim_target=fr30 ;;
- h8300*-*-*) sim_target=h8300 ;;
+ h8300*-*-*)
+ sim_target=h8300
+ extra_subdirs="${extra_subdirs} testsuite"
+ ;;
h8500-*-*) sim_target=h8500 ;;
i960-*-*) sim_target=i960 ;;
m32r-*-*) sim_target=m32r ;;
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
# OBSOLETE fr30-*-*) sim_target=fr30 ;;
- h8300*-*-*) sim_target=h8300 ;;
+ h8300*-*-*)
+ sim_target=h8300
+ extra_subdirs="${extra_subdirs} testsuite"
+ ;;
h8500-*-*) sim_target=h8500 ;;
i960-*-*) sim_target=i960 ;;
m32r-*-*) sim_target=m32r ;;
+2003-04-13 Michael Snyder <msnyder@redhat.com>
+
+ * compile.c (sim_resume): Implement 'daa' and 'das' instructions.
+
2003-03-20 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
* compile.c (cmdline_location): Added function to
}
goto next;
+ case O (O_DAA, SB):
+ /* Decimal Adjust Addition. This is for BCD arithmetic. */
+ res = GET_B_REG (code->src.reg);
+ if (!c && (0 <= (res >> 4) && (res >> 4) <= 9)
+ && !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
+ res = res; /* Value added == 0. */
+ else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8)
+ && !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
+ res = res + 0x6; /* Value added == 6. */
+ else if (!c && (0 <= (res >> 4) && (res >> 4) <= 9)
+ && h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
+ res = res + 0x6; /* Value added == 6. */
+ else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15)
+ && !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
+ res = res + 0x60; /* Value added == 60. */
+ else if (!c && (9 <= (res >> 4) && (res >> 4) <= 15)
+ && !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
+ res = res + 0x66; /* Value added == 66. */
+ else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15)
+ && h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
+ res = res + 0x66; /* Value added == 66. */
+ else if (c && (1 <= (res >> 4) && (res >> 4) <= 2)
+ && !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
+ res = res + 0x160; /* Value added == 60, plus 'carry'. */
+ else if (c && (1 <= (res >> 4) && (res >> 4) <= 2)
+ && !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
+ res = res + 0x166; /* Value added == 66, plus 'carry'. */
+ else if (c && (1 <= (res >> 4) && (res >> 4) <= 3)
+ && h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
+ res = res + 0x166; /* Value added == 66, plus 'carry'. */
+
+ goto alu8;
+
+ case O (O_DAS, SB):
+ /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
+ res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
+ if (!c && (0 <= (res >> 4) && (res >> 4) <= 9)
+ && !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
+ res = res; /* Value added == 0. */
+ else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8)
+ && h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
+ res = res + 0xfa; /* Value added == 0xfa. */
+ else if (c && (7 <= (res >> 4) && (res >> 4) <= 15)
+ && !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
+ res = res + 0xa0; /* Value added == 0xa0. */
+ else if (c && (6 <= (res >> 4) && (res >> 4) <= 15)
+ && h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
+ res = res + 0x9a; /* Value added == 0x9a. */
+
+ goto alu8;
+
default:
illegal:
cpu.state = SIM_STATE_STOPPED;
+2003-04-15 Richard Sandiford <rsandifo@redhat.com>
+
+ * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
+ unsigned operands.
+
2003-02-27 Andrew Cagney <cagney@redhat.com>
- * interp.c (sim_open):
- (sim_create_inferior):
+ * interp.c (sim_open): Rename _bfd to bfd.
+ (sim_create_inferior): Ditto.
2003-01-14 Chris Demetriou <cgd@broadcom.com>
(long) CIA);
TRACE_ALU_INPUT2 (x, y);
- product = (unsigned_p ? x * y : EXTEND32 (x) * EXTEND32 (y));
+ product = (unsigned_p
+ ? V8_4 (x, 1) * V8_4 (y, 1)
+ : EXTEND32 (x) * EXTEND32 (y));
result = (subtract_p ? lhs - product : lhs + product);
if (saturate_p)
{
--- /dev/null
+2003-04-11 Michael Snyder <msnyder@redhat.com>
+
+ * mac.s: New file. Test multiply-accumulator insns.
+ * allinsn.exp: Add mac tests.
+
+2003-04-10 Michael Snyder <msnyder@redhat.com>
+
+ * brabc.s: New file. Test for bra/bc and bra/bs.
+ * allinsn.exp: Add bra/bc test.
+ * testsuite.inc: New macro memcmp.
+ * bfld.s: Un-comment insns, assembler works now.
+
+ * bfld.s: Add tests for bfst insn.
+ * bfld.s: New file. Test for bfld insn.
+ * allinsn.exp: Add bfld test.
+
+2003-04-09 Michael Snyder <msnyder@redhat.com>
+
+ * movmd.s: New file. Test for movmd insn.
+ * allinsn.exp: Add movmd test.
+ * movsd.s: Un-comment movsd instructions (assembler works now).
+ * movsd.s: New file. Test for movsd insn.
+ * allinsn.exp: Add movsd test.
+ * add.b.s: Add tests for ABS8 mode.
+
+2003-04-08 Michael Snyder <msnyder@redhat.com>
+
+ * bset.s: New file, test bset and bclr.
+ * allinsn.exp: Add bset test.
+ * and.b.s: Add test for andc ccr.
+ * or.b.s: Add test for orc ccr.
+ * xor.b.s: Add test for xorc ccr.
+
+2003-04-07 Michael Snyder <msnyder@redhat.com>
+
+ * testutils.inc (_write_and_exit): Rewrite for new syscall lib.
+ (pass, fail): Use new syscall abi.
+
+2003-04-04 Michael Snyder <msnyder@redhat.com>
+
+ * rotl.s: Add INDEXB, INDEXW, INDEXL tests.
+ * rotl.s, rotr.s, rotxl.s, rotxr.s: New files.
+ * allinsn.exp: Add rot insn tests.
+
+2003-04-03 Michael Snyder <msnyder@redhat.com>
+
+ * shift.s: Remove. Replace with
+ * shal.s, shar.s, shll.s, shlr.s: New files.
+ * allinsn.exp: Invoke new test files.
+ * ext.w.s, ext.l.s: New files, tests for exts and extu.
+
+2003-04-02 Michael Snyder <msnyder@redhat.com>
+
+ * bra.s: New file, test for branch insns.
+ * allinsn.exp: Add bra.s.
+ * adds.s: Add ccr flags checking.
+
+2003-04-01 Michael Snyder <msnyder@redhat.com>
+
+ * shift.s: Add lots of tests.
+ * mov.b.s: Add word and long tests.
+ * neg.s: New file, test neg instructions.
+ * allinsn.exp: Add neg test.
+
+2003-03-31 Michael Snyder <msnyder@redhat.com>
+
+ * addx.s: Add word and long tests.
+
+2003-03-28 Michael Snyder <msnyder@redhat.com>
+
+ * mov.w.s: Add a bunch more tests for new addressing modes.
+ * add.l.s: Comment fixes.
+ * not.s: Add tests for word and long operations.
+ * not.s: Fill out remaining tests for byte operation.
+ * add.l.s: Fix up .if directives for h8h, h8s.
+ * mov.l.s: Simplify results checking.
+ * add.l.s: Add several dozen new tests for new addressing modes.
+
+2003-03-25 Michael Snyder <msnyder@redhat.com>
+
+ * mov.l.s: A sampling of tests for esoteric addressing modes.
+ * mov.l.s: Finish tests for immediate and register direct modes.
+ * mov.l.s: Simplify, add more tests.
+ * mov.l.s: Add more new tests.
+
+2003-03-13 Michael Snyder <msnyder@redhat.com>
+
+ * not.s: New test.
+ * allinsn.exp: Add not.s test.
+ * add.b.s, add.w.s, addx.s and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s:
+ Un-comment assembler instructions: assembler should handle 'em all.
+
+2003-03-04 Michael Snyder <msnyder@redhat.com>
+
+ * add.b.s: Add DISP16, DISP32, ABS16, ABS32.
+ * sub.b.s: Add POSTINC, POSTDEC, RDIND.
+ * or.b.s, xor.b.s: Add RDPOSTINC, RDPREINC, RDPREDEC.
+
+2003-03-03 Michael Snyder <msnyder@redhat.com>
+
+ * add.b.s, addx.s, and.b.s, cmp.b.s: Add RDPOSTINC,
+ RDPREINC, RDPREDEC.
+ * add.b.s, addx.s, and.b.s, cmp.b.s, or.b.s, xor.b.s: Add RDPOSTDEC.
+
+2003-02-28 Michael Snyder <msnyder@redhat.com>
+
+ * add.b.s, and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s:
+ Add tests for RDIND. Also add RDPOSTDEC to cmp.b.s.
+ * allinsn.exp: All tests run for all machine flavors.
+
+2003-02-27 Michael Snyder <msnyder@redhat.com>
+
+ * add.l.s, adds.s, addx.s, and.l.s, cmp.l.s, cmp.w.s, jmp.s,
+ or.l.s, or.w.s, sub.l.s, sub.w.s, xor.l.s, xor.w.s):
+ Substitute actual assembler instructions for data words!
+ * addx.s: Add tests for RDIND and RDPOSTDEC.
+ * shifts.s: New file.
+ * allinsn.exp: Add shifts.s.
+ * testutils.inc: Add assembler directive ".h8300sx".
+ * add.w.s, add.l.s, ...: Add linker directive "-m h8300sxelf".
+
+2003-02-25 Michael Snyder <msnyder@redhat.com>
+
+ * adds.s, addw.s: New files.
+ * testutils.inc (set_ccr, set_carry_flag, test_carry_clear,
+ test_carry_set, test_ovf_clear, test_ovf_set, test_zero_clear,
+ test_zero_set, test_neg_clear, test_neg_set): New macros.
+
+2003-02-24 Michael Snyder <msnyder@redhat.com>
+
+ * stc.c: Extend tests to all h8300s opcodes.
+ * ldc.s: New file.
+
+ * stc.s: New file.
+ * allinsn.exp: Add stc test.
+ * and.l.s: 'and.l imm:16 clears upper half of dest. reg.
+ * testutils.inc: Add kludge for h8sx.
+ (set_gr_a5a5, set_grs_a5a5, test_gr_a5a5, test_grs_a5a5,
+ set_ccr_zero): New macros.
+
+2003-02-18 Michael Snyder <msnyder@redhat.com>
+
+ * daa.s: New file.
+ * das.s: New file.
+ * dec.s: New file.
+ * inc.s: New file.
+ * or.b.s: New file.
+ * or.w.s: New file.
+ * or.l.s: New file.
+ * xor.b.s: New file.
+ * xor.w.s: New file.
+ * xor.l.s: New file.
+ * and.l.s: Fix expected result.
+ * allinsn.exp: Add new tests.
+
+2003-02-12 Michael Snyder <msnyder@redhat.com>
+
+ * and.b.s: New file.
+ * and.w.s: New file.
+ * and.l.s: New file.
+ * cmp.b.s: New file.
+ * cmp.w.s: New file.
+ * cmp.l.s: New file.
+ * jmp.s: New file.
+ * add.w.s: Add test for 3-bit immediate operand.
+ * add.l.s: Add test for 3-bit and 16-bit immediate operands.
+ * mov.b.s (dst_addr16, dst_addr32): Delete.
+ * nop.s: Simplify using testutils.inc macros.
+ * sub.w.s: Add test for 3-bit immediate operand.
+ * sub.l.s: Add test for 3-bit and 16-bit immediate operands.
+
+2003-02-07 Michael Snyder <msnyder@redhat.com>
+
+ * mov.b.s: Add tests for more addressing modes.
+ (src_addr16, src_addr32, dst_addr16, dst_addr32): Delete.
+ * mov.b.s: Add prospective tests for h8sx modes.
+ * mov.w.s: New file (test for 'mov.w').
+ * mov.l.s: New file (test for 'mov.l').
+ * sub.b.s: New file (test for 'sub.b').
+ * sub.w.s: New file (test for 'sub.w').
+ * sub.l.s: New file (test for 'sub.l').
+ * allinsn.exp: Turn new tests on.
+
+2003-02-06 Michael Snyder <msnyder@redhat.com>
+
+ * allinsn.exp: New file.
+ * testutils.inc: New file.
+ * nop.s: New file (test for 'nop' insn).
+ * add.b.s: New file (test for 'add.b').
+ * add.w.s: New file (test for 'add.w').
+ * add.l.s: New file (test for 'add.l').
+ * mov.b.s: New file (test for 'mov.b');
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+change-log-default-name: "ChangeLog"
+End:
--- /dev/null
+# Hitachi H8 testcase 'add.b'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # add.b #xx:8, rd ; 8 rd xxxxxxxx
+ # add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx
+ # add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx
+ # add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx
+ # add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx
+ # add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx
+ # add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx
+ # add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx
+ # add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx
+ # add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx
+ # add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx
+ # add.b rs, rd ; 0 8 rs rd
+ # add.b reg8, @erd ; 7 d rd ???? 0 8 rs ????
+ # add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs
+ # add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs
+ # add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs
+ # add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs
+ # add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16
+ # add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32
+ # add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ????
+ # add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ????
+ # add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ????
+ #
+
+ # Coming soon:
+ # add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx
+ # add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8
+ # ...
+
+.data
+pre_byte: .byte 0
+byte_dest: .byte 0
+post_byte: .byte 0
+
+ start
+
+add_b_imm8_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; add.b #xx:8,Rd
+ add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5aa r0 ; add result: a5 + 5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+add_b_imm8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@eRd
+ mov #byte_dest, er0
+ add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x7d00
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest, er0 ; er0 still contains address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #5, r0l
+ beq .L1
+ fail
+.L1:
+
+add_b_imm8_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@eRd+
+ mov #byte_dest, er0
+ add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte, er0 ; er0 contains address plus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #10, r0l
+ beq .L2
+ fail
+.L2:
+
+add_b_imm8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@eRd-
+ mov #byte_dest, er0
+ add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte, er0 ; er0 contains address minus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #15, r0l
+ beq .L3
+ fail
+.L3:
+
+add_b_imm8_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@+eRd
+ mov #pre_byte, er0
+ add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest, er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #20, r0l
+ beq .L4
+ fail
+.L4:
+
+add_b_imm8_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@-eRd
+ mov #post_byte, er0
+ add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest, er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #25, r0l
+ beq .L5
+ fail
+.L5:
+
+add_b_imm8_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@(dd:16, eRd)
+ mov #post_byte, er0
+ add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest.
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 0xffff
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte, er0 ; er0 contains address plus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #30, r0l
+ beq .L6
+ fail
+.L6:
+
+add_b_imm8_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@(dd:32, eRd)
+ mov #pre_byte, er0
+ add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest.
+;;; .word 0x7804
+;;; .word 0x6a28
+;;; .word 0x0000
+;;; .word 0x0001
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte, er0 ; er0 contains address minus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #35, r0l
+ beq .L7
+ fail
+.L7:
+
+add_b_imm8_abs8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b reg8,@aa:8
+ ;; NOTE: for abs8, we will use the SBR register as a base,
+ ;; since otherwise we would have to make sure that the destination
+ ;; was in the zero page.
+ ;;
+ mov #byte_dest-100, er0
+ ldc er0, sbr
+ add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest
+;;; .word 0x7f64
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #40, r0l
+ beq .L8
+ fail
+.L8:
+
+add_b_imm8_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@aa:16
+ add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #45, r0l
+ beq .L9
+ fail
+.L9:
+
+add_b_imm8_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b #xx:8,@aa:32
+ add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x8005
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #50, r0l
+ beq .L10
+ fail
+.L10:
+
+.endif
+
+add_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; add.b Rs,Rd
+ mov.b #5, r0h
+ add.b r0h, r0l ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0x05aa r0 ; add result: a5 + 5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+add_b_reg8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b rs8,@eRd ; Add to register indirect
+ mov #byte_dest, er0
+ mov #5, r1l
+ add.b r1l, @er0 ; reg8 src, reg indirect dest
+;;; .word 0x7d00
+;;; .word 0x0890
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #55, r0l
+ beq .L11
+ fail
+.L11:
+
+add_b_reg8_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b rs8,@eRd+ ; Add to register post-increment
+ mov #byte_dest, er0
+ mov #5, r1l
+ add.b r1l, @er0+ ; reg8 src, reg post-incr dest
+;;; .word 0x0179
+;;; .word 0x8019
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte er0 ; er0 contains address plus one
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #60, r0l
+ beq .L12
+ fail
+.L12:
+
+add_b_reg8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b rs8,@eRd- ; Add to register post-decrement
+ mov #byte_dest, er0
+ mov #5, r1l
+ add.b r1l, @er0- ; reg8 src, reg post-decr dest
+;;; .word 0x0179
+;;; .word 0xa019
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #65, r0l
+ beq .L13
+ fail
+.L13:
+
+add_b_reg8_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b rs8,@+eRd ; Add to register pre-increment
+ mov #pre_byte, er0
+ mov #5, r1l
+ add.b r1l, @+er0 ; reg8 src, reg pre-incr dest
+;;; .word 0x0179
+;;; .word 0x9019
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #70, r0l
+ beq .L14
+ fail
+.L14:
+
+add_b_reg8_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b rs8,@-eRd ; Add to register pre-decrement
+ mov #post_byte, er0
+ mov #5, r1l
+ add.b r1l, @-er0 ; reg8 src, reg pre-decr dest
+;;; .word 0x0179
+;;; .word 0xb019
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #75, r0l
+ beq .L15
+ fail
+.L15:
+
+add_b_reg8_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement
+ mov #pre_byte, er0
+ mov #5, r1l
+ add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest
+;;; .word 0x0179
+;;; .word 0xc019
+;;; .word 0x0001
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #80, r0l
+ beq .L16
+ fail
+.L16:
+
+add_b_reg8_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement
+ mov #post_byte, er0
+ mov #5, r1l
+ add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest
+;;; .word 0x0179
+;;; .word 0xd819
+;;; .word 0xffff
+;;; .word 0xffff
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte er0 ; er0 contains address plus one
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #85, r0l
+ beq .L17
+ fail
+.L17:
+
+add_b_reg8_abs8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b reg8,@aa:8
+ ;; NOTE: for abs8, we will use the SBR register as a base,
+ ;; since otherwise we would have to make sure that the destination
+ ;; was in the zero page.
+ ;;
+ mov #byte_dest-100, er0
+ ldc er0, sbr
+ mov #5, r1l
+ add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest
+;;; .word 0x7f64
+;;; .word 0x0890
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
+ test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #90, r0l
+ beq .L18
+ fail
+.L18:
+
+add_b_reg8_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b reg8,@aa:16
+ mov #5, r0l
+ add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x0880
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #95, r0l
+ beq .L19
+ fail
+.L19:
+
+add_b_reg8_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.b reg8,@aa:32
+ mov #5, r0l
+ add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x0880
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #100, r0l
+ beq .L20
+ fail
+.L20:
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'add.l'
+# mach(): h8300h h8300s h8sx
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # add.l xx:3, erd
+ # add.l xx:16, erd
+ # add.l xx:32, erd
+ # add.l xx:16, @erd
+ # add.l xx:16, @erd+
+ # add.l xx:16, @erd-
+ # add.l xx:16, @+erd
+ # add.l xx:16, @-erd
+ # add.l xx:16, @(dd:2, erd)
+ # add.l xx:16, @(dd:16, erd)
+ # add.l xx:16, @(dd:32, erd)
+ # add.l xx:16, @aa:16
+ # add.l xx:16, @aa:32
+ # add.l xx:32, @erd+
+ # add.l xx:32, @erd-
+ # add.l xx:32, @+erd
+ # add.l xx:32, @-erd
+ # add.l xx:32, @(dd:2, erd)
+ # add.l xx:32, @(dd:16, erd)
+ # add.l xx:32, @(dd:32, erd)
+ # add.l xx:32, @aa:16
+ # add.l xx:32, @aa:32
+ # add.l ers, erd
+ # add.l ers, @erd
+ # add.l ers, @erd+
+ # add.l ers, @erd-
+ # add.l ers, @+erd
+ # add.l ers, @-erd
+ # add.l ers, @(dd:2, erd)
+ # add.l ers, @(dd:16, erd)
+ # add.l ers, @(dd:32, erd)
+ # add.l ers, @aa:16
+ # add.l ers, @aa:32
+ # add.l ers, erd
+ # add.l @ers, erd
+ # add.l @ers+, erd
+ # add.l @ers-, erd
+ # add.l @+ers, erd
+ # add.l @-ers, erd
+ # add.l @(dd:2, ers), erd
+ # add.l @(dd:16, ers), erd
+ # add.l @(dd:32, ers), erd
+ # add.l @aa:16, erd
+ # add.l @aa:32, erd
+ # add.l @ers, @erd
+ # add.l @ers+, @erd+
+ # add.l @ers-, @erd-
+ # add.l @+ers, +@erd
+ # add.l @-ers, @-erd
+ # add.l @(dd:2, ers), @(dd:2, erd)
+ # add.l @(dd:16, ers), @(dd:16, erd)
+ # add.l @(dd:32, ers), @(dd:32, erd)
+ # add.l @aa:16, @aa:16
+ # add.l @aa:32, @aa:32
+
+ start
+
+ .data
+ .align 4
+long_src:
+ .long 0x12345678
+long_dst:
+ .long 0x87654321
+
+ .text
+
+ ;;
+ ;; Add long from immediate source
+ ;;
+
+.if (sim_cpu == h8sx)
+add_l_imm3_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:3, erd
+ add.l #0x3:3, er0 ; Immediate 16-bit operand
+;;; .word 0x0ab8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a5a8 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_imm16_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, erd
+ add.l #0x1234, er0 ; Immediate 16-bit operand
+;;; .word 0x7a18
+;;; .word 0x1234
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5b7d9 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+add_l_imm32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, erd
+ add.l #0x12345678, er0 ; Immediate 32-bit operand
+;;; .word 0x7a10
+;;; .long 0x12345678
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+add_l_imm16_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @erd
+ mov.l #long_dst, er1
+ add.l #0xdead:16, @er1 ; Register indirect operand
+;;; .word 0x010e
+;;; .word 0x0110
+;;; .word 0xdead
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext11
+ fail
+.Lnext11:
+ mov.l #0x87654321, @long_dst ; Initialize it again for the next use.
+
+add_l_imm16_to_postinc: ; post-increment from imm16 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @erd+
+ mov.l #long_dst, er1
+ add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands.
+;;; .word 0x010e
+;;; .word 0x8110
+;;; .word 0xdead
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst+4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext12
+ fail
+.Lnext12:
+ mov.l #0x87654321, @long_dst ; initialize it again for the next use.
+
+add_l_imm16_to_postdec: ; post-decrement from imm16 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @erd-
+ mov.l #long_dst, er1
+ add.l #0xdead:16, @er1- ; Imm16, register post-decr operands.
+;;; .word 0x010e
+;;; .word 0xa110
+;;; .word 0xdead
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext13
+ fail
+.Lnext13:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm16_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @+erd
+ mov.l #long_dst-4, er1
+ add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands
+;;; .word 0x010e
+;;; .word 0x9110
+;;; .word 0xdead
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext14
+ fail
+.Lnext14:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm16_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @-erd
+ mov.l #long_dst+4, er1
+ add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands
+;;; .word 0x010e
+;;; .word 0xb110
+;;; .word 0xdead
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext15
+ fail
+.Lnext15:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm16_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @(dd:2, erd)
+ mov.l #long_dst-3, er1
+ add.l #0xdead:16, @(3:2, er1) ; Imm16, reg plus 2-bit disp. operand
+;;; .word 0x010e
+;;; .word 0x3110
+;;; .word 0xdead
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext16
+ fail
+.Lnext16:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm16_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @(dd:16, erd)
+ mov.l #long_dst-4, er1
+ add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x010e
+;;; .word 0xc110
+;;; .word 0xdead
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext17
+ fail
+.Lnext17:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm16_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @(dd:32, erd)
+ mov.l #long_dst-8, er1
+ add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x010e
+;;; .word 0xc910
+;;; .word 0xdead
+;;; .long 8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext18
+ fail
+.Lnext18:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm16_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @aa:16
+ add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand
+;;; .word 0x010e
+;;; .word 0x4010
+;;; .word 0xdead
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext19
+ fail
+.Lnext19:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm16_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:16, @aa:32
+ add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand
+;;; .word 0x010e
+;;; .word 0x4810
+;;; .word 0xdead
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x876621ce, @long_dst
+ beq .Lnext20
+ fail
+.Lnext20:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @erd
+ mov.l #long_dst, er1
+ add.l #0xcafedead:32, @er1 ; Register indirect operand
+;;; .word 0x010e
+;;; .word 0x0118
+;;; .long 0xcafedead
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext21
+ fail
+.Lnext21:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_postinc: ; post-increment from imm32 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @erd+
+ mov.l #long_dst, er1
+ add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands.
+;;; .word 0x010e
+;;; .word 0x8118
+;;; .long 0xcafedead
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst+4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext22
+ fail
+.Lnext22:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_postdec: ; post-decrement from imm32 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @erd-
+ mov.l #long_dst, er1
+ add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands.
+;;; .word 0x010e
+;;; .word 0xa118
+;;; .long 0xcafedead
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext23
+ fail
+.Lnext23:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @+erd
+ mov.l #long_dst-4, er1
+ add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands
+;;; .word 0x010e
+;;; .word 0x9118
+;;; .long 0xcafedead
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext24
+ fail
+.Lnext24:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @-erd
+ mov.l #long_dst+4, er1
+ add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands
+;;; .word 0x010e
+;;; .word 0xb118
+;;; .long 0xcafedead
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext25
+ fail
+.Lnext25:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @(dd:2, erd)
+ mov.l #long_dst-3, er1
+ add.l #0xcafedead:32, @(3:2, er1) ; Imm32, reg plus 2-bit disp. operand
+;;; .word 0x010e
+;;; .word 0x3118
+;;; .long 0xcafedead
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext26
+ fail
+.Lnext26:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @(dd:16, erd)
+ mov.l #long_dst-4, er1
+ add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x010e
+;;; .word 0xc118
+;;; .long 0xcafedead
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext27
+ fail
+.Lnext27:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @(dd:32, erd)
+ mov.l #long_dst-8, er1
+ add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x010e
+;;; .word 0xc918
+;;; .long 0xcafedead
+;;; .long 8
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext28
+ fail
+.Lnext28:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @aa:16
+ add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand
+;;; .word 0x010e
+;;; .word 0x4018
+;;; .long 0xcafedead
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext29
+ fail
+.Lnext29:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_imm32_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l #xx:32, @aa:32
+ add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand
+;;; .word 0x010e
+;;; .word 0x4818
+;;; .long 0xcafedead
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x526421ce, @long_dst
+ beq .Lnext30
+ fail
+.Lnext30:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+.endif
+
+ ;;
+ ;; Add long from register source
+ ;;
+
+add_l_reg32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, erd
+ mov.l #0x12345678, er1
+ add.l er1, er0 ; Register 32-bit operand
+;;; .word 0x0a90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0 ; add result
+ test_h_gr32 0x12345678 er1 ; add src unchanged
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+add_l_reg32_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @erd
+ mov.l #long_dst, er1
+ add.l er0, @er1 ; Register indirect operand
+;;; .word 0x0109
+;;; .word 0x0110
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext44
+ fail
+.Lnext44:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_postinc: ; post-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @erd+
+ mov.l #long_dst, er1
+ add.l er0, @er1+ ; Register post-incr operand
+;;; .word 0x0109
+;;; .word 0x8110
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst+4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext49
+ fail
+.Lnext49:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_postdec: ; post-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @erd-
+ mov.l #long_dst, er1
+ add.l er0, @er1- ; Register post-decr operand
+;;; .word 0x0109
+;;; .word 0xa110
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext50
+ fail
+.Lnext50:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @+erd
+ mov.l #long_dst-4, er1
+ add.l er0, @+er1 ; Register pre-incr operand
+;;; .word 0x0109
+;;; .word 0x9110
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext51
+ fail
+.Lnext51:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @-erd
+ mov.l #long_dst+4, er1
+ add.l er0, @-er1 ; Register pre-decr operand
+;;; .word 0x0109
+;;; .word 0xb110
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext48
+ fail
+.Lnext48:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @(dd:2, erd)
+ mov.l #long_dst-3, er1
+ add.l er0, @(3:2, er1) ; Register plus 2-bit disp. operand
+;;; .word 0x0109
+;;; .word 0x3110
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext52
+ fail
+.Lnext52:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @(dd:16, erd)
+ mov.l #long_dst-4, er1
+ add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x0109
+;;; .word 0xc110
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext45
+ fail
+.Lnext45:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @(dd:32, erd)
+ mov.l #long_dst-8, er1
+ add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x0109
+;;; .word 0xc910
+;;; .long 8
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_h_gr32 long_dst-8, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext46
+ fail
+.Lnext46:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @aa:16
+ add.l er0, @long_dst:16 ; 16-bit address-direct operand
+;;; .word 0x0109
+;;; .word 0x4110
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext41
+ fail
+.Lnext41:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+add_l_reg32_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l ers, @aa:32
+ add.l er0, @long_dst:32 ; 32-bit address-direct operand
+;;; .word 0x0109
+;;; .word 0x4910
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
+ test_neg_clear
+ test_zero_clear
+ test_ovf_set
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x2d0ae8c6, @long_dst
+ beq .Lnext42
+ fail
+.Lnext42:
+ mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
+
+ ;;
+ ;; Add long to register destination.
+ ;;
+
+add_l_indirect_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @ers, Rd
+ mov.l #long_src, er1
+ add.l @er1, er0 ; Register indirect operand
+;;; .word 0x010a
+;;; .word 0x0110
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_h_gr32 long_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_postinc_to_reg32: ; post-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @ers+, erd
+ mov.l #long_src, er1
+ add.l @er1+, er0 ; Register post-incr operand
+;;; .word 0x010a
+;;; .word 0x8110
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_h_gr32 long_src+4, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_postdec_to_reg32: ; post-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @ers-, erd
+ mov.l #long_src, er1
+ add.l @er1-, er0 ; Register post-decr operand
+;;; .word 0x010a
+;;; .word 0xa110
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_h_gr32 long_src-4, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_preinc_to_reg32: ; pre-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @+ers, erd
+ mov.l #long_src-4, er1
+ add.l @+er1, er0 ; Register pre-incr operand
+;;; .word 0x010a
+;;; .word 0x9110
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_h_gr32 long_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_predec_to_reg32: ; pre-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @-ers, erd
+ mov.l #long_src+4, er1
+ add.l @-er1, er0 ; Register pre-decr operand
+;;; .word 0x010a
+;;; .word 0xb110
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_h_gr32 long_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+add_l_disp2_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @(dd:2, ers), erd
+ mov.l #long_src-1, er1
+ add.l @(1:2, er1), er0 ; Register plus 2-bit disp. operand
+;;; .word 0x010a
+;;; .word 0x1110
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 long_src-1, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_disp16_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @(dd:16, ers), erd
+ mov.l #long_src+0x1234, er1
+ add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand
+;;; .word 0x010a
+;;; .word 0xc110
+;;; .word -0x1234
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 long_src+0x1234, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_disp32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @(dd:32, ers), erd
+ mov.l #long_src+65536, er1
+ add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand
+;;; .word 0x010a
+;;; .word 0xc910
+;;; .long -65536
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 long_src+65536, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_abs16_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @aa:16, erd
+ add.l @long_src:16, er0 ; 16-bit address-direct operand
+;;; .word 0x010a
+;;; .word 0x4010
+;;; .word @long_src
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+add_l_abs32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @aa:32, erd
+ add.l @long_src:32, er0 ; 32-bit address-direct operand
+;;; .word 0x010a
+;;; .word 0x4810
+;;; .long @long_src
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xb7d9fc1d er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+ ;;
+ ;; Add long from memory to memory
+ ;;
+
+add_l_indirect_to_indirect: ; reg indirect, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @ers, @erd
+ mov.l #long_src, er1
+ mov.l #long_dst, er0
+ add.l @er1, @er0
+;;; .word 0x0104
+;;; .word 0x691c
+;;; .word 0x0010
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst er0
+ test_h_gr32 long_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst ; FIXME
+ beq .Lnext55
+ fail
+.Lnext55:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext56
+ fail
+.Lnext56: ; OK, pass on.
+
+add_l_postinc_to_postinc: ; reg post-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @ers+, @erd+
+ mov.l #long_src, er1
+ mov.l #long_dst, er0
+ add.l @er1+, @er0+
+;;; .word 0x0104
+;;; .word 0x6d1c
+;;; .word 0x8010
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst+4 er0
+ test_h_gr32 long_src+4 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext65
+ fail
+.Lnext65:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext66
+ fail
+.Lnext66: ; OK, pass on.
+
+add_l_postdec_to_postdec: ; reg post-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @ers-, @erd-
+ mov.l #long_src, er1
+ mov.l #long_dst, er0
+ add.l @er1-, @er0-
+;;; .word 0x0106
+;;; .word 0x6d1c
+;;; .word 0xa010
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-4 er0
+ test_h_gr32 long_src-4 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext75
+ fail
+.Lnext75:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext76
+ fail
+.Lnext76: ; OK, pass on.
+
+add_l_preinc_to_preinc: ; reg pre-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @+ers, @+erd
+ mov.l #long_src-4, er1
+ mov.l #long_dst-4, er0
+ add.l @+er1, @+er0
+;;; .word 0x0105
+;;; .word 0x6d1c
+;;; .word 0x9010
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst er0
+ test_h_gr32 long_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext85
+ fail
+.Lnext85:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext86
+ fail
+.Lnext86: ; OK, pass on.
+
+add_l_predec_to_predec: ; reg pre-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @-ers, @-erd
+ mov.l #long_src+4, er1
+ mov.l #long_dst+4, er0
+ add.l @-er1, @-er0
+;;; .word 0x0107
+;;; .word 0x6d1c
+;;; .word 0xb010
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst er0
+ test_h_gr32 long_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext95
+ fail
+.Lnext95:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext96
+ fail
+.Lnext96: ; OK, pass on.
+
+add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @(dd:2, ers), @(dd:2, erd)
+ mov.l #long_src-1, er1
+ mov.l #long_dst-2, er0
+ add.l @(1:2, er1), @(2:2, er0)
+;;; .word 0x0105
+;;; .word 0x691c
+;;; .word 0x2010
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-2 er0
+ test_h_gr32 long_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext105
+ fail
+.Lnext105:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext106
+ fail
+.Lnext106: ; OK, pass on.
+
+add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @(dd:16, ers), @(dd:16, erd)
+ mov.l #long_src-1, er1
+ mov.l #long_dst-2, er0
+ add.l @(1:16, er1), @(2:16, er0)
+;;; .word 0x0104
+;;; .word 0x6f1c
+;;; .word 0x0001
+;;; .word 0xc010
+;;; .word 0x0002
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-2 er0
+ test_h_gr32 long_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext115
+ fail
+.Lnext115:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext116
+ fail
+.Lnext116: ; OK, pass on.
+
+add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @(dd:32, ers), @(dd:32, erd)
+ mov.l #long_src-1, er1
+ mov.l #long_dst-2, er0
+ add.l @(1:32, er1), @(2:32, er0)
+;;; .word 0x7894
+;;; .word 0x6b2c
+;;; .word 0xc9c8
+;;; .long 1
+;;; .word 0xc810
+;;; .long 2
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-2 er0
+ test_h_gr32 long_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext125
+ fail
+.Lnext125:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext126
+ fail
+.Lnext126: ; OK, pass on.
+
+add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @aa:16, @aa:16
+ add.l @long_src:16, @long_dst:16
+;;; .word 0x0104
+;;; .word 0x6b0c
+;;; .word @long_src
+;;; .word 0x4010
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext135
+ fail
+.Lnext135:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext136
+ fail
+.Lnext136: ; OK, pass on.
+
+add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; add.l @aa:32, @aa:32
+ add.l @long_src:32, @long_dst:32
+;;; .word 0x0104
+;;; .word 0x6b2c
+;;; .long @long_src
+;;; .word 0x4810
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0x99999999, @long_dst
+ beq .Lnext145
+ fail
+.Lnext145:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0x87654321, @long_dst
+ cmp.l #0x99999999, @long_dst
+ bne .Lnext146
+ fail
+.Lnext146: ; OK, pass on.
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'add.w'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # add.w xx:3, rd ; 0 a 0xxx rd (sx only)
+ # add.w xx:16, rd ; 7 9 1 rd imm16
+ # add.w rs, rd ; 0 9 rs rd
+ #
+
+ start
+
+.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
+add_w_imm3:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; add.w #xx:3,Rd ; Immediate 3-bit operand
+ add.w #7, r0 ; FIXME will not assemble yet
+; .word 0x0a70 ; Fake it until assembler will take it.
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7
+ test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+add_w_imm16:
+ ;; add.w immediate not available in h8300 mode.
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; add.w #xx:16,Rd
+ add.w #0x111, r0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
+ test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+add_w_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; add.w Rs,Rd
+ mov.w #0x111, r1
+ add.w r1, r0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
+ test_h_gr16 0x0111 r1
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
+ test_h_gr32 0xa5a50111 er1
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'adds'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # adds #1, erd ; 0 b 0 xerd
+ # adds #2, erd ; 0 b 8 xerd
+ # adds #4, erd ; 0 b 9 xerd
+ #
+
+ start
+.if (sim_cpu) ; 32 bit only
+adds_1:
+ set_grs_a5a5
+ set_ccr_zero
+
+ adds #1, er0
+
+ test_cc_clear ; adds should not affect any condition codes
+ test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+adds_2:
+ set_grs_a5a5
+ set_ccr_zero
+
+ adds #2, er0
+
+ test_cc_clear ; adds should not affect any condition codes
+ test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+adds_4:
+ set_grs_a5a5
+ set_ccr_zero
+
+ adds #4, er0
+
+ test_cc_clear ; adds should not affect any condition codes
+ test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+.endif
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'addx'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx
+ # addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx
+ # addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx
+ # addx.b rs8, rd8 ; 0 e rs8 rd8
+ # addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ????
+ # addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ????
+ # addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8
+ # addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8
+ # addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ????
+ # addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ????
+ #
+ # coming soon:
+ # word ops
+ # long ops
+
+.data
+byte_src: .byte 0x5
+byte_dest: .byte 0
+
+ .align 2
+word_src: .word 0x505
+word_dest: .word 0
+
+ .align 4
+long_src: .long 0x50505
+long_dest: .long 0
+
+
+ start
+
+addx_b_imm8_0:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b #xx:8,Rd ; Addx with carry initially zero.
+ addx.b #5, r0l ; Immediate 8-bit operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr16 0xa5aa r0 ; add result: a5 + 5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_b_imm8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b #xx:8,Rd ; Addx with carry initially one.
+ set_carry_flag 1
+ addx.b #5, r0l ; Immediate 8-bit operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+addx_b_imm8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b #xx:8,@eRd ; Addx to register indirect
+ mov #byte_dest, er0
+ addx.b #5, @er0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.b #5, @byte_dest
+ beq .Lb1
+ fail
+.Lb1:
+
+addx_b_imm8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b #xx:8,@eRd- ; Addx to register post-decrement
+ mov #byte_dest, er0
+ addx.b #5, @er0-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.b #10, @byte_dest
+ beq .Lb2
+ fail
+.Lb2:
+.endif
+
+addx_b_reg8_0:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b Rs,Rd ; addx with carry initially zero
+ mov.b #5, r0h
+ addx.b r0h, r0l ; Register operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr16 0x05aa r0 ; add result: a5 + 5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b Rs,Rd ; addx with carry initially one
+ mov.b #5, r0h
+ set_carry_flag 1
+ addx.b r0h, r0l ; Register operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+addx_b_reg8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b rs8,@eRd ; Addx to register indirect
+ mov #byte_dest, er0
+ mov.b #5, r1l
+ addx.b r1l, @er0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.b #15, @byte_dest
+ beq .Lb3
+ fail
+.Lb3:
+
+addx_b_reg8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b rs8,@eRd- ; Addx to register post-decrement
+ mov #byte_dest, er0
+ mov.b #5, r1l
+ addx.b r1l, @er0-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.b #20, @byte_dest
+ beq .Lb4
+ fail
+.Lb4:
+
+addx_b_rsind_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
+ mov #byte_src, er0
+ addx.b @er0, r1l
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_src er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_b_rspostdec_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b @eRs-,rd8 ; Addx to register post-decrement
+ mov #byte_src, er0
+ addx.b @er0-, r1l
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_src-1 er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_b_rsind_rsind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
+ mov #byte_src, er0
+ mov #byte_dest, er1
+ addx.b @er0, @er1
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_src er0 ; er0 still contains src address
+ test_h_gr32 byte_dest er1 ; er1 still contains dst address
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ;; Now check the result of the add to memory.
+ cmp.b #25, @byte_dest
+ beq .Lb5
+ fail
+.Lb5:
+
+addx_b_rspostdec_rspostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.b @eRs-,rd8 ; Addx to register post-decrement
+ mov #byte_src, er0
+ mov #byte_dest, er1
+ addx.b @er0-, @er1-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one
+ test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ;; Now check the result of the add to memory.
+ cmp.b #30, @byte_dest
+ beq .Lb6
+ fail
+.Lb6:
+
+addx_w_imm16_0:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w #xx:16,Rd ; Addx with carry initially zero.
+ addx.w #0x505, r0 ; Immediate 16-bit operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505
+ test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_w_imm16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w #xx:16,Rd ; Addx with carry initially one.
+ set_carry_flag 1
+ addx.w #0x505, r0 ; Immediate 16-bit operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1
+ test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_w_imm16_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w #xx:16,@eRd ; Addx to register indirect
+ mov #word_dest, er0
+ addx.w #0x505, @er0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0 ; er0 still contains address
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.w #0x505, @word_dest
+ beq .Lw1
+ fail
+.Lw1:
+
+addx_w_imm16_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w #xx:16,@eRd- ; Addx to register post-decrement
+ mov #word_dest, er0
+ addx.w #0x505, @er0-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.w #0xa0a, @word_dest
+ beq .Lw2
+ fail
+.Lw2:
+
+addx_w_reg16_0:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w Rs,Rd ; addx with carry initially zero
+ mov.w #0x505, e0
+ addx.w e0, r0 ; Register operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 0x0505aaaa er0 ; add result:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w Rs,Rd ; addx with carry initially one
+ mov.w #0x505, e0
+ set_carry_flag 1
+ addx.w e0, r0 ; Register operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 0x0505aaab er0 ; add result:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_w_reg16_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w rs8,@eRd ; Addx to register indirect
+ mov #word_dest, er0
+ mov.w #0x505, r1
+ addx.w r1, @er0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a50505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.w #0xf0f, @word_dest
+ beq .Lw3
+ fail
+.Lw3:
+
+addx_w_reg16_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w rs8,@eRd- ; Addx to register post-decrement
+ mov #word_dest, er0
+ mov.w #0x505, r1
+ addx.w r1, @er0-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a50505 er1 ; er1 contains the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.w #0x1414, @word_dest
+ beq .Lw4
+ fail
+.Lw4:
+
+addx_w_rsind_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
+ mov #word_src, er0
+ addx.w @er0, r1
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 word_src er0 ; er0 still contains address
+ test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_w_rspostdec_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w @eRs-,rd8 ; Addx to register post-decrement
+ mov #word_src, er0
+ addx.w @er0-, r1
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 word_src-2 er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_w_rsind_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
+ mov #word_src, er0
+ mov #word_dest, er1
+ addx.w @er0, @er1
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 word_src er0 ; er0 still contains src address
+ test_h_gr32 word_dest er1 ; er1 still contains dst address
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ;; Now check the result of the add to memory.
+ cmp.w #0x1919, @word_dest
+ beq .Lw5
+ fail
+.Lw5:
+
+addx_w_rspostdec_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.w @eRs-,rd8 ; Addx to register post-decrement
+ mov #word_src, er0
+ mov #word_dest, er1
+ addx.w @er0-, @er1-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 word_src-2 er0 ; er0 contains src address minus one
+ test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ;; Now check the result of the add to memory.
+ cmp.w #0x1e1e, @word_dest
+ beq .Lw6
+ fail
+.Lw6:
+
+addx_l_imm32_0:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l #xx:32,Rd ; Addx with carry initially zero.
+ addx.l #0x50505, er0 ; Immediate 32-bit operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 0xa5aaaaaa er0 ; add result:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_l_imm32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l #xx:32,Rd ; Addx with carry initially one.
+ set_carry_flag 1
+ addx.l #0x50505, er0 ; Immediate 32-bit operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 0xa5aaaaab er0 ; add result:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_l_imm32_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l #xx:32,@eRd ; Addx to register indirect
+ mov #long_dest, er0
+ addx.l #0x50505, @er0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0 ; er0 still contains address
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.l #0x50505, @long_dest
+ beq .Ll1
+ fail
+.Ll1:
+
+addx_l_imm32_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l #xx:32,@eRd- ; Addx to register post-decrement
+ mov #long_dest, er0
+ addx.l #0x50505, @er0-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.l #0xa0a0a, @long_dest
+ beq .Ll2
+ fail
+.Ll2:
+
+addx_l_reg32_0:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l Rs,Rd ; addx with carry initially zero
+ mov.l #0x50505, er0
+ addx.l er0, er1 ; Register operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 0x50505 er0 ; add load
+ test_h_gr32 0xa5aaaaaa er1 ; add result:
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l Rs,Rd ; addx with carry initially one
+ mov.l #0x50505, er0
+ set_carry_flag 1
+ addx.l er0, er1 ; Register operand
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 0x50505 er0 ; add result:
+ test_h_gr32 0xa5aaaaab er1 ; add result:
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_l_reg32_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l rs8,@eRd ; Addx to register indirect
+ mov #long_dest, er0
+ mov.l #0x50505, er1
+ addx.l er1, @er0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0 ; er0 still contains address
+ test_h_gr32 0x50505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.l #0xf0f0f, @long_dest
+ beq .Ll3
+ fail
+.Ll3:
+
+addx_l_reg32_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l rs8,@eRd- ; Addx to register post-decrement
+ mov #long_dest, er0
+ mov.l #0x50505, er1
+ addx.l er1, @er0-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
+ test_h_gr32 0x50505 er1 ; er1 contains the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the add to memory.
+ cmp.l #0x141414, @long_dest
+ beq .Ll4
+ fail
+.Ll4:
+
+addx_l_rsind_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
+ mov #long_src, er0
+ addx.l @er0, er1
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 long_src er0 ; er0 still contains address
+ test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_l_rspostdec_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l @eRs-,rd8 ; Addx to register post-decrement
+ mov #long_src, er0
+ addx.l @er0-, er1
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 long_src-4 er0 ; er0 contains address minus one
+ test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+addx_l_rsind_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
+ mov #long_src, er0
+ mov #long_dest, er1
+ addx.l @er0, @er1
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 long_src er0 ; er0 still contains src address
+ test_h_gr32 long_dest er1 ; er1 still contains dst address
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ;; Now check the result of the add to memory.
+ cmp.l #0x191919, @long_dest
+ beq .Ll5
+ fail
+.Ll5:
+
+addx_l_rspostdec_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; addx.l @eRs-,rd8 ; Addx to register post-decrement
+ mov #long_src, er0
+ mov #long_dest, er1
+ addx.l @er0-, @er1-
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 long_src-4 er0 ; er0 contains src address minus one
+ test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ;; Now check the result of the add to memory.
+ cmp.l #0x1e1e1e, @long_dest
+ beq .Ll6
+ fail
+.Ll6:
+.endif
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8/300 (h, s, sx) simulator testsuite
+
+set all "h8300 h8300h h8300s h8sx"
+
+if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then {
+ run_sim_test add.b.s $all
+ run_sim_test add.w.s $all
+ run_sim_test add.l.s $all
+ run_sim_test adds.s $all
+ run_sim_test addx.s $all
+ run_sim_test and.b.s $all
+ run_sim_test and.w.s $all
+ run_sim_test and.l.s $all
+ run_sim_test bfld.s h8sx
+ run_sim_test bra.s $all
+ run_sim_test bset.s $all
+ run_sim_test cmp.b.s $all
+ run_sim_test cmp.w.s $all
+ run_sim_test cmp.l.s $all
+ run_sim_test daa.s $all
+ run_sim_test das.s $all
+ run_sim_test dec.s $all
+ run_sim_test ext.w.s $all
+ run_sim_test ext.l.s $all
+ run_sim_test inc.s $all
+ run_sim_test jmp.s $all
+ run_sim_test ldc.s $all
+ run_sim_test mac.s $all
+ run_sim_test mov.b.s $all
+ run_sim_test mov.w.s $all
+ run_sim_test mov.l.s $all
+ run_sim_test movmd.s h8sx
+ run_sim_test movsd.s h8sx
+ run_sim_test neg.s $all
+ run_sim_test nop.s $all
+ run_sim_test not.s $all
+ run_sim_test or.b.s $all
+ run_sim_test or.w.s $all
+ run_sim_test or.l.s $all
+ run_sim_test rotl.s $all
+ run_sim_test rotr.s $all
+ run_sim_test rotxl.s $all
+ run_sim_test rotxr.s $all
+ run_sim_test shal.s $all
+ run_sim_test shar.s $all
+ run_sim_test shll.s $all
+ run_sim_test shlr.s $all
+ run_sim_test stc.s $all
+ run_sim_test sub.b.s $all
+ run_sim_test sub.w.s $all
+ run_sim_test sub.l.s $all
+ run_sim_test xor.b.s $all
+ run_sim_test xor.w.s $all
+ run_sim_test xor.l.s $all
+}
--- /dev/null
+# Hitachi H8 testcase 'and.b'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # and.b #xx:8, rd ; e rd xxxxxxxx
+ # and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx
+ # and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
+ # and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
+ # and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
+ # and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
+ # and.b rs, rd ; 1 6 rs rd
+ # and.b reg8, @erd ; 7 d rd ???? 1 6 rs ????
+ # and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs
+ # and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs
+ # and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs
+ # and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs
+ #
+ # andc #xx:8, ccr ; 0 6 xxxxxxxx
+ # andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx
+
+ # Coming soon:
+ # ...
+
+.data
+pre_byte: .byte 0
+byte_dest: .byte 0xa5
+post_byte: .byte 0
+
+ start
+
+and_b_imm8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; and.b #xx:8,Rd
+ and.b #0xaa, r0l ; Immediate 8-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a0 r0 ; and result: a5 & aa
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+and_b_imm8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b #xx:8,@eRd
+ mov #byte_dest, er0
+ and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x7d00
+;;; .word 0xe0aa
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest, er0 ; er0 still contains address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa0, r0l
+ beq .L1
+ fail
+.L1:
+
+and_b_imm8_rdpostinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b #xx:8,@eRd+
+ mov #byte_dest, er0
+ and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0xe055
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte, er0 ; er0 contains address plus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x05, r0l
+ beq .L2
+ fail
+.L2:
+
+and_b_imm8_rdpostdec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b #xx:8,@eRd-
+ mov #byte_dest, er0
+ and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0xe0aa
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 pre_byte, er0 ; er0 contains address minus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa0, r0l
+ beq .L3
+ fail
+.L3:
+
+and_b_imm8_rdpreinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b #xx:8,@+eRd
+ mov #pre_byte, er0
+ and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0xe055
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest, er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x05, r0l
+ beq .L4
+ fail
+.L4:
+
+and_b_imm8_rdpredec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b #xx:8,@-eRd
+ mov #post_byte, er0
+ and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0xe0aa
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest, er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa0, r0l
+ beq .L5
+ fail
+.L5:
+
+
+.endif
+
+and_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; and.b Rs,Rd
+ mov.b #0xaa, r0h
+ and.b r0h, r0l ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xaaa0 r0 ; and result: a5 & aa
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+and_b_reg8_rdind:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b rs8,@eRd ; And to register indirect
+ mov #byte_dest, er0
+ mov #0x55, r1l
+ and.b r1l, @er0 ; reg8 src, reg indirect dest
+;;; .word 0x7d00
+;;; .word 0x1690
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x05, r0l
+ beq .L6
+ fail
+.L6:
+
+and_b_reg8_rdpostinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b rs8,@eRd+ ; And to register post-incr
+ mov #byte_dest, er0
+ mov #0xaa, r1l
+ and.b r1l, @er0+ ; reg8 src, reg post-incr dest
+;;; .word 0x0179
+;;; .word 0x8069
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 post_byte er0 ; er0 contains address plus one
+ test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa0, r0l
+ beq .L7
+ fail
+.L7:
+
+and_b_reg8_rdpostdec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b rs8,@eRd- ; And to register post-decr
+ mov #byte_dest, er0
+ mov #0x55, r1l
+ and.b r1l, @er0- ; reg8 src, reg post-decr dest
+;;; .word 0x0179
+;;; .word 0xa069
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x05, r0l
+ beq .L8
+ fail
+.L8:
+
+and_b_reg8_rdpreinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b rs8,@+eRd ; And to register post-incr
+ mov #pre_byte, er0
+ mov #0xaa, r1l
+ and.b r1l, @+er0 ; reg8 src, reg post-incr dest
+;;; .word 0x0179
+;;; .word 0x9069
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa0, r0l
+ beq .L9
+ fail
+.L9:
+
+and_b_reg8_rdpredec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; and.b rs8,@-eRd ; And to register post-decr
+ mov #post_byte, er0
+ mov #0x55, r1l
+ and.b r1l, @-er0 ; reg8 src, reg post-decr dest
+;;; .word 0x0179
+;;; .word 0xb069
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the and to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x05, r0l
+ beq .L10
+ fail
+.L10:
+
+andc_imm8_ccr:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; andc #xx:8,ccr
+ set_ccr 0xff
+
+ test_neg_set
+ andc #0xf7, ccr ; Immediate 8-bit operand (neg flag)
+ test_neg_clear
+
+ test_zero_set
+ andc #0xfb, ccr ; Immediate 8-bit operand (zero flag)
+ test_zero_clear
+
+ test_ovf_set
+ andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag)
+ test_ovf_clear
+
+ test_carry_set
+ andc #0xfe, ccr ; Immediate 8-bit operand (carry flag)
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'and.l'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
+and_l_imm16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; and.l #xx:16,Rd
+ and.l #0xaaaa:16, er0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+and_l_imm32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; and.l #xx:32,Rd
+ and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+and_l_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; and.l Rs,Rd
+ mov.l #0xaaaaaaaa, er1
+ and.l er1, er0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
+ test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'and.w'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+and_w_imm16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; and.w #xx:16,Rd
+ and.w #0xaaaa, r0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+and_w_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; and.w Rs,Rd
+ mov.w #0xaaaa, r1
+ and.w r1, r0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
+ test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
+ test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'bfld', 'bfst'
+# mach(): h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ .data
+byte_src: .byte 0xa5
+byte_dst: .byte 0
+
+ start
+
+.if (sim_cpu == h8sx)
+bfld_imm8_ind:
+ set_grs_a5a5
+ mov #byte_src, er2
+
+ ;; bfld #xx:8, @ers, rd8
+ set_ccr_zero
+ bfld #1, @er2, r1l
+ test_cc_clear
+ test_h_gr8 1 r1l
+
+ set_ccr_zero
+ bfld #2, @er2, r1l
+ test_cc_clear
+ test_h_gr8 0 r1l
+
+ set_ccr_zero
+ bfld #7, @er2, r1l
+ test_cc_clear
+ test_h_gr8 5 r1l
+
+ set_ccr_zero
+ bfld #0x10, @er2, r1l
+ test_cc_clear
+ test_h_gr8 0 r1l
+
+ set_ccr_zero
+ bfld #0x20, @er2, r1l
+ test_cc_clear
+ test_h_gr8 1 r1l
+
+ set_ccr_zero
+ bfld #0xf0, @er2, r1l
+ test_cc_clear
+ test_h_gr8 0xa r1l
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 0xa5a5a50a er1
+ test_h_gr32 byte_src er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+bfld_imm8_abs16:
+ set_grs_a5a5
+
+ ;; bfld #xx:8, @aa:16, rd8
+ set_ccr_zero
+ bfld #0x80, @byte_src:16, r1l
+ test_cc_clear
+ test_h_gr8 1 r1l
+
+ set_ccr_zero
+ bfld #0x40, @byte_src:16, r1l
+ test_cc_clear
+ test_h_gr8 0 r1l
+
+ set_ccr_zero
+ bfld #0xe0, @byte_src:16, r1l
+ test_cc_clear
+ test_h_gr8 0x5 r1l
+
+ set_ccr_zero
+ bfld #0x3c, @byte_src:16, r1l
+ test_cc_clear
+ test_h_gr8 9 r1l
+
+ set_ccr_zero
+ bfld #0xfe, @byte_src:16, r1l
+ test_cc_clear
+ test_h_gr8 0x52 r1l
+
+ set_ccr_zero
+ bfld #0, @byte_src:16, r1l
+ test_cc_clear
+ test_h_gr8 0 r1l
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 0xa5a5a500 er1
+ test_h_gr32 0xa5a5a5a5 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+bfst_imm8_ind:
+ set_grs_a5a5
+ mov #byte_dst, er2
+
+ ;; bfst rd8, #xx:8, @ers
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #1, @er2
+;;; .word 0x7d20
+;;; .word 0xf901
+
+ test_cc_clear
+ cmp.b #1, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #2, @er2
+;;; .word 0x7d20
+;;; .word 0xf902
+
+ test_cc_clear
+ cmp.b #2, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #7, @er2
+;;; .word 0x7d20
+;;; .word 0xf907
+
+ test_cc_clear
+ cmp.b #5, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0x10, @er2
+;;; .word 0x7d20
+;;; .word 0xf910
+
+ test_cc_clear
+ cmp.b #0x10, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0x20, @er2
+;;; .word 0x7d20
+;;; .word 0xf920
+
+ test_cc_clear
+ cmp.b #0x20, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0xf0, @er2
+;;; .word 0x7d20
+;;; .word 0xf9f0
+
+ test_cc_clear
+ cmp.b #0x50, @byte_dst
+ bne fail1:16
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 0xa5a5a5a5 er1
+ test_h_gr32 byte_dst er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+bfst_imm8_abs32:
+ set_grs_a5a5
+
+ ;; bfst #xx:8, @aa:32, rd8
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0x80, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf980
+
+ test_cc_clear
+ cmp.b #0x80, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0x40, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf940
+
+ test_cc_clear
+ cmp.b #0x40, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0xe0, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf9e0
+
+ test_cc_clear
+ cmp.b #0xa0, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0x3c, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf93c
+
+ test_cc_clear
+ cmp.b #0x14, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0xfe, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf9fe
+
+ test_cc_clear
+ cmp.b #0x4a, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf900
+
+ test_cc_clear
+ cmp.b #0x0, @byte_dst
+ bne fail1:16
+
+ mov.b #0, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0x38, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf938
+
+ test_cc_clear
+ cmp.b #0x28, @byte_dst
+ bne fail1:16
+
+ ;;
+ ;; Now let's do one in which the bits in the destination
+ ;; are appropriately combined with the bits in the source.
+ ;;
+
+ mov.b #0xc3, @byte_dst
+ set_ccr_zero
+ bfst r1l, #0x3c, @byte_dst:32
+;;; .word 0x6a38
+;;; .long byte_dst
+;;; .word 0xf93c
+
+ test_cc_clear
+ cmp.b #0xd7, @byte_dst
+ bne fail1:16
+
+ test_grs_a5a5
+
+.endif
+ pass
+
+ exit 0
+
+fail1: fail
+
--- /dev/null
+# Hitachi H8 testcase 'bra'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+.if (sim_cpu == h8sx)
+ .data
+ .align 4
+disp8: .long tgt_reg8
+disp16: .long tgt_reg16
+disp32: .long tgt_reg32
+dslot: .byte 0
+ .text
+.endif
+
+bra_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; bra dd:8 ; 8-bit displacement
+ bra tgt_8:8
+;;; .word 0x40xx ; where "xx" is tgt_8 - '.'.
+ fail
+
+tgt_8:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu) ; not available in h8/300 mode
+bra_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; bra dd:16 ; 16-bit displacement
+ bra tgt_24:16 ; NOTE: hard-coded to avoid relaxing.
+;;; .word 0x5800
+;;; .word tgt_24 - .
+ fail
+
+tgt_24:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu == h8sx)
+bra_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; bra rn.b ; 8-bit register indirect
+ sub.l #src8, @disp8
+ mov.l @disp8, er5
+;;; bra er5.b
+ .word 0x5955
+src8: fail
+
+tgt_reg8:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+;;; test_h_gr32 tgt_reg8 er5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+bra_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; bra rn.w ; 16-bit register indirect
+ sub.l #src16, @disp16
+ mov.l @disp16, er5
+;;; bra er5.w
+ .word 0x5956
+src16: fail
+
+tgt_reg16:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+;;; test_h_gr32 tgt_reg16 er5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+bra_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; bra ern ; 32-bit register indirect
+ sub.l #src32, @disp32
+ mov.l @disp32, er5
+;;; bra er5.l
+ .word 0x5957
+src32: fail
+
+tgt_reg32:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+;;; test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+bra_s: set_grs_a5a5
+ set_ccr_zero
+
+;;; bra/s tgt_post_delay
+ .word 0x4017
+ ;; The following instruction is in the delay slot, and should execute.
+ mov.b #1, @dslot
+ ;; After this, the next instructions should not execute.
+ fail
+
+tgt_post_delay:
+ test_cc_clear
+ cmp.b #0, @dslot ; Should be non-zero if delay slot executed.
+ bne dslot_ok
+ fail
+
+dslot_ok:
+ test_gr_a5a5 0 ; Make sure all general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+ pass
+ exit 0
+
+
\ No newline at end of file
--- /dev/null
+# Hitachi H8 testcase 'bra/bc'
+# mach(): h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ .data
+byte_src: .byte 0xa5
+
+ start
+
+.if (sim_cpu == h8sx)
+brabc_ind_disp8:
+ set_grs_a5a5
+ mov #byte_src, er1
+ set_ccr_zero
+ ;; bra/bc xx:3, @erd, disp8
+ bra/bc #1, @er1, .Lpass1:8
+;;; .word 0x7c10
+;;; .word 0x4110
+ fail
+.Lpass1:
+ bra/bc #2, @er1, .Lfail1:8
+;;; .word 0x7c10
+;;; .word 0x4202
+ bra .Lpass2
+.Lfail1:
+ fail
+.Lpass2:
+ test_cc_clear
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 byte_src er1
+ test_h_gr32 0xa5a5a5a5 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+brabc_abs16_disp16:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; bra/bc xx:3, @aa:16, disp16
+ bra/bc #1, @byte_src:16, .Lpass3:16
+ fail
+.Lpass3:
+ bra/bc #2, @byte_src:16, .Lfail2:16
+ bra .Lpass4
+.Lfail2:
+ fail
+.Lpass4:
+ test_cc_clear
+ test_grs_a5a5
+
+brabs_ind_disp8:
+ set_grs_a5a5
+ mov #byte_src, er1
+ set_ccr_zero
+ ;; bra/bs xx:3, @erd, disp8
+ bra/bs #2, @er1, .Lpass5:8
+;;; .word 0x7c10
+;;; .word 0x4a10
+ fail
+.Lpass5:
+ bra/bs #1, @er1, .Lfail3:8
+;;; .word 0x7c10
+;;; .word 0x4902
+ bra .Lpass6
+.Lfail3:
+ fail
+.Lpass6:
+ test_cc_clear
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 byte_src er1
+ test_h_gr32 0xa5a5a5a5 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+brabs_abs32_disp16:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; bra/bs xx:3, @aa:32, disp16
+ bra/bs #2, @byte_src:32, .Lpass7:16
+ fail
+.Lpass7:
+ bra/bs #1, @byte_src:32, .Lfail4:16
+ bra .Lpass8
+.Lfail4:
+ fail
+.Lpass8:
+ test_cc_clear
+ test_grs_a5a5
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'bset', 'bclr'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ #
+ # bset xx:3, rd8 ; 7 0 ?xxx rd8
+ # bclr xx:3, rd8 ; 7 2 ?xxx rd8
+ # bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ????
+ # bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ????
+ # bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ????
+ # bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ????
+ # bset reg8, rd8 ; 6 0 rs8 rd8
+ # bclr reg8, rd8 ; 6 2 rs8 rd8
+ # bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ????
+ # bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ????
+ # bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ????
+ # bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ????
+ #
+ # bset/eq xx:3, rd8
+ # bclr/eq xx:3, rd8
+ # bset/ne xx:3, rd8
+ # bclr/ne xx:3, rd8
+
+ .data
+byte_dst: .byte 0
+
+ start
+
+bset_imm3_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+
+ ;; bset xx:3, rd8
+ mov #0, r1l
+ set_ccr_zero
+ bset #0, r1l
+ test_cc_clear
+ test_h_gr8 1 r1l
+
+ set_ccr_zero
+ bset #1, r1l
+ test_cc_clear
+ test_h_gr8 3 r1l
+
+ set_ccr_zero
+ bset #2, r1l
+ test_cc_clear
+ test_h_gr8 7 r1l
+
+ set_ccr_zero
+ bset #3, r1l
+ test_cc_clear
+ test_h_gr8 15 r1l
+
+ set_ccr_zero
+ bset #4, r1l
+ test_cc_clear
+ test_h_gr8 31 r1l
+
+ set_ccr_zero
+ bset #5, r1l
+ test_cc_clear
+ test_h_gr8 63 r1l
+
+ set_ccr_zero
+ bset #6, r1l
+ test_cc_clear
+ test_h_gr8 127 r1l
+
+ set_ccr_zero
+ bset #7, r1l
+ test_cc_clear
+ test_h_gr8 255 r1l
+
+.if (sim_cpu == h8300)
+ test_h_gr16 0xa5ff, r1
+.else
+ test_h_gr32 0xa5a5a5ff er1
+.endif
+
+bclr_imm3_reg8:
+ set_ccr_zero
+ bclr #7, r1l
+ test_cc_clear
+ test_h_gr8 127 r1l
+
+ set_ccr_zero
+ bclr #6, r1l
+ test_cc_clear
+ test_h_gr8 63 r1l
+
+ set_ccr_zero
+ bclr #5, r1l
+ test_cc_clear
+ test_h_gr8 31 r1l
+
+ set_ccr_zero
+ bclr #4, r1l
+ test_cc_clear
+ test_h_gr8 15 r1l
+
+ set_ccr_zero
+ bclr #3, r1l
+ test_cc_clear
+ test_h_gr8 7 r1l
+
+ set_ccr_zero
+ bclr #2, r1l
+ test_cc_clear
+ test_h_gr8 3 r1l
+
+ set_ccr_zero
+ bclr #1, r1l
+ test_cc_clear
+ test_h_gr8 1 r1l
+
+ set_ccr_zero
+ bclr #0, r1l
+ test_cc_clear
+ test_h_gr8 0 r1l
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+.if (sim_cpu == h8300)
+ test_h_gr16 0xa500 r1
+.else
+ test_h_gr32 0xa5a5a500 er1
+.endif
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu)
+bset_imm3_ind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+
+ ;; bset xx:3, @erd
+ mov #byte_dst, er1
+ set_ccr_zero
+ bset #0, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 1 r2l
+
+ set_ccr_zero
+ bset #1, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 3 r2l
+
+ set_ccr_zero
+ bset #2, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 7 r2l
+
+ set_ccr_zero
+ bset #3, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 15 r2l
+
+ set_ccr_zero
+ bset #4, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 31 r2l
+
+ set_ccr_zero
+ bset #5, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 63 r2l
+
+ set_ccr_zero
+ bset #6, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 127 r2l
+
+ set_ccr_zero
+ bset #7, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 255 r2l
+
+.if (sim_cpu == h8300)
+ test_h_gr16 0xa5ff r2
+.else
+ test_h_gr32 0xa5a5a5ff er2
+.endif
+
+bclr_imm3_ind:
+ set_ccr_zero
+ bclr #7, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 127 r2l
+
+ set_ccr_zero
+ bclr #6, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 63 r2l
+
+ set_ccr_zero
+ bclr #5, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 31 r2l
+
+ set_ccr_zero
+ bclr #4, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 15 r2l
+
+ set_ccr_zero
+ bclr #3, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 7 r2l
+
+ set_ccr_zero
+ bclr #2, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 3 r2l
+
+ set_ccr_zero
+ bclr #1, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 1 r2l
+
+ set_ccr_zero
+ bclr #0, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 0 r2l
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+.if (sim_cpu == h8300)
+ test_h_gr16 byte_dst r1
+ test_h_gr16 0xa500 r2
+.else
+ test_h_gr32 byte_dst er1
+ test_h_gr32 0xa5a5a500 er2
+.endif
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+bset_imm3_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+
+ ;; bset xx:3, @aa:16
+ set_ccr_zero
+ bset #0, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 1 r2l
+
+ set_ccr_zero
+ bset #1, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 3 r2l
+
+ set_ccr_zero
+ bset #2, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 7 r2l
+
+ set_ccr_zero
+ bset #3, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 15 r2l
+
+ set_ccr_zero
+ bset #4, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 31 r2l
+
+ set_ccr_zero
+ bset #5, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 63 r2l
+
+ set_ccr_zero
+ bset #6, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 127 r2l
+
+ set_ccr_zero
+ bset #7, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 255 r2l
+
+.if (sim_cpu == h8300)
+ test_h_gr16 0xa5ff r2
+.else
+ test_h_gr32 0xa5a5a5ff er2
+.endif
+
+bclr_imm3_abs16:
+ set_ccr_zero
+ bclr #7, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 127 r2l
+
+ set_ccr_zero
+ bclr #6, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 63 r2l
+
+ set_ccr_zero
+ bclr #5, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 31 r2l
+
+ set_ccr_zero
+ bclr #4, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 15 r2l
+
+ set_ccr_zero
+ bclr #3, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 7 r2l
+
+ set_ccr_zero
+ bclr #2, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 3 r2l
+
+ set_ccr_zero
+ bclr #1, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 1 r2l
+
+ set_ccr_zero
+ bclr #0, @byte_dst:16
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 0 r2l
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+.if (sim_cpu == h8300)
+ test_h_gr16 0xa500 r2
+.else
+ test_h_gr32 0xa5a5a500 er2
+.endif
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+bset_rs8_rd8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+
+ ;; bset rs8, rd8
+ mov #0, r1h
+ mov #0, r1l
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 1 r1l
+
+ mov #1, r1h
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 3 r1l
+
+ mov #2, r1h
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 7 r1l
+
+ mov #3, r1h
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 15 r1l
+
+ mov #4, r1h
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 31 r1l
+
+ mov #5, r1h
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 63 r1l
+
+ mov #6, r1h
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 127 r1l
+
+ mov #7, r1h
+ set_ccr_zero
+ bset r1h, r1l
+ test_cc_clear
+ test_h_gr8 255 r1l
+
+.if (sim_cpu == h8300)
+ test_h_gr16 0x07ff, r1
+.else
+ test_h_gr32 0xa5a507ff er1
+.endif
+
+bclr_rs8_rd8:
+ mov #7, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 127 r1l
+
+ mov #6, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 63 r1l
+
+ mov #5, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 31 r1l
+
+ mov #4, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 15 r1l
+
+ mov #3, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 7 r1l
+
+ mov #2, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 3 r1l
+
+ mov #1, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 1 r1l
+
+ mov #0, r1h
+ set_ccr_zero
+ bclr r1h, r1l
+ test_cc_clear
+ test_h_gr8 0 r1l
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+.if (sim_cpu == h8300)
+ test_h_gr16 0x0000 r1
+.else
+ test_h_gr32 0xa5a50000 er1
+.endif
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu)
+bset_rs8_ind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+
+ ;; bset rs8, @erd
+ mov #byte_dst, er1
+ mov #0, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 1 r2l
+
+ mov #1, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 3 r2l
+
+ mov #2, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 7 r2l
+
+ mov #3, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 15 r2l
+
+ mov #4, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 31 r2l
+
+ mov #5, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 63 r2l
+
+ mov #6, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 127 r2l
+
+ mov #7, r2h
+ set_ccr_zero
+ bset r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 255 r2l
+
+.if (sim_cpu == h8300)
+ test_h_gr16 0x07ff r2
+.else
+ test_h_gr32 0xa5a507ff er2
+.endif
+
+bclr_rs8_ind:
+ mov #7, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 127 r2l
+
+ mov #6, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 63 r2l
+
+ mov #5, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 31 r2l
+
+ mov #4, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 15 r2l
+
+ mov #3, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 7 r2l
+
+ mov #2, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 3 r2l
+
+ mov #1, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 1 r2l
+
+ mov #0, r2h
+ set_ccr_zero
+ bclr r2h, @er1
+ test_cc_clear
+ mov @er1, r2l
+ test_h_gr8 0 r2l
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+.if (sim_cpu == h8300)
+ test_h_gr16 byte_dst r1
+ test_h_gr16 0x0000 r2
+.else
+ test_h_gr32 byte_dst er1
+ test_h_gr32 0xa5a50000 er2
+.endif
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+bset_rs8_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+
+ ;; bset rs8, @aa:32
+ mov #0, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 1 r2l
+
+ mov #1, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 3 r2l
+
+ mov #2, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 7 r2l
+
+ mov #3, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 15 r2l
+
+ mov #4, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 31 r2l
+
+ mov #5, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 63 r2l
+
+ mov #6, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 127 r2l
+
+ mov #7, r2h
+ set_ccr_zero
+ bset r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 255 r2l
+
+.if (sim_cpu == h8300)
+ test_h_gr16 0x07ff r2
+.else
+ test_h_gr32 0xa5a507ff er2
+.endif
+
+bclr_rs8_abs32:
+ mov #7, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 127 r2l
+
+ mov #6, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 63 r2l
+
+ mov #5, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 31 r2l
+
+ mov #4, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 15 r2l
+
+ mov #3, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 7 r2l
+
+ mov #2, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 3 r2l
+
+ mov #1, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 1 r2l
+
+ mov #0, r2h
+ set_ccr_zero
+ bclr r2h, @byte_dst:32
+ test_cc_clear
+ mov @byte_dst, r2l
+ test_h_gr8 0 r2l
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+.if (sim_cpu == h8300)
+ test_h_gr16 0x0000 r2
+.else
+ test_h_gr32 0xa5a50000 er2
+.endif
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu == h8sx)
+bset_eq_imm3_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+
+ ;; bset/eq xx:3, rd8
+ mov #0, @byte_dst
+ set_ccr_zero
+ bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect.
+ test_cc_clear
+ mov @byte_dst, r1l
+ test_h_gr8 0 r1l
+
+ set_ccr_zero
+ orc #4, ccr ; Set zero flag
+ bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed.
+
+ test_neg_clear
+ test_zero_set
+ test_ovf_clear
+ test_carry_clear
+
+ mov @byte_dst, r1l
+ test_h_gr8 1 r1l
+
+bclr_eq_imm3_abs32:
+ mov #1, @byte_dst
+ set_ccr_zero
+ bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect.
+ test_cc_clear
+ mov @byte_dst, r1l
+ test_h_gr8 1 r1l
+
+ set_ccr_zero
+ orc #4, ccr ; Set zero flag
+ bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed.
+ test_neg_clear
+ test_zero_set
+ test_ovf_clear
+ test_carry_clear
+ mov @byte_dst, r1l
+ test_h_gr8 0 r1l
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+.if (sim_cpu == h8300)
+ test_h_gr16 0xa500 r1
+.else
+ test_h_gr32 0xa5a5a500 er1
+.endif
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+ pass
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'cmp.b'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # cmp.b #xx:8, rd ; a rd xxxxxxxx
+ # cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
+ # cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
+ # cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
+ # cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
+ # cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
+ # cmp.b rs, rd ; 1 c rs rd
+ # cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ????
+ # cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs
+ # cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs
+ # cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs
+ # cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs
+ #
+
+ # Coming soon:
+ # ...
+
+.data
+pre_byte: .byte 0
+byte_dest: .byte 0xa5
+post_byte: .byte 0
+
+ start
+
+cmp_b_imm8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.b #xx:8,Rd
+ cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest
+ beq .Leq1
+ fail
+.Leq1: cmp.b #0xa6, r0l
+ blt .Llt1
+ fail
+.Llt1: cmp.b #0xa4, r0l
+ bgt .Lgt1
+ fail
+.Lgt1:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a5 r0 ; r0 unchanged
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+cmp_b_imm8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b #xx:8,@eRd
+ mov #byte_dest, er0
+ cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x7d00
+;;; .word 0xa0a5
+ beq .Leq2
+ fail
+.Leq2: set_ccr_zero
+ cmp.b #0xa6, @er0
+;;; .word 0x7d00
+;;; .word 0xa0a6
+ blt .Llt2
+ fail
+.Llt2: set_ccr_zero
+ cmp.b #0xa4, @er0
+;;; .word 0x7d00
+;;; .word 0xa0a4
+ bgt .Lgt2
+ fail
+.Lgt2:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L2
+ fail
+.L2:
+
+cmp_b_imm8_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b #xx:8,@eRd+
+ mov #byte_dest, er0
+ cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0xa0a5
+ beq .Leq3
+ fail
+.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one
+ mov #byte_dest, er0
+ set_ccr_zero
+ cmp.b #0xa6, @er0+
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0xa0a6
+ blt .Llt3
+ fail
+.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one
+ mov #byte_dest, er0
+ set_ccr_zero
+ cmp.b #0xa4, @er0+
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0xa0a4
+ bgt .Lgt3
+ fail
+.Lgt3:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte er0 ; er0 contains address plus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L3
+ fail
+.L3:
+
+cmp_b_imm8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b #xx:8,@eRd-
+ mov #byte_dest, er0
+ cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0xa0a5
+ beq .Leq4
+ fail
+.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ mov #byte_dest, er0
+ set_ccr_zero
+ cmp.b #0xa6, @er0-
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0xa0a6
+ blt .Llt4
+ fail
+.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ mov #byte_dest, er0
+ set_ccr_zero
+ cmp.b #0xa4, @er0-
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0xa0a4
+ bgt .Lgt4
+ fail
+.Lgt4:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L4
+ fail
+.L4:
+
+cmp_b_imm8_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b #xx:8,@+eRd
+ mov #pre_byte, er0
+ cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0xa0a5
+ beq .Leq5
+ fail
+.Leq5: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #pre_byte, er0
+ set_ccr_zero
+ cmp.b #0xa6, @+er0
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0xa0a6
+ blt .Llt5
+ fail
+.Llt5: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #pre_byte, er0
+ set_ccr_zero
+ cmp.b #0xa4, @+er0
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0xa0a4
+ bgt .Lgt5
+ fail
+.Lgt5:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L5
+ fail
+.L5:
+
+cmp_b_imm8_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b #xx:8,@-eRd
+ mov #post_byte, er0
+ cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0xa0a5
+ beq .Leq6
+ fail
+.Leq6: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #post_byte, er0
+ set_ccr_zero
+ cmp.b #0xa6, @-er0
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0xa0a6
+ blt .Llt6
+ fail
+.Llt6: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #post_byte, er0
+ set_ccr_zero
+ cmp.b #0xa4, @-er0
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0xa0a4
+ bgt .Lgt6
+ fail
+.Lgt6:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L6
+ fail
+.L6:
+
+
+.endif
+
+cmp_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.b Rs,Rd
+ mov.b #0xa5, r0h
+ cmp.b r0h, r0l ; Reg8 src, reg8 dst
+ beq .Leq7
+ fail
+.Leq7: mov.b #0xa6, r0h
+ cmp.b r0h, r0l
+ blt .Llt7
+ fail
+.Llt7: mov.b #0xa4, r0h
+ cmp.b r0h, r0l
+ bgt .Lgt7
+ fail
+.Lgt7:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa4a5 r0 ; r0l unchanged.
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+cmp_b_reg8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b rs8,@eRd ; cmp reg8 to register indirect
+ mov #byte_dest, er0
+ mov #0xa5, r1l
+ cmp.b r1l, @er0 ; reg8 src, reg indirect dest
+;;; .word 0x7d00
+;;; .word 0x1c90
+ beq .Leq8
+ fail
+.Leq8: set_ccr_zero
+ mov #0xa6, r1l
+ cmp.b r1l, @er0
+;;; .word 0x7d00
+;;; .word 0x1c90
+ blt .Llt8
+ fail
+.Llt8: set_ccr_zero
+ mov #0xa4, r1l
+ cmp.b r1l, @er0
+;;; .word 0x7d00
+;;; .word 0x1c90
+ bgt .Lgt8
+ fail
+.Lgt8:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (no change).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L8
+ fail
+.L8:
+
+cmp_b_reg8_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b reg8,@eRd+
+ mov #byte_dest, er0
+ mov #0xa5, r1l
+ cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst
+;;; .word 0x0179
+;;; .word 0x8029
+ beq .Leq9
+ fail
+.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one
+ mov #byte_dest er0
+ mov #0xa6, r1l
+ set_ccr_zero
+ cmp.b r1l, @er0+
+;;; .word 0x0179
+;;; .word 0x8029
+ blt .Llt9
+ fail
+.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one
+ mov #byte_dest er0
+ mov #0xa4, r1l
+ set_ccr_zero
+ cmp.b r1l, @er0+
+;;; .word 0x0179
+;;; .word 0x8029
+ bgt .Lgt9
+ fail
+.Lgt9:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte er0 ; er0 contains address plus one
+ test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L9
+ fail
+.L9:
+
+cmp_b_reg8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b reg8,@eRd-
+ mov #byte_dest, er0
+ mov #0xa5, r1l
+ cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst
+;;; .word 0x0179
+;;; .word 0xa029
+ beq .Leq10
+ fail
+.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ mov #byte_dest er0
+ mov #0xa6, r1l
+ set_ccr_zero
+ cmp.b r1l, @er0-
+;;; .word 0x0179
+;;; .word 0xa029
+ blt .Llt10
+ fail
+.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ mov #byte_dest er0
+ mov #0xa4, r1l
+ set_ccr_zero
+ cmp.b r1l, @er0-
+;;; .word 0x0179
+;;; .word 0xa029
+ bgt .Lgt10
+ fail
+.Lgt10:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L10
+ fail
+.L10:
+
+cmp_b_reg8_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b reg8,@+eRd
+ mov #pre_byte, er0
+ mov #0xa5, r1l
+ cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst
+;;; .word 0x0179
+;;; .word 0x9029
+ beq .Leq11
+ fail
+.Leq11: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #pre_byte er0
+ mov #0xa6, r1l
+ set_ccr_zero
+ cmp.b r1l, @+er0
+;;; .word 0x0179
+;;; .word 0x9029
+ blt .Llt11
+ fail
+.Llt11: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #pre_byte er0
+ mov #0xa4, r1l
+ set_ccr_zero
+ cmp.b r1l, @+er0
+;;; .word 0x0179
+;;; .word 0x9029
+ bgt .Lgt11
+ fail
+.Lgt11:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L11
+ fail
+.L11:
+
+cmp_b_reg8_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; cmp.b reg8,@-eRd
+ mov #post_byte, er0
+ mov #0xa5, r1l
+ cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst
+;;; .word 0x0179
+;;; .word 0xb029
+ beq .Leq12
+ fail
+.Leq12: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #post_byte er0
+ mov #0xa6, r1l
+ set_ccr_zero
+ cmp.b r1l, @-er0
+;;; .word 0x0179
+;;; .word 0xb029
+ blt .Llt12
+ fail
+.Llt12: test_h_gr32 byte_dest er0 ; er0 contains destination address
+ mov #post_byte er0
+ mov #0xa4, r1l
+ set_ccr_zero
+ cmp.b r1l, @-er0
+;;; .word 0x0179
+;;; .word 0xb029
+ bgt .Lgt12
+ fail
+.Lgt12:
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the cmp to memory (memory unchanged).
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L12
+ fail
+.L12:
+
+.endif
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'cmp.w'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
+cmp_l_imm3: ;
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.l #xx:3,eRd ; Immediate 3-bit operand
+ mov.l #5, er0
+ cmp.l #5, er0
+ beq eq3
+ fail
+eq3:
+ cmp.l #6, er0
+ blt lt3
+ fail
+lt3:
+ cmp.l #4, er0
+ bgt gt3
+ fail
+gt3:
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0x00000005 er0 ; er0 unchanged
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+cmp_l_imm16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.l #xx:8,Rd
+ cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand
+ beq eqi
+ fail
+eqi: cmp.l #0xa5a5a5a6, er0
+ blt lti
+ fail
+lti: cmp.l #0xa5a5a5a4, er0
+ bgt gti
+ fail
+gti:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+cmp_w_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.l Rs,Rd
+ mov.l #0xa5a5a5a5, er1
+ cmp.l er1, er0 ; Register operand
+ beq eqr
+ fail
+eqr: mov.l #0xa5a5a5a6, er1
+ cmp.l er1, er0
+ blt ltr
+ fail
+ltr: mov.l #0xa5a5a5a4, er1
+ cmp.l er1, er0
+ bgt gtr
+ fail
+gtr:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
+ test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'cmp.w'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
+cmp_w_imm3: ;
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.w #xx:3,Rd ; Immediate 3-bit operand
+ mov.w #5, r0
+ cmp.w #5, r0
+ beq eq3
+ fail
+eq3:
+ cmp.w #6, r0
+ blt lt3
+ fail
+lt3:
+ cmp.w #4, r0
+ bgt gt3
+ fail
+gt3:
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr32 0xa5a50005 er0 ; er0 unchanged
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+cmp_w_imm16: ; cmp.w immediate not available in h8300 mode.
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.w #xx:8,Rd
+ cmp.w #0xa5a5, r0 ; Immediate 16-bit operand
+ beq eqi
+ fail
+eqi: cmp.w #0xa5a6, r0
+ blt lti
+ fail
+lti: cmp.w #0xa5a4, r0
+ bgt gti
+ fail
+gti:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a5 r0 ; r0 unchanged
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+cmp_w_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; cmp.w Rs,Rd
+ mov.w #0xa5a5, r1
+ cmp.w r1, r0 ; Register operand
+ beq eqr
+ fail
+eqr: mov.w #0xa5a6, r1
+ cmp.w r1, r0
+ blt ltr
+ fail
+ltr: mov.w #0xa5a4, r1
+ cmp.w r1, r0
+ bgt gtr
+ fail
+gtr:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a5 r0 ; r0 unchanged.
+ test_h_gr16 0xa5a4 r1 ; r1 unchanged.
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
+ test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'daa'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+daa_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; daa Rd
+ daa r0l ; register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr8 5 r0l
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'das'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+das_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; das Rd
+ das r0l ; register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'dec.b, dec.w, dec.l'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+dec_b:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; dec.b Rd
+ dec.b r0h ; Decrement 8-bit reg by one
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa4a5 r0 ; dec result: a4|a5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+dec_w_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; dec.w #1, Rd
+ dec.w #1, r0 ; Decrement 16-bit reg by one
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a4 r0 ; dec result: a5|a4
+
+ test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+dec_w_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; dec.w #2, Rd
+ dec.w #2, r0 ; Decrement 16-bit reg by two
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a3 r0 ; dec result: a5|a3
+
+ test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+dec_l_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; dec.l #1, eRd
+ dec.l #1, er0 ; Decrement 32-bit reg by one
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+dec_l_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; dec.l #2, eRd
+ dec.l #2, er0 ; Decrement 32-bit reg by two
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'exts.l, extu.l'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+ .align 4
+pos: .long 0xffff0001
+neg: .long 0x00008000
+
+pos2: .long 0xffffff01
+neg2: .long 0x00000080
+
+ .text
+
+exts_l_reg32_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l ern32
+ mov.w #1, r0
+ exts.l er0
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 0x00000001 er0 ; result of sign extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+exts_l_reg32_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l ern32
+ mov.w #0xffff, r0
+ exts.l er0
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xffffffff er0 ; result of sign extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+extu_l_reg32_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l ern32
+ mov.w #0xffff, r0
+ extu.l er0
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 0x0000ffff er0 ; result of zero extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+exts_l_ind_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @ern32
+ mov.l #pos, er1
+ exts.l @er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos
+ beq .Lslindp
+ fail
+.Lslindp:
+ mov.l #0xffff0001, @pos ; Restore initial value
+
+exts_l_ind_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @ern32
+ mov.l #neg, er1
+ exts.l @er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffff8000, @neg
+ beq .Lslindn
+ fail
+.Lslindn:
+;;; Note: leave the value as 0xffff8000, so that extu has work to do.
+
+extu_l_ind_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @ern32
+ mov.l #neg, er1
+ extu.l @er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Lulindn
+ fail
+.Lulindn:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+exts_l_postinc_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @ern32+
+ mov.l #pos, er1
+ exts.l @er1+
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos+4 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos
+ beq .Lslpostincp
+ fail
+.Lslpostincp:
+ mov.l #0xffff0001, @pos ; Restore initial value
+
+exts_l_postinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @ern32+
+ mov.l #neg, er1
+ exts.l @er1+
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg+4 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffff8000, @neg
+ beq .Lslpostincn
+ fail
+.Lslpostincn:
+;;; Note: leave the value as 0xffff8000, so that extu has work to do.
+
+extu_l_postinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @ern32+
+ mov.l #neg, er1
+ extu.l @er1+
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg+4 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Lulpostincn
+ fail
+.Lulpostincn:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+exts_l_postdec_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @ern32-
+ mov.l #pos, er1
+ exts.l @er1-
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos-4 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos
+ beq .Lslpostdecp
+ fail
+.Lslpostdecp:
+ mov.l #0xffff0001, @pos ; Restore initial value
+
+exts_l_postdec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @ern32-
+ mov.l #neg, er1
+ exts.l @er1-
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg-4 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffff8000, @neg
+ beq .Lslpostdecn
+ fail
+.Lslpostdecn:
+;;; Note: leave the value as 0xffff8000, so that extu has work to do.
+
+extu_l_postdec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @ern32-
+ mov.l #neg, er1
+ extu.l @er1-
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg-4 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Lulpostdecn
+ fail
+.Lulpostdecn:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+exts_l_preinc_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @+ern32
+ mov.l #pos-4, er1
+ exts.l @+er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos
+ beq .Lslpreincp
+ fail
+.Lslpreincp:
+ mov.l #0xffff0001, @pos ; Restore initial value
+
+exts_l_preinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @+ern32
+ mov.l #neg-4, er1
+ exts.l @+er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffff8000, @neg
+ beq .Lslpreincn
+ fail
+.Lslpreincn:
+;;; Note: leave the value as 0xffff8000, so that extu has work to do.
+
+extu_l_preinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @+ern32
+ mov.l #neg-4, er1
+ extu.l @+er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Lulpreincn
+ fail
+.Lulpreincn:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+exts_l_predec_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @-ern32
+ mov.l #pos+4, er1
+ exts.l @-er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos
+ beq .Lslpredecp
+ fail
+.Lslpredecp:
+ mov.l #0xffff0001, @pos ; Restore initial value
+
+exts_l_predec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l @-ern32
+ mov.l #neg+4, er1
+ exts.l @-er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffff8000, @neg
+ beq .Lslpredecn
+ fail
+.Lslpredecn:
+;;; Note: leave the value as 0xffff8000, so that extu has work to do.
+
+extu_l_predec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @-ern32
+ mov.l #neg+4, er1
+ extu.l @-er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Lulpredecn
+ fail
+.Lulpredecn:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+extu_l_disp2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @(dd:2, ern32)
+ mov.l #neg-2, er1
+ extu.l @(2:2, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg-2 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Luldisp2n
+ fail
+.Luldisp2n:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+extu_l_disp16_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @(dd:16, ern32)
+ mov.l #neg-44, er1
+ extu.l @(44:16, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg-44 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Luldisp16n
+ fail
+.Luldisp16n:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+extu_l_disp32_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @(dd:32, ern32)
+ mov.l #neg+444, er1
+ extu.l @(-444:32, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg+444 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Luldisp32n
+ fail
+.Luldisp32n:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+extu_l_abs16_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @aa:16
+ extu.l @neg:16
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Lulabs16n
+ fail
+.Lulabs16n:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+extu_l_abs32_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l @aa:32
+ extu.l @neg:32
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00008000, @neg
+ beq .Lulabs32n
+ fail
+.Lulabs32n:
+;;; Note: leave the value as 0x00008000, so that extu has work to do.
+
+
+
+ #
+ # exts #2, nn
+ #
+
+exts_l_reg32_2_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, ern32
+ mov.b #1, r0l
+ exts.l #2, er0
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 0x00000001 er0 ; result of sign extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+exts_l_reg32_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, ern32
+ mov.b #0xff, r0l
+ exts.l #2, er0
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_ovf_clear
+ test_zero_clear
+ test_carry_clear
+
+ test_h_gr32 0xffffffff er0 ; result of sign extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+extu_l_reg32_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, ern32
+ mov.b #0xff, r0l
+ extu.l #2, er0
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 0x000000ff er0 ; result of zero extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+exts_l_ind_2_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @ern32
+ mov.l #pos2, er1
+ exts.l #2, @er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos2 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos2
+ beq .Lslindp2
+ fail
+.Lslindp2:
+ mov.l #0xffffff01, @pos2 ; Restore initial value
+
+exts_l_ind_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @ern32
+ mov.l #neg2, er1
+ exts.l #2, @er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_ovf_clear
+ test_zero_clear
+ test_carry_clear
+
+ test_h_gr32 neg2 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffffff80, @neg2
+ beq .Lslindn2
+ fail
+.Lslindn2:
+;;; Note: leave the value as 0xffffff80, so that extu has work to do.
+
+extu_l_ind_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @ern32
+ mov.l #neg2, er1
+ extu.l #2, @er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Lulindn2
+ fail
+.Lulindn2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+exts_l_postinc_2_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @ern32+
+ mov.l #pos2, er1
+ exts.l #2, @er1+
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos2+4 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos2
+ beq .Lslpostincp2
+ fail
+.Lslpostincp2:
+ mov.l #0xffffff01, @pos2 ; Restore initial value
+
+exts_l_postinc_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @ern32+
+ mov.l #neg2, er1
+ exts.l #2, @er1+
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_ovf_clear
+ test_zero_clear
+ test_carry_clear
+
+ test_h_gr32 neg2+4 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffffff80, @neg2
+ beq .Lslpostincn2
+ fail
+.Lslpostincn2:
+;;; Note: leave the value as 0xffffff80, so that extu has work to do.
+
+extu_l_postinc_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @ern32+
+ mov.l #neg2, er1
+ extu.l #2, @er1+
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2+4 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Lulpostincn2
+ fail
+.Lulpostincn2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+exts_l_postdec_2_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @ern32-
+ mov.l #pos2, er1
+ exts.l #2, @er1-
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos2-4 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos2
+ beq .Lslpostdecp2
+ fail
+.Lslpostdecp2:
+ mov.l #0xffffff01, @pos2 ; Restore initial value
+
+exts_l_postdec_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @ern32-
+ mov.l #neg2, er1
+ exts.l #2, @er1-
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_ovf_clear
+ test_zero_clear
+ test_carry_clear
+
+ test_h_gr32 neg2-4 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffffff80, @neg2
+ beq .Lslpostdecn2
+ fail
+.Lslpostdecn2:
+;;; Note: leave the value as 0xffffff80, so that extu has work to do.
+
+extu_l_postdec_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @ern32-
+ mov.l #neg2, er1
+ extu.l #2, @er1-
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2-4 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Lulpostdecn2
+ fail
+.Lulpostdecn2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+exts_l_preinc_2_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @+ern32
+ mov.l #pos2-4, er1
+ exts.l #2, @+er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos2 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos2
+ beq .Lslpreincp2
+ fail
+.Lslpreincp2:
+ mov.l #0xffffff01, @pos2 ; Restore initial value
+
+exts_l_preinc_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @+ern32
+ mov.l #neg2-4, er1
+ exts.l #2, @+er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_ovf_clear
+ test_zero_clear
+ test_carry_clear
+
+ test_h_gr32 neg2 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffffff80, @neg2
+ beq .Lslpreincn2
+ fail
+.Lslpreincn2:
+;;; Note: leave the value as 0xffffff80, so that extu has work to do.
+
+extu_l_preinc_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @+ern32
+ mov.l #neg2-4, er1
+ extu.l #2, @+er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Lulpreincn2
+ fail
+.Lulpreincn2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+exts_l_predec_2_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @-ern32
+ mov.l #pos2+4, er1
+ exts.l #2, @-er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos2 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000001, @pos2
+ beq .Lslpredecp2
+ fail
+.Lslpredecp2:
+ mov.l #0xffffff01, @pos2 ; Restore initial value
+
+exts_l_predec_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.l #2, @-ern32
+ mov.l #neg2+4, er1
+ exts.l #2, @-er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_ovf_clear
+ test_zero_clear
+ test_carry_clear
+
+ test_h_gr32 neg2 er1 ; result of sign extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0xffffff80, @neg2
+ beq .Lslpredecn2
+ fail
+.Lslpredecn2:
+;;; Note: leave the value as 0xffffff80, so that extu has work to do.
+
+extu_l_predec_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @-ern32
+ mov.l #neg2+4, er1
+ extu.l #2, @-er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Lulpredecn2
+ fail
+.Lulpredecn2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+extu_l_disp2_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @(dd:2, ern32)
+ mov.l #neg2-2, er1
+ extu.l #2, @(2:2, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2-2 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Luldisp2n2
+ fail
+.Luldisp2n2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+extu_l_disp16_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @(dd:16, ern32)
+ mov.l #neg2-44, er1
+ extu.l #2, @(44:16, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2-44 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Luldisp16n2
+ fail
+.Luldisp16n2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+extu_l_disp32_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @(dd:32, ern32)
+ mov.l #neg2+444, er1
+ extu.l #2, @(-444:32, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg2+444 er1 ; result of zero extend
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Luldisp32n2
+ fail
+.Luldisp32n2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+extu_l_abs16_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @aa:16
+ extu.l #2, @neg2:16
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Lulabs16n2
+ fail
+.Lulabs16n2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+extu_l_abs32_2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.l #2, @aa:32
+ extu.l #2, @neg2:32
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.l #0x00000080, @neg2
+ beq .Lulabs32n2
+ fail
+.Lulabs32n2:
+;;; Note: leave the value as 0x00000080, like it started out.
+
+.endif
+
+ pass
+
+ exit 0
+
+
+
+
--- /dev/null
+# Hitachi H8 testcase 'exts.w, extu.w'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+ .align 2
+pos: .word 0xff01
+neg: .word 0x0080
+
+ .text
+
+exts_w_reg16_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w rn16
+ mov.b #1, r0l
+ exts.w r0
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 0xa5a50001 er0 ; result of sign extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+exts_w_reg16_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w rn16
+ mov.b #0xff, r0l
+ exts.w r0
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5ffff er0 ; result of sign extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+extu_w_reg16_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w rn16
+ mov.b #0xff, r0l
+ extu.w r0
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 0xa5a500ff er0 ; result of zero extend
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+exts_w_ind_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @ern
+ mov.l #pos, er1
+ exts.w @er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0001, @pos
+ beq .Lswindp
+ fail
+.Lswindp:
+ mov.w #0xff01, @pos ; Restore initial value
+
+exts_w_ind_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @ern
+ mov.l #neg, er1
+ exts.w @er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0xff80, @neg
+ beq .Lswindn
+ fail
+.Lswindn:
+ ;; Note: leave the value as 0xff80, so that extu has work to do.
+
+extu_w_ind_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @ern
+ mov.l #neg, er1
+ extu.w @er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwindn
+ fail
+.Luwindn:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+exts_w_postinc_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @ern+
+ mov.l #pos, er1
+ exts.w @er1+
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0001, @pos
+ beq .Lswpostincp
+ fail
+.Lswpostincp:
+ mov.w #0xff01, @pos ; Restore initial value
+
+exts_w_postinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @ern+
+ mov.l #neg, er1
+ exts.w @er1+
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg+2 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0xff80, @neg
+ beq .Lswpostincn
+ fail
+.Lswpostincn:
+ ;; Note: leave the value as 0xff80, so that extu has work to do.
+
+extu_w_postinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @ern+
+ mov.l #neg, er1
+ extu.w @er1+
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg+2 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwpostincn
+ fail
+.Luwpostincn:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+exts_w_postdec_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @ern-
+ mov.l #pos, er1
+ exts.w @er1-
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0001, @pos
+ beq .Lswpostdecp
+ fail
+.Lswpostdecp:
+ mov.w #0xff01, @pos ; Restore initial value
+
+exts_w_postdec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @ern-
+ mov.l #neg, er1
+ exts.w @er1-
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg-2 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0xff80, @neg
+ beq .Lswpostdecn
+ fail
+.Lswpostdecn:
+ ;; Note: leave the value as 0xff80, so that extu has work to do.
+
+extu_w_postdec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @ern-
+ mov.l #neg, er1
+ extu.w @er1-
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg-2 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwpostdecn
+ fail
+.Luwpostdecn:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+exts_w_preinc_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @+ern
+ mov.l #pos-2, er1
+ exts.w @+er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos er1 ; er1 still contains target address plus 2
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0001, @pos
+ beq .Lswpreincp
+ fail
+.Lswpreincp:
+ mov.w #0xff01, @pos ; Restore initial value
+
+exts_w_preinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @+ern
+ mov.l #neg-2, er1
+ exts.w @+er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0xff80, @neg
+ beq .Lswpreincn
+ fail
+.Lswpreincn:
+ ;; Note: leave the value as 0xff80, so that extu has work to do.
+
+extu_w_preinc_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @+ern
+ mov.l #neg-2, er1
+ extu.w @+er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwpreincn
+ fail
+.Luwpreincn:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+exts_w_predec_p:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @-ern
+ mov.l #pos+2, er1
+ exts.w @-er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 pos er1 ; er1 still contains target address plus 2
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0001, @pos
+ beq .Lswpredecp
+ fail
+.Lswpredecp:
+ mov.w #0xff01, @pos ; Restore initial value
+
+exts_w_predec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; exts.w @-ern
+ mov.l #neg+2, er1
+ exts.w @-er1
+
+ ;; Test ccr H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0xff80, @neg
+ beq .Lswpredecn
+ fail
+.Lswpredecn:
+ ;; Note: leave the value as 0xff80, so that extu has work to do.
+
+extu_w_predec_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @-ern
+ mov.l #neg+2, er1
+ extu.w @-er1
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwpredecn
+ fail
+.Luwpredecn:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+extu_w_disp2_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @(dd:2, ern)
+ mov.l #neg-1, er1
+ extu.w @(1:2, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg-1 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwdisp2n
+ fail
+.Luwdisp2n:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+extu_w_disp16_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @(dd:16, ern)
+ mov.l #neg-44, er1
+ extu.w @(44:16, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg-44 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwdisp16n
+ fail
+.Luwdisp16n:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+extu_w_disp32_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @(dd:32, ern)
+ mov.l #neg+444, er1
+ extu.w @(-444:32, er1)
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_h_gr32 neg+444 er1 ; er1 still contains target address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwdisp32n
+ fail
+.Luwdisp32n:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+extu_w_abs16_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @aa:16
+ extu.w @neg:16
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwabs16n
+ fail
+.Luwabs16n:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+extu_w_abs32_n:
+ set_grs_a5a5
+ set_ccr_zero
+ ;; extu.w @aa:32
+ extu.w @neg:32
+
+ ;; Test ccr H=0 N=0 Z=0 V=0 C=0
+ test_cc_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ cmp.w #0x0080, @neg
+ beq .Luwabs32n
+ fail
+.Luwabs32n:
+ ;; Note: leave the value as 0x0080, like it started out.
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'inc, inc.w, inc.l'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+inc_b:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; inc.b Rd
+ inc.b r0h ; Increment 8-bit reg by one
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa6a5 r0 ; inc result: a6|a5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+inc_w_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; inc.w #1, Rd
+ inc.w #1, r0 ; Increment 16-bit reg by one
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a6 r0 ; inc result: a5|a6
+
+ test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+inc_w_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; inc.w #2, Rd
+ inc.w #2, r0 ; Increment 16-bit reg by two
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a7 r0 ; inc result: a5|a7
+
+ test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+inc_l_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; inc.l #1, eRd
+ inc.l #1, er0 ; Increment 32-bit reg by one
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+inc_l_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; inc.l #2, eRd
+ inc.l #2, er0 ; Increment 32-bit reg by two
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'jmp'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if 0 ; this one isn't right -- it's an indirect
+jmp_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; jmp @aa:8 ; 8-bit displacement
+ jmp @@.Ltgt_8:8
+ fail
+
+.Ltgt_8:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+jmp_24:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; jmp @aa:24 ; 24-bit address
+ jmp @.Ltgt_24:24
+ fail
+
+.Ltgt_24:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx
+jmp_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; jmp @ern ; register indirect
+ mov.l #.Ltgt_reg, er5
+ jmp @er5
+ fail
+
+.Ltgt_reg:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_h_gr32 .Ltgt_reg er5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu == h8sx)
+jmp_32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; jmp @aa:32 ; 32-bit address
+; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing
+ .word 0x5908
+ .long .Ltgt_32
+ fail
+
+.Ltgt_32:
+ test_cc_clear
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+ pass
+ exit 0
+
+
\ No newline at end of file
--- /dev/null
+# Hitachi H8 testcase 'ldc'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+ .data
+byte_pre:
+ .byte 0
+byte_src:
+ .byte 0xff
+byte_post:
+ .byte 0
+
+ start
+
+ldc_imm8_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0xff, ccr ; set all ccr flags high, immediate operand
+ bcs .L1 ; carry flag set?
+ fail
+.L1: bvs .L2 ; overflow flag set?
+ fail
+.L2: beq .L3 ; zero flag set?
+ fail
+.L3: bmi .L4 ; neg flag set?
+ fail
+.L4:
+ ldc #0, ccr ; set all ccr flags low, immediate operand
+ bcc .L5 ; carry flag clear?
+ fail
+.L5: bvc .L6 ; overflow flag clear?
+ fail
+.L6: bne .L7 ; zero flag clear?
+ fail
+.L7: bpl .L8 ; neg flag clear?
+ fail
+.L8:
+ test_cc_clear
+ test_grs_a5a5
+
+ldc_reg8_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #0xff, r0h
+ ldc r0h, ccr ; set all ccr flags high, reg operand
+ bcs .L11 ; carry flag set?
+ fail
+.L11: bvs .L12 ; overflow flag set?
+ fail
+.L12: beq .L13 ; zero flag set?
+ fail
+.L13: bmi .L14 ; neg flag set?
+ fail
+.L14:
+ mov #0, r0h
+ ldc r0h, ccr ; set all ccr flags low, reg operand
+ bcc .L15 ; carry flag clear?
+ fail
+.L15: bvc .L16 ; overflow flag clear?
+ fail
+.L16: bne .L17 ; zero flag clear?
+ fail
+.L17: bpl .L18 ; neg flag clear?
+ fail
+.L18:
+ test_cc_clear
+ test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
+ldc_imm8_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ ldc #0x87, exr ; set exr to 0x87
+
+ stc exr, r0l ; retrieve and check exr value
+ cmp.b #0x87, r0l
+ beq .L19
+ fail
+.L19:
+ test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_reg8_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ mov #0x87, r0h
+ ldc r0h, exr ; set exr to 0x87
+
+ stc exr, r0l ; retrieve and check exr value
+ cmp.b #0x87, r0l
+ beq .L21
+ fail
+.L21:
+ test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_abs16_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc @byte_src:16, ccr ; abs16 src
+ stc ccr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_abs16_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ ldc @byte_src:16, exr ; abs16 src
+ stc exr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_abs32_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc @byte_src:32, ccr ; abs32 src
+ stc ccr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_abs32_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ ldc @byte_src:32, exr ; abs32 src
+ stc exr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_disp16_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_pre, er1
+ ldc @(1:16, er1), ccr ; disp16 src
+ stc ccr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
+ test_h_gr32 byte_pre, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_disp16_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ mov #byte_post, er1
+ ldc @(-1:16, er1), exr ; disp16 src
+ stc exr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
+ test_h_gr32 byte_post, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_disp32_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_pre, er1
+ ldc @(1:32, er1), ccr ; disp32 src
+ stc ccr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
+ test_h_gr32 byte_pre, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_disp32_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ mov #byte_post, er1
+ ldc @(-1:32, er1), exr ; disp16 src
+ stc exr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
+ test_h_gr32 byte_post, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_postinc_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_src, er1
+ ldc @er1+, ccr ; postinc src
+ stc ccr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
+ test_h_gr32 byte_post, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_postinc_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ mov #byte_src, er1
+ ldc @er1+, exr ; postinc src
+ stc exr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
+ test_h_gr32 byte_post, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_ind_ccr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_src, er1
+ ldc @er1, ccr ; postinc src
+ stc ccr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
+ test_h_gr32 byte_src, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_ind_exr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0, exr
+ mov #byte_src, er1
+ ldc @er1, exr ; postinc src
+ stc exr, r0l ; copy into general reg
+
+ test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
+ test_h_gr32 byte_src, er1 ; er1 still contains address
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
+ldc_reg_sbr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #0xaaaaaaaa, er0
+ ldc er0, sbr ; set sbr to 0xaaaaaaaa
+ stc sbr, er1 ; retreive and check sbr value
+
+ test_h_gr32 0xaaaaaaaa er1
+ test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ldc_reg_vbr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #0xaaaaaaaa, er0
+ ldc er0, vbr ; set sbr to 0xaaaaaaaa
+ stc vbr, er1 ; retreive and check sbr value
+
+ test_h_gr32 0xaaaaaaaa er1
+ test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'mac'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ .data
+src1: .word 0
+src2: .word 0
+
+array: .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+ .word 0x7fff
+
+ start
+
+.if (sim_cpu)
+_clrmac:
+ set_grs_a5a5
+ set_ccr_zero
+ clrmac
+ test_cc_clear
+ test_grs_a5a5
+ ;; Now see if the mac is actually clear...
+ stmac mach, er0
+ test_zero_set
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 0 er0
+ stmac macl, er1
+ test_zero_set
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 0 er1
+
+ld_stmac:
+ set_grs_a5a5
+ sub.l er2, er2
+ set_ccr_zero
+ ldmac er1, macl
+ stmac macl, er2
+ test_ovf_clear
+ test_carry_clear
+ ;; neg and zero are undefined
+ test_h_gr32 0xa5a5a5a5 er2
+
+ sub.l er2, er2
+ set_ccr_zero
+ ldmac er1, mach
+ stmac mach, er2
+ test_ovf_clear
+ test_carry_clear
+ ;; neg and zero are undefined
+ test_h_gr32 0x0001a5 er2
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mac_2x2:
+ set_grs_a5a5
+ mov.w #2, r1
+ mov.w r1, @src1
+ mov.w #2, r2
+ mov.w r2, @src2
+ mov #src1, er1
+ mov #src2, er2
+ set_ccr_zero
+ clrmac
+ mac @er1+, @er2+
+ test_cc_clear
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 src1+2 er1
+ test_h_gr32 src2+2 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+ stmac macl, er0
+ test_zero_clear
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 4 er0
+
+ stmac mach, er0
+ test_zero_clear
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 0 er0
+
+mac_same_reg_2x4:
+ ;; Use same reg for src and dst. Should be incremented twice,
+ ;; and fetch values from consecutive locations.
+ set_grs_a5a5
+ mov.w #2, r1
+ mov.w r1, @src1
+ mov.w #4, r2
+ mov.w r2, @src2
+ mov #src1, er1
+
+ set_ccr_zero
+ clrmac
+ mac @er1+, @er1+ ; same register for src and dst
+ test_cc_clear
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 src1+4 er1
+ test_h_gr32 0xa5a50004 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+ stmac macl, er0
+ test_zero_clear
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 8 er0
+
+ stmac mach, er0
+ test_zero_clear
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 0 er0
+
+mac_0x0:
+ set_grs_a5a5
+ mov.w #0, r1
+ mov.w r1, @src1
+ mov.w #0, r2
+ mov.w r2, @src2
+ mov #src1, er1
+ mov #src2, er2
+ set_ccr_zero
+ clrmac
+ mac @er1+, @er2+
+ test_cc_clear
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 src1+2 er1
+ test_h_gr32 src2+2 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+ stmac macl, er0
+ test_zero_set ; zero flag is set
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 0 er0 ; result is zero
+
+ stmac mach, er0
+ test_zero_set
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 0 er0
+
+mac_neg2x2:
+ set_grs_a5a5
+ mov.w #-2, r1
+ mov.w r1, @src1
+ mov.w #2, r2
+ mov.w r2, @src2
+ mov #src1, er1
+ mov #src2, er2
+ set_ccr_zero
+ clrmac
+ mac @er1+, @er2+
+ test_cc_clear
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 src1+2 er1
+ test_h_gr32 src2+2 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+ stmac macl, er0
+ test_zero_clear
+ test_neg_set ; neg flag is set
+ test_ovf_clear
+ test_h_gr32 -4 er0 ; result is negative
+
+ stmac mach, er0
+ test_zero_clear
+ test_neg_set
+ test_ovf_clear
+ test_h_gr32 -1 er0 ; negative sign extend
+
+mac_array:
+ ;; Use same reg for src and dst, pointing to an array of shorts
+ set_grs_a5a5
+ mov #array, er1
+
+ set_ccr_zero
+ clrmac
+ mac @er1+, @er1+ ; same register for src and dst
+ mac @er1+, @er1+ ; repeat 8 times
+ mac @er1+, @er1+
+ mac @er1+, @er1+
+ mac @er1+, @er1+
+ mac @er1+, @er1+
+ mac @er1+, @er1+
+ mac @er1+, @er1+
+ test_cc_clear
+
+ test_h_gr32 0xa5a5a5a5 er0
+ test_h_gr32 array+32 er1
+ test_h_gr32 0xa5a5a5a5 er2
+ test_h_gr32 0xa5a5a5a5 er3
+ test_h_gr32 0xa5a5a5a5 er4
+ test_h_gr32 0xa5a5a5a5 er5
+ test_h_gr32 0xa5a5a5a5 er6
+ test_h_gr32 0xa5a5a5a5 er7
+
+ stmac macl, er0
+ test_zero_clear
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 0xfff80008 er0
+
+ stmac mach, er0
+ test_zero_clear
+ test_neg_clear
+ test_ovf_clear
+ test_h_gr32 1 er0 ; result is greater than 32 bits
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'mov.w'
+# mach(): h8300h h8300s h8sx
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+ .align 4
+byte_src:
+ .byte 0x77
+byte_dst:
+ .byte 0
+
+ .text
+
+ ;;
+ ;; Move byte from immediate source
+ ;;
+
+.if (sim_cpu == h8sx)
+mov_b_imm8_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, rd
+ mov.b #0x77:8, r0l ; Immediate 3-bit operand
+;;; .word 0xf877
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu == h8sx)
+mov_b_imm4_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:4, @aa:16
+ mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand
+;;; .word 0x6adf
+;;; .word @byte_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xf, @byte_dst
+ beq .Lnext21
+ fail
+.Lnext21:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm4_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:4, @aa:32
+ mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand
+;;; .word 0x6aff
+;;; .long @byte_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xf, @byte_dst
+ beq .Lnext22
+ fail
+.Lnext22:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @erd
+ mov.l #byte_dst, er1
+ mov.b #0xa5:8, @er1 ; Register indirect operand
+;;; .word 0x017d
+;;; .word 0x01a5
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext1
+ fail
+.Lnext1:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_postinc: ; post-increment from imm8 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @erd+
+ mov.l #byte_dst, er1
+ mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
+;;; .word 0x017d
+;;; .word 0x81a5
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst+1, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext2
+ fail
+.Lnext2:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @erd-
+ mov.l #byte_dst, er1
+ mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
+;;; .word 0x017d
+;;; .word 0xa1a5
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst-1, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext3
+ fail
+.Lnext3:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @+erd
+ mov.l #byte_dst-1, er1
+ mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
+;;; .word 0x017d
+;;; .word 0x91a5
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext4
+ fail
+.Lnext4:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @-erd
+ mov.l #byte_dst+1, er1
+ mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
+;;; .word 0x017d
+;;; .word 0xb1a5
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext5
+ fail
+.Lnext5:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @(dd:2, erd)
+ mov.l #byte_dst-3, er1
+ mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
+;;; .word 0x017d
+;;; .word 0x31a5
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext6
+ fail
+.Lnext6:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @(dd:16, erd)
+ mov.l #byte_dst-4, er1
+ mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x017d
+;;; .word 0x6f90
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext7
+ fail
+.Lnext7:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @(dd:32, erd)
+ mov.l #byte_dst-8, er1
+ mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x017d
+;;; .word 0xc9a5
+;;; .long 8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext8
+ fail
+.Lnext8:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @aa:16
+ mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand
+;;; .word 0x017d
+;;; .word 0x40a5
+;;; .word @byte_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext9
+ fail
+.Lnext9:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_imm8_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b #xx:8, @aa:32
+ mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand
+;;; .word 0x017d
+;;; .word 0x48a5
+;;; .long @byte_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b #0xa5, @byte_dst
+ beq .Lnext10
+ fail
+.Lnext10:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+.endif
+
+ ;;
+ ;; Move byte from register source
+ ;;
+
+mov_b_reg8_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, erd
+ mov.b #0x12, r1l
+ mov.b r1l, r0l ; Register 8-bit operand
+;;; .word 0x0c98
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+ test_h_gr16 0xa512 r0
+ test_h_gr16 0xa512 r1 ; mov src unchanged
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a512 er0
+ test_h_gr32 0xa5a5a512 er1 ; mov src unchanged
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+mov_b_reg8_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @erd
+ mov.l #byte_dst, er1
+ mov.b r0l, @er1 ; Register indirect operand
+;;; .word 0x6898
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.b @byte_dst, r0l
+ cmp.b r2l, r0l
+ beq .Lnext44
+ fail
+.Lnext44:
+ mov.b #0, r0l
+ mov.b r0l, @byte_dst ; zero it again for the next use.
+
+.if (sim_cpu == h8sx)
+mov_b_reg8_to_postinc: ; post-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @erd+
+ mov.l #byte_dst, er1
+ mov.b r0l, @er1+ ; Register post-incr operand
+;;; .word 0x0173
+;;; .word 0x6c98
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst+1, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b r2l, @byte_dst
+ beq .Lnext49
+ fail
+.Lnext49:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_reg8_to_postdec: ; post-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @erd-
+ mov.l #byte_dst, er1
+ mov.b r0l, @er1- ; Register post-decr operand
+;;; .word 0x0171
+;;; .word 0x6c98
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst-1, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b r2l, @byte_dst
+ beq .Lnext50
+ fail
+.Lnext50:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+
+mov_b_reg8_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @+erd
+ mov.l #byte_dst-1, er1
+ mov.b r0l, @+er1 ; Register pre-incr operand
+;;; .word 0x0172
+;;; .word 0x6c98
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b r2l, @byte_dst
+ beq .Lnext51
+ fail
+.Lnext51:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+.endif
+
+mov_b_reg8_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @-erd
+ mov.l #byte_dst+1, er1
+ mov.b r0l, @-er1 ; Register pre-decr operand
+;;; .word 0x6c98
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.b @byte_dst, r0l
+ cmp.b r2l, r0l
+ beq .Lnext48
+ fail
+.Lnext48:
+ mov.b #0, r0l
+ mov.b r0l, @byte_dst ; zero it again for the next use.
+
+.if (sim_cpu == h8sx)
+mov_b_reg8_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @(dd:2, erd)
+ mov.l #byte_dst-3, er1
+ mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand
+;;; .word 0x0173
+;;; .word 0x6898
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 byte_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b r2l, @byte_dst
+ beq .Lnext52
+ fail
+.Lnext52:
+ mov.b #0, @byte_dst ; zero it again for the next use.
+.endif
+
+mov_b_reg8_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @(dd:16, erd)
+ mov.l #byte_dst-4, er1
+ mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x6e98
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 byte_dst-4, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.b @byte_dst, r0l
+ cmp.b r2l, r0l
+ beq .Lnext45
+ fail
+.Lnext45:
+ mov.b #0, r0l
+ mov.b r0l, @byte_dst ; zero it again for the next use.
+
+mov_b_reg8_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @(dd:32, erd)
+ mov.l #byte_dst-8, er1
+ mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x7810
+;;; .word 0x6aa8
+;;; .long 8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 byte_dst-8, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.b @byte_dst, r0l
+ cmp.b r2l, r0l
+ beq .Lnext46
+ fail
+.Lnext46:
+ mov.b #0, r0l
+ mov.b r0l, @byte_dst ; zero it again for the next use.
+
+mov_b_reg8_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @aa:16
+ mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand
+;;; .word 0x6a88
+;;; .word @byte_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.b @byte_dst, r0l
+ cmp.b r0l, r1l
+ beq .Lnext41
+ fail
+.Lnext41:
+ mov.b #0, r0l
+ mov.b r0l, @byte_dst ; zero it again for the next use.
+
+mov_b_reg8_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b ers, @aa:32
+ mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand
+;;; .word 0x6aa8
+;;; .long @byte_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.b @byte_dst, r0l
+ cmp.b r0l, r1l
+ beq .Lnext42
+ fail
+.Lnext42:
+ mov.b #0, r0l
+ mov.b r0l, @byte_dst ; zero it again for the next use.
+
+ ;;
+ ;; Move byte to register destination.
+ ;;
+
+mov_b_indirect_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @ers, rd
+ mov.l #byte_src, er1
+ mov.b @er1, r0l ; Register indirect operand
+;;; .word 0x6818
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_h_gr32 byte_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_b_postinc_to_reg8: ; post-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @ers+, rd
+
+ mov.l #byte_src, er1
+ mov.b @er1+, r0l ; Register post-incr operand
+;;; .word 0x6c18
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_h_gr32 byte_src+1, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+mov_b_postdec_to_reg8: ; post-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @ers-, rd
+
+ mov.l #byte_src, er1
+ mov.b @er1-, r0l ; Register post-decr operand
+;;; .word 0x0172
+;;; .word 0x6c18
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_h_gr32 byte_src-1, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_b_preinc_to_reg8: ; pre-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @+ers, rd
+
+ mov.l #byte_src-1, er1
+ mov.b @+er1, r0l ; Register pre-incr operand
+;;; .word 0x0171
+;;; .word 0x6c18
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_h_gr32 byte_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_b_predec_to_reg8: ; pre-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @-ers, rd
+
+ mov.l #byte_src+1, er1
+ mov.b @-er1, r0l ; Register pre-decr operand
+;;; .word 0x0173
+;;; .word 0x6c18
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_h_gr32 byte_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+mov_b_disp2_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @(dd:2, ers), rd
+ mov.l #byte_src-1, er1
+ mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand
+;;; .word 0x0171
+;;; .word 0x6818
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 byte_src-1, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+mov_b_disp16_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @(dd:16, ers), rd
+ mov.l #byte_src+0x1234, er1
+ mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand
+;;; .word 0x6e18
+;;; .word -0x1234
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 byte_src+0x1234, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_b_disp32_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @(dd:32, ers), rd
+ mov.l #byte_src+65536, er1
+ mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand
+;;; .word 0x7810
+;;; .word 0x6a28
+;;; .long -65536
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 byte_src+65536, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_b_abs16_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @aa:16, rd
+ mov.b @byte_src:16, r0l ; 16-bit address-direct operand
+;;; .word 0x6a08
+;;; .word @byte_src
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_b_abs32_to_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @aa:32, rd
+ mov.b @byte_src:32, r0l ; 32-bit address-direct operand
+;;; .word 0x6a28
+;;; .long @byte_src
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a5a577 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+
+ ;;
+ ;; Move byte from memory to memory
+ ;;
+
+mov_b_indirect_to_indirect: ; reg indirect, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @ers, @erd
+
+ mov.l #byte_src, er1
+ mov.l #byte_dst, er0
+ mov.b @er1, @er0
+;;; .word 0x0178
+;;; .word 0x0100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst er0
+ test_h_gr32 byte_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext55
+ fail
+.Lnext55:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext56
+ fail
+.Lnext56: ; OK, pass on.
+
+mov_b_postinc_to_postinc: ; reg post-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @ers+, @erd+
+
+ mov.l #byte_src, er1
+ mov.l #byte_dst, er0
+ mov.b @er1+, @er0+
+;;; .word 0x0178
+;;; .word 0x8180
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst+1 er0
+ test_h_gr32 byte_src+1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext65
+ fail
+.Lnext65:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext66
+ fail
+.Lnext66: ; OK, pass on.
+
+mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @ers-, @erd-
+
+ mov.l #byte_src, er1
+ mov.l #byte_dst, er0
+ mov.b @er1-, @er0-
+;;; .word 0x0178
+;;; .word 0xa1a0
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst-1 er0
+ test_h_gr32 byte_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext75
+ fail
+.Lnext75:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext76
+ fail
+.Lnext76: ; OK, pass on.
+
+mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @+ers, @+erd
+
+ mov.l #byte_src-1, er1
+ mov.l #byte_dst-1, er0
+ mov.b @+er1, @+er0
+;;; .word 0x0178
+;;; .word 0x9190
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst er0
+ test_h_gr32 byte_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext85
+ fail
+.Lnext85:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext86
+ fail
+.Lnext86: ; OK, pass on.
+
+mov_b_predec_to_predec: ; reg pre-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @-ers, @-erd
+
+ mov.l #byte_src+1, er1
+ mov.l #byte_dst+1, er0
+ mov.b @-er1, @-er0
+;;; .word 0x0178
+;;; .word 0xb1b0
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst er0
+ test_h_gr32 byte_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext95
+ fail
+.Lnext95:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext96
+ fail
+.Lnext96: ; OK, pass on.
+
+mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @(dd:2, ers), @(dd:2, erd)
+
+ mov.l #byte_src-1, er1
+ mov.l #byte_dst-2, er0
+ mov.b @(1:2, er1), @(2:2, er0)
+;;; .word 0x0178
+;;; .word 0x1120
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst-2 er0
+ test_h_gr32 byte_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext105
+ fail
+.Lnext105:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext106
+ fail
+.Lnext106: ; OK, pass on.
+
+mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @(dd:16, ers), @(dd:16, erd)
+
+ mov.l #byte_src-1, er1
+ mov.l #byte_dst-2, er0
+ mov.b @(1:16, er1), @(2:16, er0)
+;;; .word 0x0178
+;;; .word 0xc1c0
+;;; .word 0x0001
+;;; .word 0x0002
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst-2 er0
+ test_h_gr32 byte_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext115
+ fail
+.Lnext115:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext116
+ fail
+.Lnext116: ; OK, pass on.
+
+mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @(dd:32, ers), @(dd:32, erd)
+
+ mov.l #byte_src-1, er1
+ mov.l #byte_dst-2, er0
+ mov.b @(1:32, er1), @(2:32, er0)
+;;; .word 0x0178
+;;; .word 0xc9c8
+;;; .long 1
+;;; .long 2
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 byte_dst-2 er0
+ test_h_gr32 byte_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext125
+ fail
+.Lnext125:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext126
+ fail
+.Lnext126: ; OK, pass on.
+
+mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @aa:16, @aa:16
+
+ mov.b @byte_src:16, @byte_dst:16
+;;; .word 0x0178
+;;; .word 0x4040
+;;; .word @byte_src
+;;; .word @byte_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext135
+ fail
+.Lnext135:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext136
+ fail
+.Lnext136: ; OK, pass on.
+
+mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.b @aa:32, @aa:32
+
+ mov.b @byte_src:32, @byte_dst:32
+;;; .word 0x0178
+;;; .word 0x4848
+;;; .long @byte_src
+;;; .long @byte_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.b @byte_src, @byte_dst
+ beq .Lnext145
+ fail
+.Lnext145:
+ ;; Now clear the destination location, and verify that.
+ mov.b #0, @byte_dst
+ cmp.b @byte_src, @byte_dst
+ bne .Lnext146
+ fail
+.Lnext146: ; OK, pass on.
+
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'mov.l'
+# mach(): h8300h h8300s h8sx
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+ .align 4
+long_src:
+ .long 0x77777777
+long_dst:
+ .long 0
+
+ .text
+
+ ;;
+ ;; Move long from immediate source
+ ;;
+
+.if (sim_cpu == h8sx)
+mov_l_imm3_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:3, erd
+ mov.l #0x3:3, er0 ; Immediate 3-bit operand
+;;; .word 0x0fb8
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x3 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_imm16_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, erd
+ mov.l #0x1234, er0 ; Immediate 16-bit operand
+;;; .word 0x7a08
+;;; .word 0x1234
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x1234 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+mov_l_imm32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, erd
+ mov.l #0x12345678, er0 ; Immediate 32-bit operand
+;;; .word 0x7a00
+;;; .long 0x12345678
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x12345678 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+mov_l_imm8_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @erd
+ mov.l #long_dst, er1
+ mov.l #0xa5:8, @er1 ; Register indirect operand
+;;; .word 0x010d
+;;; .word 0x01a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext1
+ fail
+.Lnext1:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_postinc: ; post-increment from imm8 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @erd+
+ mov.l #long_dst, er1
+ mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands.
+;;; .word 0x010d
+;;; .word 0x81a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst+4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext2
+ fail
+.Lnext2:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @erd-
+ mov.l #long_dst, er1
+ mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands.
+;;; .word 0x010d
+;;; .word 0xa1a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext3
+ fail
+.Lnext3:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @+erd
+ mov.l #long_dst-4, er1
+ mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands
+;;; .word 0x010d
+;;; .word 0x91a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext4
+ fail
+.Lnext4:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @-erd
+ mov.l #long_dst+4, er1
+ mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands
+;;; .word 0x010d
+;;; .word 0xb1a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext5
+ fail
+.Lnext5:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @(dd:2, erd)
+ mov.l #long_dst-3, er1
+ mov.l #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
+;;; .word 0x010d
+;;; .word 0x31a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext6
+ fail
+.Lnext6:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @(dd:16, erd)
+ mov.l #long_dst-4, er1
+ mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x010d
+;;; .word 0x6f90
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext7
+ fail
+.Lnext7:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @(dd:32, erd)
+ mov.l #long_dst-8, er1
+ mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x010d
+;;; .word 0xc9a5
+;;; .long 8
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext8
+ fail
+.Lnext8:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @aa:16
+ mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand
+;;; .word 0x010d
+;;; .word 0x40a5
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext9
+ fail
+.Lnext9:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm8_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:8, @aa:32
+ mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand
+;;; .word 0x010d
+;;; .word 0x48a5
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xa5, @long_dst
+ beq .Lnext10
+ fail
+.Lnext10:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @erd
+ mov.l #long_dst, er1
+ mov.l #0xdead:16, @er1 ; Register indirect operand
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0x0100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext11
+ fail
+.Lnext11:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_postinc: ; post-increment from imm16 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @erd+
+ mov.l #long_dst, er1
+ mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands.
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0x8100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst+4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext12
+ fail
+.Lnext12:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @erd-
+ mov.l #long_dst, er1
+ mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands.
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0xa100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext13
+ fail
+.Lnext13:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @+erd
+ mov.l #long_dst-4, er1
+ mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0x9100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext14
+ fail
+.Lnext14:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @-erd
+ mov.l #long_dst+4, er1
+ mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0xb100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext15
+ fail
+.Lnext15:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @(dd:2, erd)
+ mov.l #long_dst-3, er1
+ mov.l #0xdead:16, @(3:2, er1) ; Imm16, reg plus 2-bit disp. operand
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0x3100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext16
+ fail
+.Lnext16:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @(dd:16, erd)
+ mov.l #long_dst-4, er1
+ mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0xc100
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext17
+ fail
+.Lnext17:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @(dd:32, erd)
+ mov.l #long_dst-8, er1
+ mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0xc900
+;;; .long 8
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext18
+ fail
+.Lnext18:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @aa:16
+ mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0x4000
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext19
+ fail
+.Lnext19:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm16_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:16, @aa:32
+ mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand
+;;; .word 0x7a7c
+;;; .word 0xdead
+;;; .word 0x4800
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xdead, @long_dst
+ beq .Lnext20
+ fail
+.Lnext20:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @erd
+ mov.l #long_dst, er1
+ mov.l #0xcafedead:32, @er1 ; Register indirect operand
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0x0100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext21
+ fail
+.Lnext21:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_postinc: ; post-increment from imm32 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @erd+
+ mov.l #long_dst, er1
+ mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands.
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0x8100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst+4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext22
+ fail
+.Lnext22:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @erd-
+ mov.l #long_dst, er1
+ mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands.
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0xa100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext23
+ fail
+.Lnext23:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @+erd
+ mov.l #long_dst-4, er1
+ mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0x9100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext24
+ fail
+.Lnext24:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @-erd
+ mov.l #long_dst+4, er1
+ mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0xb100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext25
+ fail
+.Lnext25:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @(dd:2, erd)
+ mov.l #long_dst-3, er1
+ mov.l #0xcafedead:32, @(3:2, er1) ; Imm32, reg plus 2-bit disp. operand
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0x3100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext26
+ fail
+.Lnext26:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @(dd:16, erd)
+ mov.l #long_dst-4, er1
+ mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0xc100
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext27
+ fail
+.Lnext27:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @(dd:32, erd)
+ mov.l #long_dst-8, er1
+ mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0xc900
+;;; .long 8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext28
+ fail
+.Lnext28:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @aa:16
+ mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0x4000
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext29
+ fail
+.Lnext29:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_imm32_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l #xx:32, @aa:32
+ mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand
+;;; .word 0x7a74
+;;; .long 0xcafedead
+;;; .word 0x4800
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l #0xcafedead, @long_dst
+ beq .Lnext30
+ fail
+.Lnext30:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+.endif
+
+ ;;
+ ;; Move long from register source
+ ;;
+
+mov_l_reg32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, erd
+ mov.l #0x12345678, er1
+ mov.l er1, er0 ; Register 32-bit operand
+;;; .word 0x0f90
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+ test_h_gr32 0x12345678 er0
+ test_h_gr32 0x12345678 er1 ; mov src unchanged
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_reg32_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @erd
+ mov.l #long_dst, er1
+ mov.l er0, @er1 ; Register indirect operand
+;;; .word 0x0100
+;;; .word 0x6990
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.l #0, er0
+ mov.l @long_dst, er0
+ cmp.l er2, er0
+ beq .Lnext44
+ fail
+.Lnext44:
+ mov.l #0, er0
+ mov.l er0, @long_dst ; zero it again for the next use.
+
+.if (sim_cpu == h8sx)
+mov_l_reg32_to_postinc: ; post-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @erd+
+ mov.l #long_dst, er1
+ mov.l er0, @er1+ ; Register post-incr operand
+;;; .word 0x0103
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst+4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l er2, @long_dst
+ beq .Lnext49
+ fail
+.Lnext49:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_reg32_to_postdec: ; post-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @erd-
+ mov.l #long_dst, er1
+ mov.l er0, @er1- ; Register post-decr operand
+;;; .word 0x0101
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l er2, @long_dst
+ beq .Lnext50
+ fail
+.Lnext50:
+ mov.l #0, @long_dst ; zero it again for the next use.
+
+mov_l_reg32_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @+erd
+ mov.l #long_dst-4, er1
+ mov.l er0, @+er1 ; Register pre-incr operand
+;;; .word 0x0102
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l er2, @long_dst
+ beq .Lnext51
+ fail
+.Lnext51:
+ mov.l #0, @long_dst ; zero it again for the next use.
+.endif ; h8sx
+
+mov_l_reg32_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @-erd
+ mov.l #long_dst+4, er1
+ mov.l er0, @-er1 ; Register pre-decr operand
+;;; .word 0x0100
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.l #0, er0
+ mov.l @long_dst, er0
+ cmp.l er2, er0
+ beq .Lnext48
+ fail
+.Lnext48:
+ mov.l #0, er0
+ mov.l er0, @long_dst ; zero it again for the next use.
+
+.if (sim_cpu == h8sx)
+mov_l_reg32_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @(dd:2, erd)
+ mov.l #long_dst-3, er1
+ mov.l er0, @(3:2, er1) ; Register plus 2-bit disp. operand
+;;; .word 0x0103
+;;; .word 0x6990
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 long_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l er2, @long_dst
+ beq .Lnext52
+ fail
+.Lnext52:
+ mov.l #0, @long_dst ; zero it again for the next use.
+.endif ; h8sx
+
+mov_l_reg32_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @(dd:16, erd)
+ mov.l #long_dst-4, er1
+ mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x0100
+;;; .word 0x6f90
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 long_dst-4, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.l #0, er0
+ mov.l @long_dst, er0
+ cmp.l er2, er0
+ beq .Lnext45
+ fail
+.Lnext45:
+ mov.l #0, er0
+ mov.l er0, @long_dst ; zero it again for the next use.
+
+mov_l_reg32_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @(dd:32, erd)
+ mov.l #long_dst-8, er1
+ mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x7890
+;;; .word 0x6ba0
+;;; .long 8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 long_dst-8, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.l #0, er0
+ mov.l @long_dst, er0
+ cmp.l er2, er0
+ beq .Lnext46
+ fail
+.Lnext46:
+ mov.l #0, er0
+ mov.l er0, @long_dst ; zero it again for the next use.
+
+mov_l_reg32_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @aa:16
+ mov.l er0, @long_dst:16 ; 16-bit address-direct operand
+;;; .word 0x0100
+;;; .word 0x6b80
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.l #0, er0
+ mov.l @long_dst, er0
+ cmp.l er0, er1
+ beq .Lnext41
+ fail
+.Lnext41:
+ mov.l #0, er0
+ mov.l er0, @long_dst ; zero it again for the next use.
+
+mov_l_reg32_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l ers, @aa:32
+ mov.l er0, @long_dst:32 ; 32-bit address-direct operand
+;;; .word 0x0100
+;;; .word 0x6ba0
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.l #0, er0
+ mov.l @long_dst, er0
+ cmp.l er0, er1
+ beq .Lnext42
+ fail
+.Lnext42:
+ mov.l #0, er0
+ mov.l er0, @long_dst ; zero it again for the next use.
+
+ ;;
+ ;; Move long to register destination.
+ ;;
+
+mov_l_indirect_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @ers, erd
+ mov.l #long_src, er1
+ mov.l @er1, er0 ; Register indirect operand
+;;; .word 0x0100
+;;; .word 0x6910
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0
+
+ test_h_gr32 long_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_postinc_to_reg32: ; post-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @ers+, erd
+
+ mov.l #long_src, er1
+ mov.l @er1+, er0 ; Register post-incr operand
+;;; .word 0x0100
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0
+
+ test_h_gr32 long_src+4, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+mov_l_postdec_to_reg32: ; post-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @ers-, erd
+
+ mov.l #long_src, er1
+ mov.l @er1-, er0 ; Register post-decr operand
+;;; .word 0x0102
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0
+
+ test_h_gr32 long_src-4, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_preinc_to_reg32: ; pre-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @+ers, erd
+
+ mov.l #long_src-4, er1
+ mov.l @+er1, er0 ; Register pre-incr operand
+;;; .word 0x0101
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0
+
+ test_h_gr32 long_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_predec_to_reg32: ; pre-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @-ers, erd
+
+ mov.l #long_src+4, er1
+ mov.l @-er1, er0 ; Register pre-decr operand
+;;; .word 0x0103
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0
+
+ test_h_gr32 long_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+mov_l_disp2_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @(dd:2, ers), erd
+ mov.l #long_src-1, er1
+ mov.l @(1:2, er1), er0 ; Register plus 2-bit disp. operand
+;;; .word 0x0101
+;;; .word 0x6910
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 long_src-1, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif ; h8sx
+
+mov_l_disp16_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @(dd:16, ers), erd
+ mov.l #long_src+0x1234, er1
+ mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand
+;;; .word 0x0100
+;;; .word 0x6f10
+;;; .word -0x1234
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 long_src+0x1234, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_disp32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @(dd:32, ers), erd
+ mov.l #long_src+65536, er1
+ mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand
+;;; .word 0x7890
+;;; .word 0x6b20
+;;; .long -65536
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 long_src+65536, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_abs16_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @aa:16, erd
+ mov.l @long_src:16, er0 ; 16-bit address-direct operand
+;;; .word 0x0100
+;;; .word 0x6b00
+;;; .word @long_src
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_l_abs32_to_reg32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @aa:32, erd
+ mov.l @long_src:32, er0 ; 32-bit address-direct operand
+;;; .word 0x0100
+;;; .word 0x6b20
+;;; .long @long_src
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0x77777777 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+.if (sim_cpu == h8sx)
+
+ ;;
+ ;; Move long from memory to memory
+ ;;
+
+mov_l_indirect_to_indirect: ; reg indirect, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @ers, @erd
+
+ mov.l #long_src, er1
+ mov.l #long_dst, er0
+ mov.l @er1, @er0
+;;; .word 0x0108
+;;; .word 0x0100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst er0
+ test_h_gr32 long_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext55
+ fail
+.Lnext55:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext56
+ fail
+.Lnext56: ; OK, pass on.
+
+mov_l_postinc_to_postinc: ; reg post-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @ers+, @erd+
+
+ mov.l #long_src, er1
+ mov.l #long_dst, er0
+ mov.l @er1+, @er0+
+;;; .word 0x0108
+;;; .word 0x8180
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst+4 er0
+ test_h_gr32 long_src+4 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext65
+ fail
+.Lnext65:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext66
+ fail
+.Lnext66: ; OK, pass on.
+
+mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @ers-, @erd-
+
+ mov.l #long_src, er1
+ mov.l #long_dst, er0
+ mov.l @er1-, @er0-
+;;; .word 0x0108
+;;; .word 0xa1a0
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-4 er0
+ test_h_gr32 long_src-4 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext75
+ fail
+.Lnext75:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext76
+ fail
+.Lnext76: ; OK, pass on.
+
+mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @+ers, @+erd
+
+ mov.l #long_src-4, er1
+ mov.l #long_dst-4, er0
+ mov.l @+er1, @+er0
+;;; .word 0x0108
+;;; .word 0x9190
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst er0
+ test_h_gr32 long_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext85
+ fail
+.Lnext85:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext86
+ fail
+.Lnext86: ; OK, pass on.
+
+mov_l_predec_to_predec: ; reg pre-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @-ers, @-erd
+
+ mov.l #long_src+4, er1
+ mov.l #long_dst+4, er0
+ mov.l @-er1, @-er0
+;;; .word 0x0108
+;;; .word 0xb1b0
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst er0
+ test_h_gr32 long_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext95
+ fail
+.Lnext95:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext96
+ fail
+.Lnext96: ; OK, pass on.
+
+mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @(dd:2, ers), @(dd:2, erd)
+
+ mov.l #long_src-1, er1
+ mov.l #long_dst-2, er0
+ mov.l @(1:2, er1), @(2:2, er0)
+;;; .word 0x0108
+;;; .word 0x1120
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-2 er0
+ test_h_gr32 long_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext105
+ fail
+.Lnext105:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext106
+ fail
+.Lnext106: ; OK, pass on.
+
+mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @(dd:16, ers), @(dd:16, erd)
+
+ mov.l #long_src-1, er1
+ mov.l #long_dst-2, er0
+ mov.l @(1:16, er1), @(2:16, er0)
+;;; .word 0x0108
+;;; .word 0xc1c0
+;;; .word 0x0001
+;;; .word 0x0002
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-2 er0
+ test_h_gr32 long_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext115
+ fail
+.Lnext115:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext116
+ fail
+.Lnext116: ; OK, pass on.
+
+mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @(dd:32, ers), @(dd:32, erd)
+
+ mov.l #long_src-1, er1
+ mov.l #long_dst-2, er0
+ mov.l @(1:32, er1), @(2:32, er0)
+;;; .word 0x0108
+;;; .word 0xc9c8
+;;; .long 1
+;;; .long 2
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 long_dst-2 er0
+ test_h_gr32 long_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext125
+ fail
+.Lnext125:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext126
+ fail
+.Lnext126: ; OK, pass on.
+
+mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @aa:16, @aa:16
+
+ mov.l @long_src:16, @long_dst:16
+;;; .word 0x0108
+;;; .word 0x4040
+;;; .word @long_src
+;;; .word @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext135
+ fail
+.Lnext135:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext136
+ fail
+.Lnext136: ; OK, pass on.
+
+mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.l @aa:32, @aa:32
+
+ mov.l @long_src:32, @long_dst:32
+;;; .word 0x0108
+;;; .word 0x4848
+;;; .long @long_src
+;;; .long @long_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.l @long_src, @long_dst
+ beq .Lnext145
+ fail
+.Lnext145:
+ ;; Now clear the destination location, and verify that.
+ mov.l #0, @long_dst
+ cmp.l @long_src, @long_dst
+ bne .Lnext146
+ fail
+.Lnext146: ; OK, pass on.
+
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'mov.w'
+# mach(): h8300h h8300s h8sx
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+ .align 2
+word_src:
+ .word 0x7777
+word_dst:
+ .word 0
+
+ .text
+
+ ;;
+ ;; Move word from immediate source
+ ;;
+
+.if (sim_cpu == h8sx)
+mov_w_imm3_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:3, rd
+ mov.w #0x3:3, r0 ; Immediate 3-bit operand
+;;; .word 0x0f30
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a50003 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+mov_w_imm16_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, rd
+ mov.w #0x1234, r0 ; Immediate 16-bit operand
+;;; .word 0x7900
+;;; .word 0x1234
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a51234 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+mov_w_imm4_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:4, @aa:16
+ mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct
+;;; .word 0x6bdf
+;;; .word @word_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xf, @word_dst
+ beq .Lnext21
+ fail
+.Lnext21:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm4_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:4, @aa:32
+ mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct
+;;; .word 0x6bff
+;;; .long @word_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xf, @word_dst
+ beq .Lnext22
+ fail
+.Lnext22:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @erd
+ mov.l #word_dst, er1
+ mov.w #0xa5:8, @er1 ; Register indirect operand
+;;; .word 0x015d
+;;; .word 0x01a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext1
+ fail
+.Lnext1:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_postinc: ; post-increment from imm8 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @erd+
+ mov.l #word_dst, er1
+ mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
+;;; .word 0x015d
+;;; .word 0x81a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst+2, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext2
+ fail
+.Lnext2:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @erd-
+ mov.l #word_dst, er1
+ mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
+;;; .word 0x015d
+;;; .word 0xa1a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-2, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext3
+ fail
+.Lnext3:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @+erd
+ mov.l #word_dst-2, er1
+ mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
+;;; .word 0x015d
+;;; .word 0x91a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext4
+ fail
+.Lnext4:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @-erd
+ mov.l #word_dst+2, er1
+ mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
+;;; .word 0x015d
+;;; .word 0xb1a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext5
+ fail
+.Lnext5:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @(dd:2, erd)
+ mov.l #word_dst-3, er1
+ mov.w #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
+;;; .word 0x015d
+;;; .word 0x31a5
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext6
+ fail
+.Lnext6:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @(dd:16, erd)
+ mov.l #word_dst-4, er1
+ mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x015d
+;;; .word 0x6f90
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext7
+ fail
+.Lnext7:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @(dd:32, erd)
+ mov.l #word_dst-8, er1
+ mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x015d
+;;; .word 0xc9a5
+;;; .long 8
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext8
+ fail
+.Lnext8:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @aa:16
+ mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand
+;;; .word 0x015d
+;;; .word 0x40a5
+;;; .word @word_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext9
+ fail
+.Lnext9:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm8_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:8, @aa:32
+ mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand
+;;; .word 0x015d
+;;; .word 0x48a5
+;;; .long @word_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xa5, @word_dst
+ beq .Lnext10
+ fail
+.Lnext10:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @erd
+ mov.l #word_dst, er1
+ mov.w #0xdead:16, @er1 ; Register indirect operand
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0x0100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext11
+ fail
+.Lnext11:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_postinc: ; post-increment from imm16 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @erd+
+ mov.l #word_dst, er1
+ mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands.
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0x8100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst+2, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext12
+ fail
+.Lnext12:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @erd-
+ mov.l #word_dst, er1
+ mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands.
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0xa100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-2, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext13
+ fail
+.Lnext13:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @+erd
+ mov.l #word_dst-2, er1
+ mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0x9100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext14
+ fail
+.Lnext14:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @-erd
+ mov.l #word_dst+2, er1
+ mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0xb100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext15
+ fail
+.Lnext15:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @(dd:2, erd)
+ mov.l #word_dst-3, er1
+ mov.w #0xdead:16, @(3:2, er1) ; Imm16, reg plus 2-bit disp. operand
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0x3100
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext16
+ fail
+.Lnext16:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @(dd:16, erd)
+ mov.l #word_dst-4, er1
+ mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0xc100
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-4, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext17
+ fail
+.Lnext17:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @(dd:32, erd)
+ mov.l #word_dst-8, er1
+ mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0xc900
+;;; .long 8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-8, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext18
+ fail
+.Lnext18:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @aa:16
+ mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0x4000
+;;; .word @word_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext19
+ fail
+.Lnext19:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_imm16_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w #xx:16, @aa:32
+ mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand
+;;; .word 0x7974
+;;; .word 0xdead
+;;; .word 0x4800
+;;; .long @word_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w #0xdead, @word_dst
+ beq .Lnext20
+ fail
+.Lnext20:
+ mov.w #0, @word_dst ; zero it again for the next use.
+.endif
+
+ ;;
+ ;; Move word from register source
+ ;;
+
+mov_w_reg16_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, erd
+ mov.w #0x1234, r1
+ mov.w r1, r0 ; Register 16-bit operand
+;;; .word 0x0d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+ test_h_gr16 0x1234 r0
+ test_h_gr16 0x1234 r1 ; mov src unchanged
+.if (sim_cpu)
+ test_h_gr32 0xa5a51234 er0
+ test_h_gr32 0xa5a51234 er1 ; mov src unchanged
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+mov_w_reg16_to_indirect:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @erd
+ mov.l #word_dst, er1
+ mov.w r0, @er1 ; Register indirect operand
+;;; .word 0x6990
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.w #0, r0
+ mov.w @word_dst, r0
+ cmp.w r2, r0
+ beq .Lnext44
+ fail
+.Lnext44:
+ mov.w #0, r0
+ mov.w r0, @word_dst ; zero it again for the next use.
+
+.if (sim_cpu == h8sx)
+mov_w_reg16_to_postinc: ; post-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @erd+
+ mov.l #word_dst, er1
+ mov.w r0, @er1+ ; Register post-incr operand
+;;; .word 0x0153
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst+2, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w r2, @word_dst
+ beq .Lnext49
+ fail
+.Lnext49:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_reg16_to_postdec: ; post-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @erd-
+ mov.l #word_dst, er1
+ mov.w r0, @er1- ; Register post-decr operand
+;;; .word 0x0151
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-2, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w r2, @word_dst
+ beq .Lnext50
+ fail
+.Lnext50:
+ mov.w #0, @word_dst ; zero it again for the next use.
+
+mov_w_reg16_to_preinc: ; pre-increment from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @+erd
+ mov.l #word_dst-2, er1
+ mov.w r0, @+er1 ; Register pre-incr operand
+;;; .word 0x0152
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w r2, @word_dst
+ beq .Lnext51
+ fail
+.Lnext51:
+ mov.w #0, @word_dst ; zero it again for the next use.
+.endif
+
+mov_w_reg16_to_predec: ; pre-decrement from register to mem
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @-erd
+ mov.l #word_dst+2, er1
+ mov.w r0, @-er1 ; Register pre-decr operand
+;;; .word 0x6d90
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.w #0, r0
+ mov.w @word_dst, r0
+ cmp.w r2, r0
+ beq .Lnext48
+ fail
+.Lnext48:
+ mov.w #0, r0
+ mov.w r0, @word_dst ; zero it again for the next use.
+
+.if (sim_cpu == h8sx)
+mov_w_reg16_to_disp2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @(dd:2, erd)
+ mov.l #word_dst-3, er1
+ mov.w r0, @(3:2, er1) ; Register plus 2-bit disp. operand
+;;; .word 0x0153
+;;; .word 0x6990
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_h_gr32 word_dst-3, er1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w r2, @word_dst
+ beq .Lnext52
+ fail
+.Lnext52:
+ mov.w #0, @word_dst ; zero it again for the next use.
+.endif
+
+mov_w_reg16_to_disp16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @(dd:16, erd)
+ mov.l #word_dst-4, er1
+ mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand
+;;; .word 0x6f90
+;;; .word 0x0004
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 word_dst-4, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.w #0, r0
+ mov.w @word_dst, r0
+ cmp.w r2, r0
+ beq .Lnext45
+ fail
+.Lnext45:
+ mov.w #0, r0
+ mov.w r0, @word_dst ; zero it again for the next use.
+
+mov_w_reg16_to_disp32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @(dd:32, erd)
+ mov.l #word_dst-8, er1
+ mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand
+;;; .word 0x7810
+;;; .word 0x6ba0
+;;; .long 8
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 word_dst-8, er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.w #0, r0
+ mov.w @word_dst, r0
+ cmp.w r2, r0
+ beq .Lnext46
+ fail
+.Lnext46:
+ mov.w #0, r0
+ mov.w r0, @word_dst ; zero it again for the next use.
+
+mov_w_reg16_to_abs16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @aa:16
+ mov.w r0, @word_dst:16 ; 16-bit address-direct operand
+;;; .word 0x6b80
+;;; .word @word_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.w #0, r0
+ mov.w @word_dst, r0
+ cmp.w r0, r1
+ beq .Lnext41
+ fail
+.Lnext41:
+ mov.w #0, r0
+ mov.w r0, @word_dst ; zero it again for the next use.
+
+mov_w_reg16_to_abs32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w ers, @aa:32
+ mov.w r0, @word_dst:32 ; 32-bit address-direct operand
+;;; .word 0x6ba0
+;;; .long @word_dst
+
+ ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_neg_set
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
+ test_gr_a5a5 1 ; (first, because on h8/300 we must use one
+ test_gr_a5a5 2 ; to examine the destination memory).
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ mov.w #0, r0
+ mov.w @word_dst, r0
+ cmp.w r0, r1
+ beq .Lnext42
+ fail
+.Lnext42:
+ mov.w #0, r0
+ mov.w r0, @word_dst ; zero it again for the next use.
+
+ ;;
+ ;; Move word to register destination.
+ ;;
+
+mov_w_indirect_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @ers, rd
+ mov.l #word_src, er1
+ mov.w @er1, r0 ; Register indirect operand
+;;; .word 0x6910
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0
+
+ test_h_gr32 word_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_w_postinc_to_reg16: ; post-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @ers+, rd
+
+ mov.l #word_src, er1
+ mov.w @er1+, r0 ; Register post-incr operand
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0
+
+ test_h_gr32 word_src+2, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+mov_w_postdec_to_reg16: ; post-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @ers-, rd
+
+ mov.l #word_src, er1
+ mov.w @er1-, r0 ; Register post-decr operand
+;;; .word 0x0152
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0
+
+ test_h_gr32 word_src-2, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_w_preinc_to_reg16: ; pre-increment from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @+ers, rd
+
+ mov.l #word_src-2, er1
+ mov.w @+er1, r0 ; Register pre-incr operand
+;;; .word 0x0151
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0
+
+ test_h_gr32 word_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_w_predec_to_reg16: ; pre-decrement from mem to register
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @-ers, rd
+
+ mov.l #word_src+2, er1
+ mov.w @-er1, r0 ; Register pre-decr operand
+;;; .word 0x0153
+;;; .word 0x6d10
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0
+
+ test_h_gr32 word_src, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+
+mov_w_disp2_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @(dd:2, ers), rd
+ mov.l #word_src-1, er1
+ mov.w @(1:2, er1), r0 ; Register plus 2-bit disp. operand
+;;; .word 0x0151
+;;; .word 0x6910
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 word_src-1, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+mov_w_disp16_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @(dd:16, ers), rd
+ mov.l #word_src+0x1234, er1
+ mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand
+;;; .word 0x6f10
+;;; .word -0x1234
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 word_src+0x1234, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_w_disp32_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @(dd:32, ers), rd
+ mov.l #word_src+65536, er1
+ mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand
+;;; .word 0x7810
+;;; .word 0x6b20
+;;; .long -65536
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
+
+ test_h_gr32 word_src+65536, er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_w_abs16_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @aa:16, rd
+ mov.w @word_src:16, r0 ; 16-bit address-direct operand
+;;; .word 0x6b00
+;;; .word @word_src
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+mov_w_abs32_to_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @aa:32, rd
+ mov.w @word_src:32, r0 ; 32-bit address-direct operand
+;;; .word 0x6b20
+;;; .long @word_src
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_h_gr32 0xa5a57777 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+
+ ;;
+ ;; Move word from memory to memory
+ ;;
+
+mov_w_indirect_to_indirect: ; reg indirect, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @ers, @erd
+
+ mov.l #word_src, er1
+ mov.l #word_dst, er0
+ mov.w @er1, @er0
+;;; .word 0x0158
+;;; .word 0x0100
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst er0
+ test_h_gr32 word_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext55
+ fail
+.Lnext55:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext56
+ fail
+.Lnext56: ; OK, pass on.
+
+mov_w_postinc_to_postinc: ; reg post-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @ers+, @erd+
+
+ mov.l #word_src, er1
+ mov.l #word_dst, er0
+ mov.w @er1+, @er0+
+;;; .word 0x0158
+;;; .word 0x8180
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst+2 er0
+ test_h_gr32 word_src+2 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext65
+ fail
+.Lnext65:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext66
+ fail
+.Lnext66: ; OK, pass on.
+
+mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @ers-, @erd-
+
+ mov.l #word_src, er1
+ mov.l #word_dst, er0
+ mov.w @er1-, @er0-
+;;; .word 0x0158
+;;; .word 0xa1a0
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst-2 er0
+ test_h_gr32 word_src-2 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext75
+ fail
+.Lnext75:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext76
+ fail
+.Lnext76: ; OK, pass on.
+
+mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @+ers, @+erd
+
+ mov.l #word_src-2, er1
+ mov.l #word_dst-2, er0
+ mov.w @+er1, @+er0
+;;; .word 0x0158
+;;; .word 0x9190
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst er0
+ test_h_gr32 word_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext85
+ fail
+.Lnext85:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext86
+ fail
+.Lnext86: ; OK, pass on.
+
+mov_w_predec_to_predec: ; reg pre-decrement, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @-ers, @-erd
+
+ mov.l #word_src+2, er1
+ mov.l #word_dst+2, er0
+ mov.w @-er1, @-er0
+;;; .word 0x0158
+;;; .word 0xb1b0
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst er0
+ test_h_gr32 word_src er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext95
+ fail
+.Lnext95:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext96
+ fail
+.Lnext96: ; OK, pass on.
+
+mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @(dd:2, ers), @(dd:2, erd)
+
+ mov.l #word_src-1, er1
+ mov.l #word_dst-2, er0
+ mov.w @(1:2, er1), @(2:2, er0)
+;;; .word 0x0158
+;;; .word 0x1120
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst-2 er0
+ test_h_gr32 word_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext105
+ fail
+.Lnext105:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext106
+ fail
+.Lnext106: ; OK, pass on.
+
+mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @(dd:16, ers), @(dd:16, erd)
+
+ mov.l #word_src-1, er1
+ mov.l #word_dst-2, er0
+ mov.w @(1:16, er1), @(2:16, er0)
+;;; .word 0x0158
+;;; .word 0xc1c0
+;;; .word 0x0001
+;;; .word 0x0002
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst-2 er0
+ test_h_gr32 word_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext115
+ fail
+.Lnext115:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext116
+ fail
+.Lnext116: ; OK, pass on.
+
+mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @(dd:32, ers), @(dd:32, erd)
+
+ mov.l #word_src-1, er1
+ mov.l #word_dst-2, er0
+ mov.w @(1:32, er1), @(2:32, er0)
+;;; .word 0x0158
+;;; .word 0xc9c8
+;;; .long 1
+;;; .long 2
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ ;; Verify the affected registers.
+
+ test_h_gr32 word_dst-2 er0
+ test_h_gr32 word_src-1 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext125
+ fail
+.Lnext125:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext126
+ fail
+.Lnext126: ; OK, pass on.
+
+mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @aa:16, @aa:16
+
+ mov.w @word_src:16, @word_dst:16
+;;; .word 0x0158
+;;; .word 0x4040
+;;; .word @word_src
+;;; .word @word_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext135
+ fail
+.Lnext135:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext136
+ fail
+.Lnext136: ; OK, pass on.
+
+mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; mov.w @aa:32, @aa:32
+
+ mov.w @word_src:32, @word_dst:32
+;;; .word 0x0158
+;;; .word 0x4848
+;;; .long @word_src
+;;; .long @word_dst
+
+ ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
+ test_neg_clear
+ test_zero_clear
+ test_ovf_clear
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure *NO* general registers are changed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the move to memory.
+ cmp.w @word_src, @word_dst
+ beq .Lnext145
+ fail
+.Lnext145:
+ ;; Now clear the destination location, and verify that.
+ mov.w #0, @word_dst
+ cmp.w @word_src, @word_dst
+ bne .Lnext146
+ fail
+.Lnext146: ; OK, pass on.
+
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'movmd'
+# mach(): h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ .data
+byte_src:
+ .byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+byte_dst:
+ .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+ .align 2
+word_src:
+ .word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+word_dst:
+ .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+ .align 4
+long_src:
+ .long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+long_dst:
+ .long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+ start
+.if (sim_cpu == h8sx)
+movmd_b:#
+ # Byte block transfer
+ #
+ set_grs_a5a5
+
+ mov #byte_src, er5
+ mov #byte_dst, er6
+ mov #10, r4
+ set_ccr_zero
+ ;; movmd.b
+ movmd.b
+;;; .word 0x7b94
+
+ test_cc_clear
+ test_gr_a5a5 0
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_h_gr32 0xa5a50000 er4
+ test_h_gr32 byte_src+10 er5
+ test_h_gr32 byte_dst+10 er6
+ test_gr_a5a5 7
+
+ #
+ # Now make sure exactly 10 bytes were transferred.
+ memcmp byte_src byte_dst 10
+ cmp.b #0, @byte_dst+10
+ beq .L0
+ fail
+.L0:
+
+movmd_w:#
+ # Word block transfer
+ #
+ set_grs_a5a5
+
+ mov #word_src, er5
+ mov #word_dst, er6
+ mov #10, r4
+ set_ccr_zero
+ ;; movmd.w
+ movmd.w
+;;; .word 0x7ba4
+
+ test_cc_clear
+ test_gr_a5a5 0
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_h_gr32 0xa5a50000 er4
+ test_h_gr32 word_src+20 er5
+ test_h_gr32 word_dst+20 er6
+ test_gr_a5a5 7
+
+ #
+ # Now make sure exactly 20 bytes were transferred.
+ memcmp word_src word_dst 20
+ cmp.w #0, @word_dst+20
+ beq .L1
+ fail
+.L1:
+
+movmd_l:#
+ # Long block transfer
+ #
+ set_grs_a5a5
+
+ mov #long_src, er5
+ mov #long_dst, er6
+ mov #10, r4
+ set_ccr_zero
+ ;; movmd.b
+ movmd.l
+;;; .word 0x7bb4
+
+ test_cc_clear
+ test_gr_a5a5 0
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_h_gr32 0xa5a50000 er4
+ test_h_gr32 long_src+40 er5
+ test_h_gr32 long_dst+40 er6
+ test_gr_a5a5 7
+
+ #
+ # Now make sure exactly 40 bytes were transferred.
+ memcmp long_src long_dst 40
+ cmp.l #0, @long_dst+40
+ beq .L2
+ fail
+.L2:
+
+.endif
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'movsd'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ .data
+src: .byte 'h', 'e', 'l', 'l', 'o', 0
+dst1: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+dst2: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+ start
+.if (sim_cpu == h8sx)
+movsd_n:#
+ # In this test, the transfer will stop after n bytes.
+ #
+ set_grs_a5a5
+
+ mov #src, er5
+ mov #dst1, er6
+ mov #4, r4
+ set_ccr_zero
+ ;; movsd.b disp:16
+ movsd.b fail1:16
+;;; .word 0x7b84
+;;; .word 0x02
+
+ bra pass1
+fail1: fail
+pass1: test_cc_clear
+ test_gr_a5a5 0
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_h_gr32 0xa5a50000 er4
+ test_h_gr32 src+4 er5
+ test_h_gr32 dst1+4 er6
+ test_gr_a5a5 7
+
+ #
+ # Now make sure exactly 4 bytes were transferred.
+ cmp.b @src, @dst1
+ bne fail1:16
+ cmp.b @src+1, @dst1+1
+ bne fail1:16
+ cmp.b @src+2, @dst1+2
+ bne fail1:16
+ cmp.b @src+3, @dst1+3
+ bne fail1:16
+ cmp.b @src+4, @dst1+4
+ beq fail1:16
+
+movsd_s:#
+ # In this test, the entire null-terminated string is transferred.
+ #
+ set_grs_a5a5
+
+ mov #src, er5
+ mov #dst2, er6
+ mov #8, r4
+ set_ccr_zero
+ ;; movsd.b disp:16
+ movsd.b pass2:16
+;;; .word 0x7b84
+;;; .word 0x10
+
+fail2: fail
+pass2: test_cc_clear
+ test_gr_a5a5 0
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_h_gr32 0xa5a50002 er4
+ test_h_gr32 src+6 er5
+ test_h_gr32 dst2+6 er6
+ test_gr_a5a5 7
+ #
+ # Now make sure 5 bytes were transferred, and the 6th is zero.
+ cmp.b @src, @dst2
+ bne fail2:16
+ cmp.b @src+1, @dst2+1
+ bne fail2:16
+ cmp.b @src+2, @dst2+2
+ bne fail2:16
+ cmp.b @src+3, @dst2+3
+ bne fail2:16
+ cmp.b @src+4, @dst2+4
+ bne fail2:16
+ cmp.b #0, @dst2+5
+ bne fail2:16
+.endif
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'neg.b, neg.w, neg.l'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # neg.b rd ; 1 7 8 rd
+ # neg.b @erd ; 7 d rd ???? 1 7 8 ignore
+ # neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore
+ # neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore
+ # neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore
+ # neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore
+ # neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore
+ # neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore
+ # neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore
+ # neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore
+ # neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore
+ # word operations
+ # long operations
+ #
+ # Coming soon:
+ # neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore
+ #
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+ start
+
+ #
+ # Note: apparently carry is set for neg of anything except zero.
+ #
+
+ #
+ # 8-bit byte operations
+ #
+
+neg_b_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b Rd
+ neg r0l ; 8-bit register
+;;; .word 0x1788
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.b #0x5b, r0l ; result of "neg 0xa5"
+ beq .Lbrd
+ fail
+.Lbrd:
+ test_h_gr16 0xa55b r0 ; r0 changed by 'neg'
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg'
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+neg_b_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @eRd
+ mov #byte_dest, er0
+ neg.b @er0 ; register indirect operand
+;;; .word 0x7d00
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ cmp.b #0x5b, @er0 ; memory contents changed
+ beq .Lbind
+ fail
+.Lbind:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @eRd+
+ mov #byte_dest, er0 ; register post-increment operand
+ neg.b @er0+
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one
+ cmp.b #0xa5, @-er0
+ beq .Lbpostinc
+ fail
+.Lbpostinc:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @eRd-
+ mov #byte_dest, er0 ; register post-decrement operand
+ neg.b @er0-
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
+ cmp.b #0x5b, @+er0
+ beq .Lbpostdec
+ fail
+.Lbpostdec:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @+eRd
+ mov #byte_dest-1, er0
+ neg.b @+er0 ; reg pre-increment operand
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5, @er0
+ beq .Lbpreinc
+ fail
+.Lbpreinc:
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @-eRd
+ mov #byte_dest+1, er0
+ neg.b @-er0 ; reg pre-decr operand
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.b #0x5b, @er0
+ beq .Lbpredec
+ fail
+.Lbpredec:
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_disp2dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @(dd:2, erd)
+ mov #byte_dest-1, er0
+ neg.b @(1:2, er0) ; reg plus 2-bit displacement
+;;; .word 0x0175
+;;; .word 0x6808
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5, @+er0
+ beq .Lbdisp2
+ fail
+.Lbdisp2:
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_disp16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @(dd:16, erd)
+ mov #byte_dest+100, er0
+ neg.b @(-100:16, er0) ; reg plus 16-bit displacement
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word -100
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.b #0x5b, @byte_dest
+ beq .Lbdisp16
+ fail
+.Lbdisp16:
+ test_h_gr32 byte_dest+100 er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_disp32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @(dd:32, erd)
+ mov #byte_dest-0xfffff, er0
+ neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement
+;;; .word 0x7804
+;;; .word 0x6a28
+;;; .long 0xfffff
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5, @byte_dest
+ beq .Lbdisp32
+ fail
+.Lbdisp32:
+ test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_abs16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @aa:16
+ neg.b @byte_dest:16 ; 16-bit absolute address
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.b #0x5b, @byte_dest
+ beq .Lbabs16
+ fail
+.Lbabs16:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_b_abs32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.b @aa:32
+ neg.b @byte_dest:32 ; 32-bit absolute address
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x1780
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5, @byte_dest
+ beq .Lbabs32
+ fail
+.Lbabs32:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+ #
+ # 16-bit word operations
+ #
+
+.if (sim_cpu) ; any except plain-vanilla h8/300
+neg_w_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w Rd
+ neg r1 ; 16-bit register operand
+;;; .word 0x1791
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5"
+ beq .Lwrd
+ fail
+.Lwrd:
+ test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg'
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+neg_w_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @eRd
+ mov #word_dest, er1
+ neg.w @er1 ; register indirect operand
+;;; .word 0x0154
+;;; .word 0x6d18
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5b, @word_dest ; memory contents changed
+ beq .Lwind
+ fail
+.Lwind:
+ test_h_gr32 word_dest er1 ; er1 still contains address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @eRd+
+ mov #word_dest, er1 ; register post-increment operand
+ neg.w @er1+
+;;; .word 0x0154
+;;; .word 0x6d18
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwpostinc
+ fail
+.Lwpostinc:
+ test_h_gr32 word_dest+2 er1 ; er1 contains address plus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @eRd-
+ mov #word_dest, er1
+ neg.w @er1-
+;;; .word 0x0156
+;;; .word 0x6d18
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5b, @word_dest
+ beq .Lwpostdec
+ fail
+.Lwpostdec:
+ test_h_gr32 word_dest-2 er1 ; er1 contains address minus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @+eRd
+ mov #word_dest-2, er1
+ neg.w @+er1 ; reg pre-increment operand
+;;; .word 0x0155
+;;; .word 0x6d18
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwpreinc
+ fail
+.Lwpreinc:
+ test_h_gr32 word_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @-eRd
+ mov #word_dest+2, er1
+ neg.w @-er1 ; reg pre-decr operand
+;;; .word 0x0157
+;;; .word 0x6d18
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5b, @word_dest
+ beq .Lwpredec
+ fail
+.Lwpredec:
+ test_h_gr32 word_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_disp2dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @(dd:2, erd)
+ mov #word_dest-1, er1
+ neg.w @(1:2, er1) ; reg plus 2-bit displacement
+;;; .word 0x0155
+;;; .word 0x6918
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwdisp2
+ fail
+.Lwdisp2:
+ test_h_gr32 word_dest-1 er1 ; er1 contains address minus one
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_disp16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @(dd:16, erd)
+ mov #word_dest+100, er1
+ neg.w @(-100:16, er1) ; reg plus 16-bit displacement
+;;; .word 0x0154
+;;; .word 0x6f18
+;;; .word -100
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5b, @word_dest
+ beq .Lwdisp16
+ fail
+.Lwdisp16:
+ test_h_gr32 word_dest+100 er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_disp32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @(dd:32, erd)
+ mov #word_dest-0xfffff, er1
+ neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement
+;;; .word 0x7814
+;;; .word 0x6b28
+;;; .long 0xfffff
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwdisp32
+ fail
+.Lwdisp32:
+ test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_abs16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @aa:16
+ neg.w @word_dest:16 ; 16-bit absolute address
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5b, @word_dest
+ beq .Lwabs16
+ fail
+.Lwabs16:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_w_abs32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.w @aa:32
+ neg.w @word_dest:32 ; 32-bit absolute address
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1790
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwabs32
+ fail
+.Lwabs32:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif ; h8sx
+.endif ; h8/300
+
+ #
+ # 32-bit word operations
+ #
+
+.if (sim_cpu) ; any except plain-vanilla h8/300
+neg_l_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l eRd
+ neg er1 ; 32-bit register operand
+;;; .word 0x17b1
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5"
+ beq .Llrd
+ fail
+.Llrd:
+ test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg'
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+neg_l_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @eRd
+ mov #long_dest, er1
+ neg.l @er1 ; register indirect operand
+;;; .word 0x0104
+;;; .word 0x6d18
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed
+ beq .Llind
+ fail
+.Llind:
+ test_h_gr32 long_dest er1 ; er1 still contains address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @eRd+
+ mov #long_dest, er1 ; register post-increment operand
+ neg.l @er1+
+;;; .word 0x0104
+;;; .word 0x6d18
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Llpostinc
+ fail
+.Llpostinc:
+ test_h_gr32 long_dest+4 er1 ; er1 contains address plus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @eRd-
+ mov #long_dest, er1
+ neg.l @er1-
+;;; .word 0x0106
+;;; .word 0x6d18
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5b, @long_dest
+ beq .Llpostdec
+ fail
+.Llpostdec:
+ test_h_gr32 long_dest-4 er1 ; er1 contains address minus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @+eRd
+ mov #long_dest-4, er1
+ neg.l @+er1 ; reg pre-increment operand
+;;; .word 0x0105
+;;; .word 0x6d18
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Llpreinc
+ fail
+.Llpreinc:
+ test_h_gr32 long_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @-eRd
+ mov #long_dest+4, er1
+ neg.l @-er1 ; reg pre-decr operand
+;;; .word 0x0107
+;;; .word 0x6d18
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5b, @long_dest
+ beq .Llpredec
+ fail
+.Llpredec:
+ test_h_gr32 long_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_disp2dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @(dd:2, erd)
+ mov #long_dest-1, er1
+ neg.l @(1:2, er1) ; reg plus 2-bit displacement
+;;; .word 0x0105
+;;; .word 0x6918
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Lldisp2
+ fail
+.Lldisp2:
+ test_h_gr32 long_dest-1 er1 ; er1 contains address minus one
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_disp16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @(dd:16, erd)
+ mov #long_dest+100, er1
+ neg.l @(-100:16, er1) ; reg plus 16-bit displacement
+;;; .word 0x0104
+;;; .word 0x6f18
+;;; .word -100
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5b, @long_dest
+ beq .Lldisp16
+ fail
+.Lldisp16:
+ test_h_gr32 long_dest+100 er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_disp32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @(dd:32, erd)
+ mov #long_dest-0xfffff, er1
+ neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement
+;;; .word 0x7894
+;;; .word 0x6b28
+;;; .long 0xfffff
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Lldisp32
+ fail
+.Lldisp32:
+ test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_abs16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @aa:16
+ neg.l @long_dest:16 ; 16-bit absolute address
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5b, @long_dest
+ beq .Llabs16
+ fail
+.Llabs16:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+neg_l_abs32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; neg.l @aa:32
+ neg.l @long_dest:32 ; 32-bit absolute address
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x17b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Llabs32
+ fail
+.Llabs32:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif ; h8sx
+.endif ; h8/300
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'nop'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+nop: set_grs_a5a5
+ set_ccr_zero
+
+ nop
+
+ test_cc_clear
+ test_grs_a5a5
+
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'not.b, not.w, not.l'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # not.b rd ; 1 7 0 rd
+ # not.b @erd ; 7 d rd ???? 1 7 0 ignore
+ # not.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 0 ignore
+ # not.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 0 ignore
+ # not.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 0 ignore
+ # not.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 0 ignore
+ # not.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 0 ignore
+ # not.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 0 ignore
+ # not.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 0 ignore
+ # not.b @aa:16 ; 6 a 1 1??? aa:16 1 7 0 ignore
+ # not.b @aa:32 ; 6 a 3 1??? aa:32 1 7 0 ignore
+ # word operations
+ # long operations
+ #
+ # Coming soon:
+ # not.b @aa:8 ; 7 f aaaaaaaa 1 7 0 ignore
+ #
+
+.data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+ start
+
+ #
+ # 8-bit byte operations
+ #
+
+not_b_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; not.b Rd
+ not r0l ; 8-bit register
+;;; .word 0x1708
+
+ cmp.b #0x5a, r0l ; result of "not 0xa5"
+ beq .Lbrd
+ fail
+.Lbrd:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa55a r0 ; r0 changed by 'not'
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a55a er0 ; er0 changed by 'not'
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+not_b_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @eRd
+ mov #byte_dest, er0
+ not.b @er0 ; register indirect operand
+;;; .word 0x7d00
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ cmp.b #0x5a:8, @er0 ; memory contents changed
+ beq .Lbind
+ fail
+.Lbind:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @eRd+
+ mov #byte_dest, er0 ; register post-increment operand
+ not.b @er0+
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one
+ cmp.b #0xa5:8, @-er0
+ beq .Lbpostinc
+ fail
+.Lbpostinc:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @eRd-
+ mov #byte_dest, er0 ; register post-decrement operand
+ not.b @er0-
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
+ cmp.b #0x5a:8, @+er0
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0xa05a
+ beq .Lbpostdec
+ fail
+.Lbpostdec:
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @+eRd
+ mov #byte_dest-1, er0
+ not.b @+er0 ; reg pre-increment operand
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5:8, @er0
+ beq .Lbpreinc
+ fail
+.Lbpreinc:
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @-eRd
+ mov #byte_dest+1, er0
+ not.b @-er0 ; reg pre-decr operand
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.b #0x5a:8, @er0
+ beq .Lbpredec
+ fail
+.Lbpredec:
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_disp2dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @(dd:2, erd)
+ mov #byte_dest-1, er0
+ not.b @(1:2, er0) ; reg plus 2-bit displacement
+;;; .word 0x0175
+;;; .word 0x6808
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5:8, @+er0
+ beq .Lbdisp2
+ fail
+.Lbdisp2:
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_disp16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @(dd:16, erd)
+ mov #byte_dest+100, er0
+ not.b @(-100:16, er0) ; reg plus 16-bit displacement
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word -100
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.b #0x5a:8, @byte_dest
+ beq .Lbdisp16
+ fail
+.Lbdisp16:
+ test_h_gr32 byte_dest+100 er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_disp32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @(dd:32, erd)
+ mov #byte_dest-0xfffff, er0
+ not.b @(0xfffff:32, er0) ; reg plus 32-bit displacement
+;;; .word 0x7804
+;;; .word 0x6a28
+;;; .long 0xfffff
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5:8, @byte_dest
+ beq .Lbdisp32
+ fail
+.Lbdisp32:
+ test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_abs16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @aa:16
+ not.b @byte_dest:16 ; 16-bit absolute address
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.b #0x5a:8, @byte_dest
+ beq .Lbabs16
+ fail
+.Lbabs16:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_b_abs32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.b @aa:32
+ not.b @byte_dest:32 ; 32-bit absolute address
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x1700
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.b #0xa5:8, @byte_dest
+ beq .Lbabs32
+ fail
+.Lbabs32:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+ #
+ # 16-bit word operations
+ #
+
+.if (sim_cpu) ; any except plain-vanilla h8/300
+not_w_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; not.w Rd
+ not r1 ; 16-bit register operand
+;;; .word 0x1711
+
+ cmp.w #0x5a5a, r1 ; result of "not 0xa5a5"
+ beq .Lwrd
+ fail
+.Lwrd:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr32 0xa5a55a5a er1 ; er1 changed by 'not'
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+not_w_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @eRd
+ mov #word_dest, er1
+ not.w @er1 ; register indirect operand
+;;; .word 0x0154
+;;; .word 0x6d18
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5a, @word_dest ; memory contents changed
+ beq .Lwind
+ fail
+.Lwind:
+ test_h_gr32 word_dest er1 ; er1 still contains address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @eRd+
+ mov #word_dest, er1 ; register post-increment operand
+ not.w @er1+
+;;; .word 0x0154
+;;; .word 0x6d18
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwpostinc
+ fail
+.Lwpostinc:
+ test_h_gr32 word_dest+2 er1 ; er1 contains address plus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @eRd-
+ mov #word_dest, er1
+ not.w @er1-
+;;; .word 0x0156
+;;; .word 0x6d18
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5a, @word_dest
+ beq .Lwpostdec
+ fail
+.Lwpostdec:
+ test_h_gr32 word_dest-2 er1 ; er1 contains address minus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @+eRd
+ mov #word_dest-2, er1
+ not.w @+er1 ; reg pre-increment operand
+;;; .word 0x0155
+;;; .word 0x6d18
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwpreinc
+ fail
+.Lwpreinc:
+ test_h_gr32 word_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @-eRd
+ mov #word_dest+2, er1
+ not.w @-er1 ; reg pre-decr operand
+;;; .word 0x0157
+;;; .word 0x6d18
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5a, @word_dest
+ beq .Lwpredec
+ fail
+.Lwpredec:
+ test_h_gr32 word_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_disp2dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @(dd:2, erd)
+ mov #word_dest-1, er1
+ not.w @(1:2, er1) ; reg plus 2-bit displacement
+;;; .word 0x0155
+;;; .word 0x6918
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwdisp2
+ fail
+.Lwdisp2:
+ test_h_gr32 word_dest-1 er1 ; er1 contains address minus one
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_disp16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @(dd:16, erd)
+ mov #word_dest+100, er1
+ not.w @(-100:16, er1) ; reg plus 16-bit displacement
+;;; .word 0x0154
+;;; .word 0x6f18
+;;; .word -100
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5a, @word_dest
+ beq .Lwdisp16
+ fail
+.Lwdisp16:
+ test_h_gr32 word_dest+100 er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_disp32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @(dd:32, erd)
+ mov #word_dest-0xfffff, er1
+ not.w @(0xfffff:32, er1) ; reg plus 32-bit displacement
+;;; .word 0x7814
+;;; .word 0x6b28
+;;; .long 0xfffff
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwdisp32
+ fail
+.Lwdisp32:
+ test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_abs16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @aa:16
+ not.w @word_dest:16 ; 16-bit absolute address
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.w #0x5a5a, @word_dest
+ beq .Lwabs16
+ fail
+.Lwabs16:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_w_abs32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.w @aa:32
+ not.w @word_dest:32 ; 32-bit absolute address
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1710
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.w #0xa5a5, @word_dest
+ beq .Lwabs32
+ fail
+.Lwabs32:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif ; h8sx
+.endif ; h8/300
+
+ #
+ # 32-bit word operations
+ #
+
+.if (sim_cpu) ; any except plain-vanilla h8/300
+not_l_reg16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; not.l eRd
+ not er1 ; 32-bit register operand
+;;; .word 0x1731
+
+ cmp.l #0x5a5a5a5a, er1 ; result of "not 0xa5a5a5a5"
+ beq .Llrd
+ fail
+.Llrd:
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr32 0x5a5a5a5a er1 ; er1 changed by 'not'
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+not_l_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @eRd
+ mov #long_dest, er1
+ not.l @er1 ; register indirect operand
+;;; .word 0x0104
+;;; .word 0x6d18
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5a, @long_dest ; memory contents changed
+ beq .Llind
+ fail
+.Llind:
+ test_h_gr32 long_dest er1 ; er1 still contains address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @eRd+
+ mov #long_dest, er1 ; register post-increment operand
+ not.l @er1+
+;;; .word 0x0104
+;;; .word 0x6d18
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Llpostinc
+ fail
+.Llpostinc:
+ test_h_gr32 long_dest+4 er1 ; er1 contains address plus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @eRd-
+ mov #long_dest, er1
+ not.l @er1-
+;;; .word 0x0106
+;;; .word 0x6d18
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5a, @long_dest
+ beq .Llpostdec
+ fail
+.Llpostdec:
+ test_h_gr32 long_dest-4 er1 ; er1 contains address minus two
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_rdpreinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @+eRd
+ mov #long_dest-4, er1
+ not.l @+er1 ; reg pre-increment operand
+;;; .word 0x0105
+;;; .word 0x6d18
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Llpreinc
+ fail
+.Llpreinc:
+ test_h_gr32 long_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_rdpredec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @-eRd
+ mov #long_dest+4, er1
+ not.l @-er1 ; reg pre-decr operand
+;;; .word 0x0107
+;;; .word 0x6d18
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5a, @long_dest
+ beq .Llpredec
+ fail
+.Llpredec:
+ test_h_gr32 long_dest er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_disp2dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @(dd:2, erd)
+ mov #long_dest-1, er1
+ not.l @(1:2, er1) ; reg plus 2-bit displacement
+;;; .word 0x0105
+;;; .word 0x6918
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Lldisp2
+ fail
+.Lldisp2:
+ test_h_gr32 long_dest-1 er1 ; er1 contains address minus one
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_disp16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @(dd:16, erd)
+ mov #long_dest+100, er1
+ not.l @(-100:16, er1) ; reg plus 16-bit displacement
+;;; .word 0x0104
+;;; .word 0x6f18
+;;; .word -100
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5a, @long_dest
+ beq .Lldisp16
+ fail
+.Lldisp16:
+ test_h_gr32 long_dest+100 er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_disp32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @(dd:32, erd)
+ mov #long_dest-0xfffff, er1
+ not.l @(0xfffff:32, er1) ; reg plus 32-bit displacement
+;;; .word 0x7894
+;;; .word 0x6b28
+;;; .long 0xfffff
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Lldisp32
+ fail
+.Lldisp32:
+ test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_abs16dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @aa:16
+ not.l @long_dest:16 ; 16-bit absolute address
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ cmp.l #0x5a5a5a5a, @long_dest
+ beq .Llabs16
+ fail
+.Llabs16:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+not_l_abs32dst:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; not.l @aa:32
+ not.l @long_dest:32 ; 32-bit absolute address
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x1730
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ cmp.l #0xa5a5a5a5, @long_dest
+ beq .Llabs32
+ fail
+.Llabs32:
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif ; h8sx
+.endif ; h8/300
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'or.b'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # or.b #xx:8, rd ; c rd xxxxxxxx
+ # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx
+ # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
+ # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
+ # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
+ # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
+ # or.b rs, rd ; 1 4 rs rd
+ # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ????
+ # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs
+ # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs
+ # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs
+ # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs
+ #
+
+ # Coming soon:
+ # ...
+
+.data
+pre_byte: .byte 0
+byte_dest: .byte 0xa5
+post_byte: .byte 0
+
+ start
+
+or_b_imm8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; or.b #xx:8,Rd
+ or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5af r0 ; or result: a5 | aa
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+or_b_imm8_rdind:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b #xx:8,@eRd
+ mov #byte_dest, er0
+ or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x7d00
+;;; .word 0xc0aa
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest, er0 ; er0 still contains address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xaf, r0l
+ beq .L1
+ fail
+.L1:
+
+or_b_imm8_rdpostinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b #xx:8,@eRd+
+ mov #byte_dest, er0
+ or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0xc055
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 post_byte, er0 ; er0 contains address plus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xf5, r0l
+ beq .L2
+ fail
+.L2:
+
+or_b_imm8_rdpostdec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b #xx:8,@eRd-
+ mov #byte_dest, er0
+ or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0xc0aa
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 pre_byte, er0 ; er0 contains address minus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xaf, r0l
+ beq .L3
+ fail
+.L3:
+
+or_b_imm8_rdpreinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b #xx:8,@+eRd
+ mov #pre_byte, er0
+ or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0xc055
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest, er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xf5, r0l
+ beq .L4
+ fail
+.L4:
+
+or_b_imm8_rdpredec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b #xx:8,@-eRd
+ mov #post_byte, er0
+ or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0xc0aa
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest, er0 ; er0 contains destination address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xaf, r0l
+ beq .L5
+ fail
+.L5:
+
+
+.endif
+
+or_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; or.b Rs,Rd
+ mov.b #0xaa, r0h
+ or.b r0h, r0l ; Reg8 src, reg8 dest
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xaaaf r0 ; or result: a5 | aa
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+or_b_reg8_rdind:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b rs8,@eRd ; or reg8 to register indirect
+ mov #byte_dest, er0
+ mov #0xaa, r1l
+ or.b r1l, @er0 ; reg8 src, reg indirect dest
+;;; .word 0x7d00
+;;; .word 0x1490
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xaf, r0l
+ beq .L6
+ fail
+.L6:
+
+or_b_reg8_rdpostinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment
+ mov #byte_dest, er0
+ mov #0x55, r1l
+ or.b r1l, @er0+ ; reg8 src, reg post-incr dest
+;;; .word 0x0179
+;;; .word 0x8049
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 post_byte er0 ; er0 contains address plus one
+ test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xf5, r0l
+ beq .L7
+ fail
+.L7:
+
+or_b_reg8_rdpostdec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement
+ mov #byte_dest, er0
+ mov #0xaa, r1l
+ or.b r1l, @er0- ; reg8 src, reg post-decr dest
+;;; .word 0x0179
+;;; .word 0xa049
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xaf, r0l
+ beq .L8
+ fail
+.L8:
+
+or_b_reg8_rdpreinc:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment
+ mov #pre_byte, er0
+ mov #0x55, r1l
+ or.b r1l, @+er0 ; reg8 src, reg pre-incr dest
+;;; .word 0x0179
+;;; .word 0x9049
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xf5, r0l
+ beq .L9
+ fail
+.L9:
+
+or_b_reg8_rdpredec:
+ mov #byte_dest, er0
+ mov.b #0xa5, r1l
+ mov.b r1l, @er0
+
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement
+ mov #post_byte, er0
+ mov #0xaa, r1l
+ or.b r1l, @-er0 ; reg8 src, reg pre-decr dest
+;;; .word 0x0179
+;;; .word 0xb049
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0 ; er0 contains destination address
+ test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xaf, r0l
+ beq .L10
+ fail
+.L10:
+
+orc_imm8_ccr:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; orc #xx:8,ccr
+
+ test_neg_clear
+ orc #0x8, ccr ; Immediate 8-bit operand (neg flag)
+ test_neg_set
+
+ test_zero_clear
+ orc #0x4, ccr ; Immediate 8-bit operand (zero flag)
+ test_zero_set
+
+ test_ovf_clear
+ orc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
+ test_ovf_set
+
+ test_carry_clear
+ orc #0x1, ccr ; Immediate 8-bit operand (carry flag)
+ test_carry_set
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'or.l'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
+or_l_imm16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; or.l #xx:16,Rd
+ or.l #0xaaaa, er0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+or_l_imm32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; or.l #xx:32,Rd
+ or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+or_l_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; or.l Rs,Rd
+ mov.l #0xaaaaaaaa, er1
+ or.l er1, er0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
+ test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'or.w'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+or_w_imm16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; or.w #xx:16,Rd
+ or.w #0xaaaa, r0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+or_w_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; or.w Rs,Rd
+ mov.w #0xaaaa, r1
+ or.w r1, r0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
+ test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
+ test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'rotl'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+rotl_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotl.b r0l ; shift left arithmetic by one
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a54b er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotl_b_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotl.b @er0 ; shift right arithmetic by one, indirect
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0100 1011
+ cmp.b #0x4b, @byte_dest
+ beq .Lbind1
+ fail
+.Lbind1:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexb16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r0l
+ rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0100 1011
+ cmp.b #0x4b, @byte_dest
+ beq .Lbindexb161
+ fail
+.Lbindexb161:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexw16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r0
+ rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a50100 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0100 1011
+ cmp.b #0x4b, @byte_dest
+ beq .Lbindexw161
+ fail
+.Lbindexw161:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexl16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er0
+ rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xffffffff er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0100 1011
+ cmp.b #0x4b, @byte_dest
+ beq .Lbindexl161
+ fail
+.Lbindexl161:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexb32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r1l
+ rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0100 1011
+ cmp.b #0x4b, @byte_dest
+ beq .Lbindexb321
+ fail
+.Lbindexb321:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexw32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r1
+ rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a50100 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0100 1011
+ cmp.b #0x4b, @byte_dest
+ beq .Lbindexw321
+ fail
+.Lbindexw321:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexl32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er1
+ rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xffffffff er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0100 1011
+ cmp.b #0x4b, @byte_dest
+ beq .Lbindexl321
+ fail
+.Lbindexl321:
+ mov.b #0xa5, @byte_dest
+
+.endif
+
+rotl_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotl.b #2, r0l ; shift left arithmetic by two
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a596 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotl_b_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotl.b #2, @er0 ; shift right arithmetic by one, indirect
+
+ test_carry_clear ; H=0 N=1 Z=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1001 0110
+ cmp.b #0x96, @byte_dest
+ beq .Lbind2
+ fail
+.Lbind2:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexb16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r0l
+ rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a5a505 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1001 0110
+ cmp.b #0x96, @byte_dest
+ beq .Lbindexb162
+ fail
+.Lbindexb162:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexw16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r0
+ rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word
+
+ test_carry_clear ; H=0 N=1 Z=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a50100 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1001 0110
+ cmp.b #0x96, @byte_dest
+ beq .Lbindexw162
+ fail
+.Lbindexw162:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexl16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er0
+ rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long
+
+ test_carry_clear ; H=0 N=1 Z=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xffffffff er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1001 0110
+ cmp.b #0x96, @byte_dest
+ beq .Lbindexl162
+ fail
+.Lbindexl162:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexb32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r1l
+ rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1001 0110
+ cmp.b #0x96, @byte_dest
+ beq .Lbindexb322
+ fail
+.Lbindexb322:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexw32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r1
+ rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word
+
+ test_carry_clear ; H=0 N=1 Z=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a50100 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1001 0110
+ cmp.b #0x96, @byte_dest
+ beq .Lbindexw322
+ fail
+.Lbindexw322:
+ mov.b #0xa5, @byte_dest
+
+rotl_b_indexl32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er1
+ rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long
+
+ test_carry_clear ; H=0 N=1 Z=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xffffffff er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1001 0110
+ cmp.b #0x96, @byte_dest
+ beq .Lbindexl322
+ fail
+.Lbindexl322:
+ mov.b #0xa5, @byte_dest
+
+.endif
+
+.if (sim_cpu) ; Not available in h8300 mode
+rotl_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotl.w r0 ; shift left arithmetic by one
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
+ test_h_gr32 0xa5a54b4b er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotl_w_indexb16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r0l
+ rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
+ cmp.w #0x4b4b, @word_dest
+ beq .Lwindexb161
+ fail
+.Lwindexb161:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexw16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r0
+ rotl.w @(word_dest-512:16, r0.w) ; indexed word/word
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a50100 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
+ cmp.w #0x4b4b, @word_dest
+ beq .Lwindexw161
+ fail
+.Lwindexw161:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexl16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er0
+ rotl.w @(word_dest+2:16, er0.l) ; indexed word/long
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xffffffff er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
+ cmp.w #0x4b4b, @word_dest
+ beq .Lwindexl161
+ fail
+.Lwindexl161:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexb32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r1l
+ rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
+ cmp.w #0x4b4b, @word_dest
+ beq .Lwindexb321
+ fail
+.Lwindexb321:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexw32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r1
+ rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a50100 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
+ cmp.w #0x4b4b, @word_dest
+ beq .Lwindexw321
+ fail
+.Lwindexw321:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexl32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er1
+ rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xffffffff er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
+ cmp.w #0x4b4b, @word_dest
+ beq .Lwindexl321
+ fail
+.Lwindexl321:
+ mov.w #0xa5a5, @word_dest
+.endif
+
+rotl_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotl.w #2, r0 ; shift left arithmetic by two
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
+ test_h_gr32 0xa5a59696 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotl_w_indexb16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r0l
+ rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a5a505 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
+ cmp.w #0x9696, @word_dest
+ beq .Lwindexb162
+ fail
+.Lwindexb162:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexw16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r0
+ rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a50100 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
+ cmp.w #0x9696, @word_dest
+ beq .Lwindexw162
+ fail
+.Lwindexw162:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexl16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er0
+ rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xffffffff er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
+ cmp.w #0x9696, @word_dest
+ beq .Lwindexl162
+ fail
+.Lwindexl162:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexb32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r1l
+ rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
+ cmp.w #0x9696, @word_dest
+ beq .Lwindexb322
+ fail
+.Lwindexb322:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexw32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r1
+ rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a50100 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
+ cmp.w #0x9696, @word_dest
+ beq .Lwindexw322
+ fail
+.Lwindexw322:
+ mov.w #0xa5a5, @word_dest
+
+rotl_w_indexl32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er1
+ rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xffffffff er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
+ cmp.w #0x9696, @word_dest
+ beq .Lwindexl322
+ fail
+.Lwindexl322:
+ mov.w #0xa5a5, @word_dest
+.endif
+
+rotl_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotl.l er0 ; shift left arithmetic by one
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1011
+ test_h_gr32 0x4b4b4b4b er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotl_l_indexb16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r0l
+ rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1011
+ cmp.l #0x4b4b4b4b, @long_dest
+ beq .Llindexb161
+ fail
+.Llindexb161:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexw16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r0
+ rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a50100 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1011
+ cmp.l #0x4b4b4b4b, @long_dest
+ beq .Llindexw161
+ fail
+.Llindexw161:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexl16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er0
+ rotl.l @(long_dest+4:16, er0.l) ; indexed long/long
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xffffffff er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1011
+ cmp.l #0x4b4b4b4b, @long_dest
+ beq .Llindexl161
+ fail
+.Llindexl161:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexb32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r1l
+ rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1011
+ cmp.l #0x4b4b4b4b, @long_dest
+ beq .Llindexb321
+ fail
+.Llindexb321:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexw32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r1
+ rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xa5a50100 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1011
+ cmp.l #0x4b4b4b4b, @long_dest
+ beq .Llindexw321
+ fail
+.Llindexw321:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexl32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er1
+ rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 0xffffffff er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1011
+ cmp.l #0x4b4b4b4b, @long_dest
+ beq .Llindexl321
+ fail
+.Llindexl321:
+ mov.l #0xa5a5a5a5, @long_dest
+.endif
+
+rotl_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotl.l #2, er0 ; shift left arithmetic by two
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0110
+ test_h_gr32 0x96969696 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotl_l_indexb16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r0l
+ rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a5a505 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0110
+ cmp.l #0x96969696, @long_dest
+ beq .Llindexb162
+ fail
+.Llindexb162:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexw16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r0
+ rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a50100 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0110
+ cmp.l #0x96969696, @long_dest
+ beq .Llindexw162
+ fail
+.Llindexw162:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexl16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er0
+ rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xffffffff er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0110
+ cmp.l #0x96969696, @long_dest
+ beq .Llindexl162
+ fail
+.Llindexl162:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexb32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.b #5, r1l
+ rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0110
+ cmp.l #0x96969696, @long_dest
+ beq .Llindexb322
+ fail
+.Llindexb322:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexw32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.w #256, r1
+ rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xa5a50100 er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0110
+ cmp.l #0x96969696, @long_dest
+ beq .Llindexw322
+ fail
+.Llindexw322:
+ mov.l #0xa5a5a5a5, @long_dest
+
+rotl_l_indexl32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov.l #0xffffffff, er1
+ rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 0xffffffff er1
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0110
+ cmp.l #0x96969696, @long_dest
+ beq .Llindexl322
+ fail
+.Llindexl322:
+ mov.l #0xa5a5a5a5, @long_dest
+.endif
+.endif
+
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'rotr'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+rotr_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.b r0l ; shift right arithmetic by one
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a5d2 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotr_b_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotr.b @er0 ; shift right arithmetic by one, indirect
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbind1
+ fail
+.Lbind1:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotr.b @er0+ ; shift right arithmetic by one, postinc
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpostinc1
+ fail
+.Lbpostinc1:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotr.b @er0- ; shift right arithmetic by one, postdec
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpostdec1
+ fail
+.Lbpostdec1:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ rotr.b @+er0 ; shift right arithmetic by one, preinc
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpreinc1
+ fail
+.Lbpreinc1:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ rotr.b @-er0 ; shift right arithmetic by one, predec
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpredec1
+ fail
+.Lbpredec1:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ rotr.b @(2:2, er0) ; shift right arithmetic by one, disp2
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbdisp21
+ fail
+.Lbdisp21:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ rotr.b @(44:16, er0) ; shift right arithmetic by one, disp16
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbdisp161
+ fail
+.Lbdisp161:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ rotr.b @(666:32, er0) ; shift right arithmetic by one, disp32
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbdisp321
+ fail
+.Lbdisp321:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.b @byte_dest:16 ; shift right arithmetic by one, abs16
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbabs161
+ fail
+.Lbabs161:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.b @byte_dest:32 ; shift right arithmetic by one, abs32
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbabs321
+ fail
+.Lbabs321:
+ mov.b #0xa5, @byte_dest
+.endif
+
+rotr_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.b #2, r0l ; shift right arithmetic by two
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0xa569 r0 ; 1010 0101 -> 0110 1001
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a569 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotr_b_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotr.b #2, @er0 ; shift right arithmetic by two, indirect
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbind2
+ fail
+.Lbind2:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotr.b #2, @er0+ ; shift right arithmetic by two, postinc
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbpostinc2
+ fail
+.Lbpostinc2:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotr.b #2, @er0- ; shift right arithmetic by two, postdec
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbpostdec2
+ fail
+.Lbpostdec2:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ rotr.b #2, @+er0 ; shift right arithmetic by two, preinc
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbpreinc2
+ fail
+.Lbpreinc2:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ rotr.b #2, @-er0 ; shift right arithmetic by two, predec
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbpredec2
+ fail
+.Lbpredec2:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ rotr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbdisp22
+ fail
+.Lbdisp22:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ rotr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbdisp162
+ fail
+.Lbdisp162:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ rotr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbdisp322
+ fail
+.Lbdisp322:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbabs162
+ fail
+.Lbabs162:
+ mov.b #0xa5, @byte_dest
+
+rotr_b_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0110 1001
+ cmp.b #0x69, @byte_dest
+ beq .Lbabs322
+ fail
+.Lbabs322:
+ mov.b #0xa5, @byte_dest
+.endif
+
+.if (sim_cpu) ; Not available in h8300 mode
+rotr_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.w r0 ; shift right arithmetic by one
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ test_h_gr32 0xa5a5d2d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotr_w_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotr.w @er0 ; shift right arithmetic by one, indirect
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwind1
+ fail
+.Lwind1:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotr.w @er0+ ; shift right arithmetic by one, postinc
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpostinc1
+ fail
+.Lwpostinc1:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotr.w @er0- ; shift right arithmetic by one, postdec
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpostdec1
+ fail
+.Lwpostdec1:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotr.w @+er0 ; shift right arithmetic by one, preinc
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpreinc1
+ fail
+.Lwpreinc1:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ rotr.w @-er0 ; shift right arithmetic by one, predec
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpredec1
+ fail
+.Lwpredec1:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotr.w @(2:2, er0) ; shift right arithmetic by one, disp2
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwdisp21
+ fail
+.Lwdisp21:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ rotr.w @(44:16, er0) ; shift right arithmetic by one, disp16
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwdisp161
+ fail
+.Lwdisp161:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ rotr.w @(666:32, er0) ; shift right arithmetic by one, disp32
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwdisp321
+ fail
+.Lwdisp321:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.w @word_dest:16 ; shift right arithmetic by one, abs16
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwabs161
+ fail
+.Lwabs161:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.w @word_dest:32 ; shift right arithmetic by one, abs32
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwabs321
+ fail
+.Lwabs321:
+ mov.w #0xa5a5, @word_dest
+.endif
+
+rotr_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.w #2, r0 ; shift right arithmetic by two
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0x6969 r0 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ test_h_gr32 0xa5a56969 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotr_w_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotr.w #2, @er0 ; shift right arithmetic by two, indirect
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwind2
+ fail
+.Lwind2:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotr.w #2, @er0+ ; shift right arithmetic by two, postinc
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwpostinc2
+ fail
+.Lwpostinc2:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotr.w #2, @er0- ; shift right arithmetic by two, postdec
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwpostdec2
+ fail
+.Lwpostdec2:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotr.w #2, @+er0 ; shift right arithmetic by two, preinc
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwpreinc2
+ fail
+.Lwpreinc2:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ rotr.w #2, @-er0 ; shift right arithmetic by two, predec
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwpredec2
+ fail
+.Lwpredec2:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotr.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwdisp22
+ fail
+.Lwdisp22:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ rotr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwdisp162
+ fail
+.Lwdisp162:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ rotr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwdisp322
+ fail
+.Lwdisp322:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwabs162
+ fail
+.Lwabs162:
+ mov.w #0xa5a5, @word_dest
+
+rotr_w_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
+ cmp.w #0x6969, @word_dest
+ beq .Lwabs322
+ fail
+.Lwabs322:
+ mov.w #0xa5a5, @word_dest
+.endif
+
+rotr_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.l er0 ; shift right arithmetic by one, register
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ test_h_gr32 0xd2d2d2d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotr_l_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotr.l @er0 ; shift right arithmetic by one, indirect
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llind1
+ fail
+.Llind1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotr.l @er0+ ; shift right arithmetic by one, postinc
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpostinc1
+ fail
+.Llpostinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotr.l @er0- ; shift right arithmetic by one, postdec
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpostdec1
+ fail
+.Llpostdec1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ rotr.l @+er0 ; shift right arithmetic by one, preinc
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpreinc1
+ fail
+.Llpreinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ rotr.l @-er0 ; shift right arithmetic by one, predec
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpredec1
+ fail
+.Llpredec1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ rotr.l @(2:2, er0) ; shift right arithmetic by one, disp2
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Lldisp21
+ fail
+.Lldisp21:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ rotr.l @(44:16, er0) ; shift right arithmetic by one, disp16
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Lldisp161
+ fail
+.Lldisp161:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ rotr.l @(666:32, er0) ; shift right arithmetic by one, disp32
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Lldisp321
+ fail
+.Lldisp321:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.l @long_dest:16 ; shift right arithmetic by one, abs16
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llabs161
+ fail
+.Llabs161:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.l @long_dest:32 ; shift right arithmetic by one, abs32
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llabs321
+ fail
+.Llabs321:
+ mov #0xa5a5a5a5, @long_dest
+.endif
+
+rotr_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.l #2, er0 ; shift right arithmetic by two, register
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ test_h_gr32 0x69696969 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+
+rotr_l_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotr.l #2, @er0 ; shift right arithmetic by two, indirect
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Llind2
+ fail
+.Llind2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotr.l #2, @er0+ ; shift right arithmetic by two, postinc
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Llpostinc2
+ fail
+.Llpostinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotr.l #2, @er0- ; shift right arithmetic by two, postdec
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Llpostdec2
+ fail
+.Llpostdec2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ rotr.l #2, @+er0 ; shift right arithmetic by two, preinc
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Llpreinc2
+ fail
+.Llpreinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ rotr.l #2, @-er0 ; shift right arithmetic by two, predec
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Llpredec2
+ fail
+.Llpredec2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ rotr.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Lldisp22
+ fail
+.Lldisp22:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ rotr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Lldisp162
+ fail
+.Lldisp162:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ rotr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Lldisp322
+ fail
+.Lldisp322:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Llabs162
+ fail
+.Llabs162:
+ mov #0xa5a5a5a5, @long_dest
+
+rotr_l_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x69696969, @long_dest
+ beq .Llabs322
+ fail
+.Llabs322:
+ mov #0xa5a5a5a5, @long_dest
+
+.endif
+.endif
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'rotxl'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+rotxl_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxl.b r0l ; shift left arithmetic by one
+;;; .word 0x1208
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a54a er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+rotxl_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxl.b #2, r0l ; shift left arithmetic by two
+;;; .word 0x1248
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xa595 r0 ; 1010 0101 -> 1001 0101
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a595 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu) ; Not available in h8300 mode
+rotxl_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxl.w r0 ; shift left arithmetic by one
+;;; .word 0x1210
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
+ test_h_gr32 0xa5a54b4a er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+rotxl_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxl.w #2, r0 ; shift left arithmetic by two
+;;; .word 0x1250
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0x9695 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0101
+ test_h_gr32 0xa5a59695 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+rotxl_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxl.l er0 ; shift left arithmetic by one
+;;; .word 1030
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1010
+ test_h_gr32 0x4b4b4b4a er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+rotxl_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxl.l #2, er0 ; shift left arithmetic by two
+;;; .word 0x1270
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0101
+ test_h_gr32 0x96969695 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'rotxr'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+rotxr_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.b r0l ; shift right arithmetic by one
+;;; .word 0x1308
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a552 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotxr_b_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotxr.b @er0 ; shift right arithmetic by one, indirect
+;;; .word 0x7d00
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbind1
+ fail
+.Lbind1:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotxr.b @er0+ ; shift right arithmetic by one, postinc
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpostinc1
+ fail
+.Lbpostinc1:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotxr.b @er0- ; shift right arithmetic by one, postdec
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpostdec1
+ fail
+.Lbpostdec1:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ rotxr.b @+er0 ; shift right arithmetic by one, preinc
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpreinc1
+ fail
+.Lbpreinc1:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ rotxr.b @-er0 ; shift right arithmetic by one, predec
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpredec1
+ fail
+.Lbpredec1:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2
+;;; .word 0x0176
+;;; .word 0x6808
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbdisp21
+ fail
+.Lbdisp21:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 44
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbdisp161
+ fail
+.Lbdisp161:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32
+;;; .word 0x7884
+;;; .word 0x6a28
+;;; .long 666
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbdisp321
+ fail
+.Lbdisp321:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbabs161
+ fail
+.Lbabs161:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x1300
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbabs321
+ fail
+.Lbabs321:
+ mov #0xa5a5a5a5, @byte_dest
+.endif
+
+rotxr_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.b #2, r0l ; shift right arithmetic by two
+;;; .word 0x1348
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a5a9 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotxr_b_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotxr.b #2, @er0 ; shift right arithmetic by two, indirect
+;;; .word 0x7d00
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbind2
+ fail
+.Lbind2:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbpostinc2
+ fail
+.Lbpostinc2:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ rotxr.b #2, @er0- ; shift right arithmetic by two, postdec
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbpostdec2
+ fail
+.Lbpostdec2:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbpreinc2
+ fail
+.Lbpreinc2:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ rotxr.b #2, @-er0 ; shift right arithmetic by two, predec
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbpredec2
+ fail
+.Lbpredec2:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+;;; .word 0x0176
+;;; .word 0x6808
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbdisp22
+ fail
+.Lbdisp22:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 44
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbdisp162
+ fail
+.Lbdisp162:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+;;; .word 0x7884
+;;; .word 0x6a28
+;;; .long 666
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbdisp322
+ fail
+.Lbdisp322:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbabs162
+ fail
+.Lbabs162:
+ mov #0xa5a5a5a5, @byte_dest
+
+rotxr_b_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x1340
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1010 1001
+ cmp.b #0xa9, @byte_dest
+ beq .Lbabs322
+ fail
+.Lbabs322:
+ mov #0xa5a5a5a5, @byte_dest
+.endif
+
+.if (sim_cpu) ; Not available in h8300 mode
+rotxr_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.w r0 ; shift right arithmetic by one
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ test_h_gr32 0xa5a552d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotxr_w_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotxr.w @er0 ; shift right arithmetic by one, indirect
+;;; .word 0x7d80
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwind1
+ fail
+.Lwind1:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotxr.w @er0+ ; shift right arithmetic by one, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpostinc1
+ fail
+.Lwpostinc1:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotxr.w @er0- ; shift right arithmetic by one, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpostdec1
+ fail
+.Lwpostdec1:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotxr.w @+er0 ; shift right arithmetic by one, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpreinc1
+ fail
+.Lwpreinc1:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ rotxr.w @-er0 ; shift right arithmetic by one, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpredec1
+ fail
+.Lwpredec1:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotxr.w @(2:2, er0) ; shift right arithmetic by one, disp2
+;;; .word 0x0156
+;;; .word 0xa908
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwdisp21
+ fail
+.Lwdisp21:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwdisp161
+ fail
+.Lwdisp161:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwdisp321
+ fail
+.Lwdisp321:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwabs161
+ fail
+.Lwabs161:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1310
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwabs321
+ fail
+.Lwabs321:
+ mov #0xa5a5a5a5, @word_dest
+.endif
+
+rotxr_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.w #2, r0 ; shift right arithmetic by two
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ test_h_gr32 0xa5a5a969 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotxr_w_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotxr.w #2, @er0 ; shift right arithmetic by two, indirect
+;;; .word 0x7d80
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwind2
+ fail
+.Lwind2:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwpostinc2
+ fail
+.Lwpostinc2:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ rotxr.w #2, @er0- ; shift right arithmetic by two, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwpostdec2
+ fail
+.Lwpostdec2:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwpreinc2
+ fail
+.Lwpreinc2:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ rotxr.w #2, @-er0 ; shift right arithmetic by two, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwpredec2
+ fail
+.Lwpredec2:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ rotxr.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+;;; .word 0x0156
+;;; .word 0xa908
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwdisp22
+ fail
+.Lwdisp22:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwdisp162
+ fail
+.Lwdisp162:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwdisp322
+ fail
+.Lwdisp322:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwabs162
+ fail
+.Lwabs162:
+ mov #0xa5a5a5a5, @word_dest
+
+rotxr_w_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1350
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
+ cmp.w #0xa969, @word_dest
+ beq .Lwabs322
+ fail
+.Lwabs322:
+ mov #0xa5a5a5a5, @word_dest
+.endif
+
+rotxr_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.l er0 ; shift right arithmetic by one, register
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ test_h_gr32 0x52d2d2d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+rotxr_l_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotxr.l @er0 ; shift right arithmetic by one, indirect
+;;; .word 0x0104
+;;; .word 0xa908
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llind1
+ fail
+.Llind1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotxr.l @er0+ ; shift right arithmetic by one, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpostinc1
+ fail
+.Llpostinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotxr.l @er0- ; shift right arithmetic by one, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpostdec1
+ fail
+.Llpostdec1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ rotxr.l @+er0 ; shift right arithmetic by one, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpreinc1
+ fail
+.Llpreinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ rotxr.l @-er0 ; shift right arithmetic by one, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpredec1
+ fail
+.Llpredec1:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ rotxr.l @(2:2, er0) ; shift right arithmetic by one, disp2
+;;; .word 0x0106
+;;; .word 0xa908
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Lldisp21
+ fail
+.Lldisp21:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Lldisp161
+ fail
+.Lldisp161:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Lldisp321
+ fail
+.Lldisp321:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llabs161
+ fail
+.Llabs161:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x1330
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llabs321
+ fail
+.Llabs321:
+ mov #0xa5a5a5a5, @long_dest
+.endif
+
+rotxr_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.l #2, er0 ; shift right arithmetic by two, register
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ test_h_gr32 0xa9696969 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+
+rotxr_l_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotxr.l #2, @er0 ; shift right arithmetic by two, indirect
+;;; .word 0x0104
+;;; .word 0xa908
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Llind2
+ fail
+.Llind2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Llpostinc2
+ fail
+.Llpostinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ rotxr.l #2, @er0- ; shift right arithmetic by two, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Llpostdec2
+ fail
+.Llpostdec2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Llpreinc2
+ fail
+.Llpreinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ rotxr.l #2, @-er0 ; shift right arithmetic by two, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Llpredec2
+ fail
+.Llpredec2:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ rotxr.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+;;; .word 0x0106
+;;; .word 0xa908
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Lldisp22
+ fail
+.Lldisp22:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Lldisp162
+ fail
+.Lldisp162:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Lldisp322
+ fail
+.Lldisp322:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Llabs162
+ fail
+.Llabs162:
+ mov #0xa5a5a5a5, @long_dest
+
+rotxr_l_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x1370
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xa9696969, @long_dest
+ beq .Llabs322
+ fail
+.Llabs322:
+ mov #0xa5a5a5a5, @long_dest
+
+.endif
+.endif
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'shal'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+shal_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shal.b r0l ; shift left arithmetic by one
+;;; .word 0x1088
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+; test_ovf_clear ; FIXME
+ test_neg_clear
+ test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a54a er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shal_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shal.b #2, r0l ; shift left arithmetic by two
+;;; .word 0x10c8
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+; test_ovf_clear ; FIXME
+ test_neg_set
+
+ test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a594 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu) ; Not available in h8300 mode
+shal_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shal.w r0 ; shift left arithmetic by one
+;;; .word 0x1090
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+; test_ovf_clear ; FIXME
+ test_neg_clear
+ test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
+ test_h_gr32 0xa5a54b4a er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shal_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shal.w #2, r0 ; shift left arithmetic by two
+;;; .word 0x10d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+; test_ovf_clear ; FIXME
+ test_neg_set
+ test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
+ test_h_gr32 0xa5a59694 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shal_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shal.l er0 ; shift left arithmetic by one
+;;; .word 10b0
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+; test_ovf_clear ; FIXME
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1010
+ test_h_gr32 0x4b4b4b4a er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shal_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shal.l #2, er0 ; shift left arithmetic by two
+;;; .word 0x10f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+; test_ovf_clear ; FIXME
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0100
+ test_h_gr32 0x96969694 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'shar'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+shar_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.b r0l ; shift right arithmetic by one
+;;; .word 0x1188
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a5d2 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shar_b_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shar.b @er0 ; shift right arithmetic by one, indirect
+;;; .word 0x7d00
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbind1
+ fail
+.Lbind1:
+ mov.b #0xa5, @byte_dest
+
+shar_b_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shar.b @er0+ ; shift right arithmetic by one, postinc
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpostinc1
+ fail
+.Lbpostinc1:
+ mov.b #0xa5, @byte_dest
+
+shar_b_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shar.b @er0- ; shift right arithmetic by one, postdec
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpostdec1
+ fail
+.Lbpostdec1:
+ mov.b #0xa5, @byte_dest
+
+shar_b_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ shar.b @+er0 ; shift right arithmetic by one, preinc
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpreinc1
+ fail
+.Lbpreinc1:
+ mov.b #0xa5, @byte_dest
+
+shar_b_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ shar.b @-er0 ; shift right arithmetic by one, predec
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbpredec1
+ fail
+.Lbpredec1:
+ mov.b #0xa5, @byte_dest
+
+shar_b_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ shar.b @(2:2, er0) ; shift right arithmetic by one, disp2
+;;; .word 0x0176
+;;; .word 0x6808
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbdisp21
+ fail
+.Lbdisp21:
+ mov.b #0xa5, @byte_dest
+
+shar_b_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ shar.b @(44:16, er0) ; shift right arithmetic by one, disp16
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 44
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbdisp161
+ fail
+.Lbdisp161:
+ mov.b #0xa5, @byte_dest
+
+shar_b_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ shar.b @(666:32, er0) ; shift right arithmetic by one, disp32
+;;; .word 0x7884
+;;; .word 0x6a28
+;;; .long 666
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbdisp321
+ fail
+.Lbdisp321:
+ mov.b #0xa5, @byte_dest
+
+shar_b_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.b @byte_dest:16 ; shift right arithmetic by one, abs16
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbabs161
+ fail
+.Lbabs161:
+ mov.b #0xa5, @byte_dest
+
+shar_b_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.b @byte_dest:32 ; shift right arithmetic by one, abs32
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x1180
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1101 0010
+ cmp.b #0xd2, @byte_dest
+ beq .Lbabs321
+ fail
+.Lbabs321:
+ mov.b #0xa5, @byte_dest
+.endif
+
+shar_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.b #2, r0l ; shift right arithmetic by two
+;;; .word 0x11c8
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a5e9 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shar_b_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shar.b #2, @er0 ; shift right arithmetic by two, indirect
+;;; .word 0x7d00
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbind2
+ fail
+.Lbind2:
+ mov.b #0xa5, @byte_dest
+
+shar_b_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shar.b #2, @er0+ ; shift right arithmetic by two, postinc
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbpostinc2
+ fail
+.Lbpostinc2:
+ mov.b #0xa5, @byte_dest
+
+shar_b_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shar.b #2, @er0- ; shift right arithmetic by two, postdec
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbpostdec2
+ fail
+.Lbpostdec2:
+ mov.b #0xa5, @byte_dest
+
+shar_b_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ shar.b #2, @+er0 ; shift right arithmetic by two, preinc
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbpreinc2
+ fail
+.Lbpreinc2:
+ mov.b #0xa5, @byte_dest
+
+shar_b_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ shar.b #2, @-er0 ; shift right arithmetic by two, predec
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbpredec2
+ fail
+.Lbpredec2:
+ mov.b #0xa5, @byte_dest
+
+shar_b_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+;;; .word 0x0176
+;;; .word 0x6808
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbdisp22
+ fail
+.Lbdisp22:
+ mov.b #0xa5, @byte_dest
+
+shar_b_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 44
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbdisp162
+ fail
+.Lbdisp162:
+ mov.b #0xa5, @byte_dest
+
+shar_b_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+;;; .word 0x7884
+;;; .word 0x6a28
+;;; .long 666
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbdisp322
+ fail
+.Lbdisp322:
+ mov.b #0xa5, @byte_dest
+
+shar_b_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbabs162
+ fail
+.Lbabs162:
+ mov.b #0xa5, @byte_dest
+
+shar_b_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x11c0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 1110 1001
+ cmp.b #0xe9, @byte_dest
+ beq .Lbabs322
+ fail
+.Lbabs322:
+ mov.b #0xa5, @byte_dest
+.endif
+
+.if (sim_cpu) ; Not available in h8300 mode
+shar_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.w r0 ; shift right arithmetic by one
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ test_h_gr32 0xa5a5d2d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shar_w_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shar.w @er0 ; shift right arithmetic by one, indirect
+;;; .word 0x7d80
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwind1
+ fail
+.Lwind1:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shar.w @er0+ ; shift right arithmetic by one, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpostinc1
+ fail
+.Lwpostinc1:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shar.w @er0- ; shift right arithmetic by one, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpostdec1
+ fail
+.Lwpostdec1:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shar.w @+er0 ; shift right arithmetic by one, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpreinc1
+ fail
+.Lwpreinc1:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ shar.w @-er0 ; shift right arithmetic by one, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwpredec1
+ fail
+.Lwpredec1:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shar.w @(2:2, er0) ; shift right arithmetic by one, disp2
+;;; .word 0x0156
+;;; .word 0x6908
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwdisp21
+ fail
+.Lwdisp21:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ shar.w @(44:16, er0) ; shift right arithmetic by one, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwdisp161
+ fail
+.Lwdisp161:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ shar.w @(666:32, er0) ; shift right arithmetic by one, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwdisp321
+ fail
+.Lwdisp321:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.w @word_dest:16 ; shift right arithmetic by one, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwabs161
+ fail
+.Lwabs161:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.w @word_dest:32 ; shift right arithmetic by one, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1190
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
+ cmp.w #0xd2d2, @word_dest
+ beq .Lwabs321
+ fail
+.Lwabs321:
+ mov.w #0xa5a5, @word_dest
+.endif
+
+shar_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.w #2, r0 ; shift right arithmetic by two
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ test_h_gr32 0xa5a5e969 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shar_w_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shar.w #2, @er0 ; shift right arithmetic by two, indirect
+;;; .word 0x7d80
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwind2
+ fail
+.Lwind2:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shar.w #2, @er0+ ; shift right arithmetic by two, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwpostinc2
+ fail
+.Lwpostinc2:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shar.w #2, @er0- ; shift right arithmetic by two, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwpostdec2
+ fail
+.Lwpostdec2:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shar.w #2, @+er0 ; shift right arithmetic by two, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwpreinc2
+ fail
+.Lwpreinc2:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ shar.w #2, @-er0 ; shift right arithmetic by two, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwpredec2
+ fail
+.Lwpredec2:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shar.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+;;; .word 0x0156
+;;; .word 0x6908
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwdisp22
+ fail
+.Lwdisp22:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwdisp162
+ fail
+.Lwdisp162:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwdisp322
+ fail
+.Lwdisp322:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwabs162
+ fail
+.Lwabs162:
+ mov.w #0xa5a5, @word_dest
+
+shar_w_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x11d0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
+ cmp.w #0xe969, @word_dest
+ beq .Lwabs322
+ fail
+.Lwabs322:
+ mov.w #0xa5a5, @word_dest
+.endif
+
+shar_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.l er0 ; shift right arithmetic by one, register
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ test_h_gr32 0xd2d2d2d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shar_l_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shar.l @er0 ; shift right arithmetic by one, indirect
+;;; .word 0x0104
+;;; .word 0x6908
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llind1
+ fail
+.Llind1:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shar.l @er0+ ; shift right arithmetic by one, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpostinc1
+ fail
+.Llpostinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shar.l @er0- ; shift right arithmetic by one, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpostdec1
+ fail
+.Llpostdec1:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ shar.l @+er0 ; shift right arithmetic by one, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpreinc1
+ fail
+.Llpreinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ shar.l @-er0 ; shift right arithmetic by one, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llpredec1
+ fail
+.Llpredec1:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ shar.l @(2:2, er0) ; shift right arithmetic by one, disp2
+;;; .word 0x0106
+;;; .word 0x6908
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Lldisp21
+ fail
+.Lldisp21:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ shar.l @(44:16, er0) ; shift right arithmetic by one, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Lldisp161
+ fail
+.Lldisp161:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ shar.l @(666:32, er0) ; shift right arithmetic by one, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Lldisp321
+ fail
+.Lldisp321:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.l @long_dest:16 ; shift right arithmetic by one, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llabs161
+ fail
+.Llabs161:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.l @long_dest:32 ; shift right arithmetic by one, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x11b0
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0xd2d2d2d2, @long_dest
+ beq .Llabs321
+ fail
+.Llabs321:
+ mov #0xa5a5a5a5, @long_dest
+.endif
+
+shar_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.l #2, er0 ; shift right arithmetic by two, register
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ test_h_gr32 0xe9696969 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+
+shar_l_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shar.l #2, @er0 ; shift right arithmetic by two, indirect
+;;; .word 0x0104
+;;; .word 0x6908
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Llind2
+ fail
+.Llind2:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shar.l #2, @er0+ ; shift right arithmetic by two, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Llpostinc2
+ fail
+.Llpostinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shar.l #2, @er0- ; shift right arithmetic by two, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Llpostdec2
+ fail
+.Llpostdec2:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ shar.l #2, @+er0 ; shift right arithmetic by two, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Llpreinc2
+ fail
+.Llpreinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ shar.l #2, @-er0 ; shift right arithmetic by two, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Llpredec2
+ fail
+.Llpredec2:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ shar.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2
+;;; .word 0x0106
+;;; .word 0x6908
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Lldisp22
+ fail
+.Lldisp22:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Lldisp162
+ fail
+.Lldisp162:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Lldisp322
+ fail
+.Lldisp322:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Llabs162
+ fail
+.Llabs162:
+ mov #0xa5a5a5a5, @long_dest
+
+shar_l_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x11f0
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0xe9696969, @long_dest
+ beq .Llabs322
+ fail
+.Llabs322:
+ mov #0xa5a5a5a5, @long_dest
+
+.endif
+.endif
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'shll'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+shll_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.b r0l ; shift left logical by one
+;;; .word 0x1008
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a54a er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shll_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.b #2, r0l ; shift left logical by two
+;;; .word 0x1048
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+
+ test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a594 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shll_b_reg8_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.b #4, r0l ; shift left logical by four
+;;; .word 0x10a8
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000
+ test_h_gr32 0xa5a5a550 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu) ; Not available in h8300 mode
+shll_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.w r0 ; shift left logical by one
+;;; .word 0x1010
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
+ test_h_gr32 0xa5a54b4a er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shll_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.w #2, r0 ; shift left logical by two
+;;; .word 0x1050
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
+ test_h_gr32 0xa5a59694 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shll_w_reg16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.w #4, r0 ; shift left logical by four
+;;; .word 0x1020
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000
+ test_h_gr32 0xa5a55a50 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shll_w_reg16_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.w #8, r0 ; shift left logical by eight
+;;; .word 0x1060
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000
+ test_h_gr32 0xa5a5a500 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+shll_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.l er0 ; shift left logical by one
+;;; .word 1030
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0100 1011 0100 1011 0100 1011 0100 1010
+ test_h_gr32 0x4b4b4b4a er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shll_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.l #2, er0 ; shift left logical by two
+;;; .word 0x1070
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1001 0110 1001 0110 1001 0110 1001 0100
+ test_h_gr32 0x96969694 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shll_l_reg32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.l #4, er0 ; shift left logical by four
+;;; .word 0x1038
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0101 1010 0101 1010 0101 1010 0101 0000
+ test_h_gr32 0x5a5a5a50 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shll_l_reg32_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.l #8, er0 ; shift left logical by eight
+;;; .word 0x1078
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0xa500 r0
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1010 0101 1010 0101 1010 0101 0000 0000
+ test_h_gr32 0xa5a5a500 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shll_l_reg32_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shll.l #16, er0 ; shift left logical by sixteen
+;;; .word 0x10f8
+
+ test_carry_set ; H=0 N=1 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 1010 0101 1010 0101 0000 0000 0000 0000
+ test_h_gr32 0xa5a50000 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+.endif
+
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'shlr'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+ .data
+byte_dest: .byte 0xa5
+ .align 2
+word_dest: .word 0xa5a5
+ .align 4
+long_dest: .long 0xa5a5a5a5
+
+ .text
+
+shlr_b_reg8_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b r0l ; shift right logical by one
+;;; .word 0x1108
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a552 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shlr_b_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b @er0 ; shift right logical by one, indirect
+;;; .word 0x7d00
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbind1
+ fail
+.Lbind1:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b @er0+ ; shift right logical by one, postinc
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpostinc1
+ fail
+.Lbpostinc1:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b @er0- ; shift right logical by one, postdec
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpostdec1
+ fail
+.Lbpostdec1:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ shlr.b @+er0 ; shift right logical by one, preinc
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpreinc1
+ fail
+.Lbpreinc1:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ shlr.b @-er0 ; shift right logical by one, predec
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbpredec1
+ fail
+.Lbpredec1:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ shlr.b @(2:2, er0) ; shift right logical by one, disp2
+;;; .word 0x0176
+;;; .word 0x6808
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbdisp21
+ fail
+.Lbdisp21:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ shlr.b @(44:16, er0) ; shift right logical by one, disp16
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 44
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbdisp161
+ fail
+.Lbdisp161:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ shlr.b @(666:32, er0) ; shift right logical by one, disp32
+;;; .word 0x7884
+;;; .word 0x6a28
+;;; .long 666
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbdisp321
+ fail
+.Lbdisp321:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b @byte_dest:16 ; shift right logical by one, abs16
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbabs161
+ fail
+.Lbabs161:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b @byte_dest:32 ; shift right logical by one, abs32
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x1100
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0101 0010
+ cmp.b #0x52, @byte_dest
+ beq .Lbabs321
+ fail
+.Lbabs321:
+ mov.b #0xa5, @byte_dest
+.endif
+
+shlr_b_reg8_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b #2, r0l ; shift right logical by two
+;;; .word 0x1148
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001
+.if (sim_cpu)
+ test_h_gr32 0xa5a5a529 er0
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shlr_b_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b #2, @er0 ; shift right logical by two, indirect
+;;; .word 0x7d00
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbind2
+ fail
+.Lbind2:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b #2, @er0+ ; shift right logical by two, postinc
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbpostinc2
+ fail
+.Lbpostinc2:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b #2, @er0- ; shift right logical by two, postdec
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbpostdec2
+ fail
+.Lbpostdec2:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ shlr.b #2, @+er0 ; shift right logical by two, preinc
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbpreinc2
+ fail
+.Lbpreinc2:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ shlr.b #2, @-er0 ; shift right logical by two, predec
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbpredec2
+ fail
+.Lbpredec2:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2
+;;; .word 0x0176
+;;; .word 0x6808
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbdisp22
+ fail
+.Lbdisp22:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 44
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbdisp162
+ fail
+.Lbdisp162:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32
+;;; .word 0x7884
+;;; .word 0x6a28
+;;; .long 666
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbdisp322
+ fail
+.Lbdisp322:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbabs162
+ fail
+.Lbabs162:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x1140
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0010 1001
+ cmp.b #0x29, @byte_dest
+ beq .Lbabs322
+ fail
+.Lbabs322:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_reg8_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b #4, r0l ; shift right logical by four
+;;; .word 0x11a8
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010
+ test_h_gr32 0xa5a5a50a er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shlr_b_ind_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b #4, @er0 ; shift right logical by four, indirect
+;;; .word 0x7d00
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbind4
+ fail
+.Lbind4:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_postinc_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b #4, @er0+ ; shift right logical by four, postinc
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest+1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbpostinc4
+ fail
+.Lbpostinc4:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_postdec_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest, er0
+ shlr.b #4, @er0- ; shift right logical by four, postdec
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-1 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbpostdec4
+ fail
+.Lbpostdec4:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_preinc_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-1, er0
+ shlr.b #4, @+er0 ; shift right logical by four, preinc
+;;; .word 0x0175
+;;; .word 0x6c08
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbpreinc4
+ fail
+.Lbpreinc4:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_predec_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest+1, er0
+ shlr.b #4, @-er0 ; shift right logical by four, predec
+;;; .word 0x0177
+;;; .word 0x6c08
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbpredec4
+ fail
+.Lbpredec4:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp2_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-2, er0
+ shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2
+;;; .word 0x0176
+;;; .word 0x6808
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbdisp24
+ fail
+.Lbdisp24:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-44, er0
+ shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16
+;;; .word 0x0174
+;;; .word 0x6e08
+;;; .word 44
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbdisp164
+ fail
+.Lbdisp164:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_disp32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #byte_dest-666, er0
+ shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32
+;;; .word 0x7884
+;;; .word 0x6a28
+;;; .long 666
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbdisp324
+ fail
+.Lbdisp324:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_abs16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16
+;;; .word 0x6a18
+;;; .word byte_dest
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbabs164
+ fail
+.Lbabs164:
+ mov.b #0xa5, @byte_dest
+
+shlr_b_abs32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32
+;;; .word 0x6a38
+;;; .long byte_dest
+;;; .word 0x11a0
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 -> 0000 1010
+ cmp.b #0x0a, @byte_dest
+ beq .Lbabs324
+ fail
+.Lbabs324:
+ mov.b #0xa5, @byte_dest
+.endif
+
+.if (sim_cpu == h8sx)
+shlr_w_imm5_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #15:5, r0 ; shift right logical by 5-bit immediate
+;;; .word 0x038f
+;;; .word 0x1110
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ ; 1010 0101 1010 0101 -> 0000 0000 0000 0001
+ test_h_gr32 0xa5a50001 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu) ; Not available in h8300 mode
+shlr_w_reg16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w r0 ; shift right logical by one
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ test_h_gr32 0xa5a552d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shlr_w_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w @er0 ; shift right logical by one, indirect
+;;; .word 0x7d80
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwind1
+ fail
+.Lwind1:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w @er0+ ; shift right logical by one, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpostinc1
+ fail
+.Lwpostinc1:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w @er0- ; shift right logical by one, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpostdec1
+ fail
+.Lwpostdec1:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w @+er0 ; shift right logical by one, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpreinc1
+ fail
+.Lwpreinc1:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ shlr.w @-er0 ; shift right logical by one, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwpredec1
+ fail
+.Lwpredec1:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w @(2:2, er0) ; shift right logical by one, disp2
+;;; .word 0x0156
+;;; .word 0x6908
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwdisp21
+ fail
+.Lwdisp21:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ shlr.w @(44:16, er0) ; shift right logical by one, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwdisp161
+ fail
+.Lwdisp161:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ shlr.w @(666:32, er0) ; shift right logical by one, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwdisp321
+ fail
+.Lwdisp321:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w @word_dest:16 ; shift right logical by one, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwabs161
+ fail
+.Lwabs161:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w @word_dest:32 ; shift right logical by one, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1110
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
+ cmp.w #0x52d2, @word_dest
+ beq .Lwabs321
+ fail
+.Lwabs321:
+ mov.w #0xa5a5, @word_dest
+.endif
+
+shlr_w_reg16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #2, r0 ; shift right logical by two
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ test_h_gr32 0xa5a52969 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shlr_w_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #2, @er0 ; shift right logical by two, indirect
+;;; .word 0x7d80
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwind2
+ fail
+.Lwind2:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #2, @er0+ ; shift right logical by two, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwpostinc2
+ fail
+.Lwpostinc2:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #2, @er0- ; shift right logical by two, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwpostdec2
+ fail
+.Lwpostdec2:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w #2, @+er0 ; shift right logical by two, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwpreinc2
+ fail
+.Lwpreinc2:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ shlr.w #2, @-er0 ; shift right logical by two, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwpredec2
+ fail
+.Lwpredec2:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w #2, @(2:2, er0) ; shift right logical by two, disp2
+;;; .word 0x0156
+;;; .word 0x6908
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwdisp22
+ fail
+.Lwdisp22:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwdisp162
+ fail
+.Lwdisp162:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwdisp322
+ fail
+.Lwdisp322:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #2, @word_dest:16 ; shift right logical by two, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwabs162
+ fail
+.Lwabs162:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #2, @word_dest:32 ; shift right logical by two, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1150
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
+ cmp.w #0x2969, @word_dest
+ beq .Lwabs322
+ fail
+.Lwabs322:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_reg16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #4, r0 ; shift right logical by four
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ test_h_gr32 0xa5a50a5a er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shlr_w_ind_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #4, @er0 ; shift right logical by four, indirect
+;;; .word 0x7d80
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwind4
+ fail
+.Lwind4:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postinc_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #4, @er0+ ; shift right logical by four, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwpostinc4
+ fail
+.Lwpostinc4:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postdec_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #4, @er0- ; shift right logical by four, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwpostdec4
+ fail
+.Lwpostdec4:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_preinc_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w #4, @+er0 ; shift right logical by four, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwpreinc4
+ fail
+.Lwpreinc4:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_predec_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ shlr.w #4, @-er0 ; shift right logical by four, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwpredec4
+ fail
+.Lwpredec4:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp2_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w #4, @(2:2, er0) ; shift right logical by four, disp2
+;;; .word 0x0156
+;;; .word 0x6908
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwdisp24
+ fail
+.Lwdisp24:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwdisp164
+ fail
+.Lwdisp164:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwdisp324
+ fail
+.Lwdisp324:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #4, @word_dest:16 ; shift right logical by four, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwabs164
+ fail
+.Lwabs164:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #4, @word_dest:32 ; shift right logical by four, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1120
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
+ cmp.w #0x0a5a, @word_dest
+ beq .Lwabs324
+ fail
+.Lwabs324:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_reg16_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #8, r0 ; shift right logical by eight
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ test_h_gr32 0xa5a500a5 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shlr_w_ind_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #8, @er0 ; shift right logical by eight, indirect
+;;; .word 0x7d80
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwind8
+ fail
+.Lwind8:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postinc_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #8, @er0+ ; shift right logical by eight, postinc
+;;; .word 0x0154
+;;; .word 0x6d08
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest+2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwpostinc8
+ fail
+.Lwpostinc8:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_postdec_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest, er0
+ shlr.w #8, @er0- ; shift right logical by eight, postdec
+;;; .word 0x0156
+;;; .word 0x6d08
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwpostdec8
+ fail
+.Lwpostdec8:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_preinc_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w #8, @+er0 ; shift right logical by eight, preinc
+;;; .word 0x0155
+;;; .word 0x6d08
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwpreinc8
+ fail
+.Lwpreinc8:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_predec_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest+2, er0
+ shlr.w #8, @-er0 ; shift right logical by eight, predec
+;;; .word 0x0157
+;;; .word 0x6d08
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwpredec8
+ fail
+.Lwpredec8:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp2_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-2, er0
+ shlr.w #8, @(2:2, er0) ; shift right logical by eight, disp2
+;;; .word 0x0156
+;;; .word 0x6908
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwdisp28
+ fail
+.Lwdisp28:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp16_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-44, er0
+ shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16
+;;; .word 0x0154
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwdisp168
+ fail
+.Lwdisp168:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_disp32_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #word_dest-666, er0
+ shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 word_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwdisp328
+ fail
+.Lwdisp328:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs16_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16
+;;; .word 0x6b18
+;;; .word word_dest
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwabs168
+ fail
+.Lwabs168:
+ mov.w #0xa5a5, @word_dest
+
+shlr_w_abs32_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32
+;;; .word 0x6b38
+;;; .long word_dest
+;;; .word 0x1160
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
+ cmp.w #0x00a5, @word_dest
+ beq .Lwabs328
+ fail
+.Lwabs328:
+ mov.w #0xa5a5, @word_dest
+
+shlr_l_imm5_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #31:5, er0 ; shift right logical by 5-bit immediate
+;;; .word 0x0399
+;;; .word 0x1130
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0000 0000 0000 0000 0000 0000 0000 0001
+ test_h_gr32 0x1 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+shlr_l_reg32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l er0 ; shift right logical by one, register
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ test_h_gr32 0x52d2d2d2 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+shlr_l_ind_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l @er0 ; shift right logical by one, indirect
+;;; .word 0x0104
+;;; .word 0x6908
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llind1
+ fail
+.Llind1:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l @er0+ ; shift right logical by one, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpostinc1
+ fail
+.Llpostinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postdec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l @er0- ; shift right logical by one, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpostdec1
+ fail
+.Llpostdec1:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_preinc_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ shlr.l @+er0 ; shift right logical by one, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpreinc1
+ fail
+.Llpreinc1:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_predec_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ shlr.l @-er0 ; shift right logical by one, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llpredec1
+ fail
+.Llpredec1:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp2_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ shlr.l @(2:2, er0) ; shift right logical by one, disp2
+;;; .word 0x0106
+;;; .word 0x6908
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Lldisp21
+ fail
+.Lldisp21:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ shlr.l @(44:16, er0) ; shift right logical by one, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Lldisp161
+ fail
+.Lldisp161:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ shlr.l @(666:32, er0) ; shift right logical by one, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Lldisp321
+ fail
+.Lldisp321:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs16_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l @long_dest:16 ; shift right logical by one, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llabs161
+ fail
+.Llabs161:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs32_1:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l @long_dest:32 ; shift right logical by one, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x1130
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0101 0010 1101 0010 1101 0010 1101 0010
+ cmp.l #0x52d2d2d2, @long_dest
+ beq .Llabs321
+ fail
+.Llabs321:
+ mov #0xa5a5a5a5, @long_dest
+.endif
+
+shlr_l_reg32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #2, er0 ; shift right logical by two, register
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ test_h_gr32 0x29696969 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+
+shlr_l_ind_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #2, @er0 ; shift right logical by two, indirect
+;;; .word 0x0104
+;;; .word 0x6908
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Llind2
+ fail
+.Llind2:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #2, @er0+ ; shift right logical by two, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Llpostinc2
+ fail
+.Llpostinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postdec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #2, @er0- ; shift right logical by two, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Llpostdec2
+ fail
+.Llpostdec2:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_preinc_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ shlr.l #2, @+er0 ; shift right logical by two, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Llpreinc2
+ fail
+.Llpreinc2:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_predec_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ shlr.l #2, @-er0 ; shift right logical by two, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Llpredec2
+ fail
+.Llpredec2:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp2_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ shlr.l #2, @(2:2, er0) ; shift right logical by two, disp2
+;;; .word 0x0106
+;;; .word 0x6908
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Lldisp22
+ fail
+.Lldisp22:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Lldisp162
+ fail
+.Lldisp162:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Lldisp322
+ fail
+.Lldisp322:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs16_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #2, @long_dest:16 ; shift right logical by two, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Llabs162
+ fail
+.Llabs162:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs32_2:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #2, @long_dest:32 ; shift right logical by two, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x1170
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0010 1001 0110 1001 0110 1001 0110 1001
+ cmp.l #0x29696969, @long_dest
+ beq .Llabs322
+ fail
+.Llabs322:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_reg32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #4, er0 ; shift right logical by four, register
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ test_h_gr32 0x0a5a5a5a er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shlr_l_ind_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #4, @er0 ; shift right logical by four, indirect
+;;; .word 0x0104
+;;; .word 0x6908
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Llind4
+ fail
+.Llind4:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postinc_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #4, @er0+ ; shift right logical by four, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Llpostinc4
+ fail
+.Llpostinc4:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postdec_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #4, @er0- ; shift right logical by four, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Llpostdec4
+ fail
+.Llpostdec4:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_preinc_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ shlr.l #4, @+er0 ; shift right logical by four, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Llpreinc4
+ fail
+.Llpreinc4:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_predec_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ shlr.l #4, @-er0 ; shift right logical by four, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Llpredec4
+ fail
+.Llpredec4:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp2_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ shlr.l #4, @(2:2, er0) ; shift right logical by four, disp2
+;;; .word 0x0106
+;;; .word 0x6908
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Lldisp24
+ fail
+.Lldisp24:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Lldisp164
+ fail
+.Lldisp164:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Lldisp324
+ fail
+.Lldisp324:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs16_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #4, @long_dest:16 ; shift right logical by four, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Llabs164
+ fail
+.Llabs164:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs32_4:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #4, @long_dest:32 ; shift right logical by four, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x1138
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 1010 0101 1010 0101 1010 0101 1010
+ cmp.l #0x0a5a5a5a, @long_dest
+ beq .Llabs324
+ fail
+.Llabs324:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_reg32_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #8, er0 ; shift right logical by eight, register
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ test_h_gr32 0x00a5a5a5 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shlr_l_ind_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #8, @er0 ; shift right logical by eight, indirect
+;;; .word 0x0104
+;;; .word 0x6908
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Llind8
+ fail
+.Llind8:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postinc_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #8, @er0+ ; shift right logical by eight, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Llpostinc8
+ fail
+.Llpostinc8:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postdec_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #8, @er0- ; shift right logical by eight, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Llpostdec8
+ fail
+.Llpostdec8:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_preinc_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ shlr.l #8, @+er0 ; shift right logical by eight, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Llpreinc8
+ fail
+.Llpreinc8:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_predec_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ shlr.l #8, @-er0 ; shift right logical by eight, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Llpredec8
+ fail
+.Llpredec8:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp2_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ shlr.l #8, @(2:2, er0) ; shift right logical by eight, disp2
+;;; .word 0x0106
+;;; .word 0x6908
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Lldisp28
+ fail
+.Lldisp28:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp16_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Lldisp168
+ fail
+.Lldisp168:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp32_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Lldisp328
+ fail
+.Lldisp328:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs16_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Llabs168
+ fail
+.Llabs168:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs32_8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x1178
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 1010 0101 1010 0101 1010 0101
+ cmp.l #0x00a5a5a5, @long_dest
+ beq .Llabs328
+ fail
+.Llabs328:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_reg32_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #16, er0 ; shift right logical by sixteen, register
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ test_h_gr32 0x0000a5a5 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+shlr_l_ind_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #16, @er0 ; shift right logical by sixteen, indirect
+;;; .word 0x0104
+;;; .word 0x6908
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Llind16
+ fail
+.Llind16:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postinc_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #16, @er0+ ; shift right logical by sixteen, postinc
+;;; .word 0x0104
+;;; .word 0x6d08
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest+4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Llpostinc16
+ fail
+.Llpostinc16:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_postdec_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest, er0
+ shlr.l #16, @er0- ; shift right logical by sixteen, postdec
+;;; .word 0x0106
+;;; .word 0x6d08
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-4 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Llpostdec16
+ fail
+.Llpostdec16:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_preinc_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-4, er0
+ shlr.l #16, @+er0 ; shift right logical by sixteen, preinc
+;;; .word 0x0105
+;;; .word 0x6d08
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Llpreinc16
+ fail
+.Llpreinc16:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_predec_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest+4, er0
+ shlr.l #16, @-er0 ; shift right logical by sixteen, predec
+;;; .word 0x0107
+;;; .word 0x6d08
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Llpredec16
+ fail
+.Llpredec16:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp2_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-2, er0
+ shlr.l #16, @(2:2, er0) ; shift right logical by 16, dest2
+;;; .word 0x0106
+;;; .word 0x6908
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-2 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Lldisp216
+ fail
+.Lldisp216:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp16_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-44, er0
+ shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16
+;;; .word 0x0104
+;;; .word 0x6f08
+;;; .word 44
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-44 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Lldisp1616
+ fail
+.Lldisp1616:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_disp32_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #long_dest-666, er0
+ shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32
+;;; .word 0x7884
+;;; .word 0x6b28
+;;; .long 666
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr32 long_dest-666 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Lldisp3216
+ fail
+.Lldisp3216:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs16_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16
+;;; .word 0x0104
+;;; .word 0x6b08
+;;; .word long_dest
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Llabs1616
+ fail
+.Llabs1616:
+ mov #0xa5a5a5a5, @long_dest
+
+shlr_l_abs32_16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32
+;;; .word 0x0104
+;;; .word 0x6b28
+;;; .long long_dest
+;;; .word 0x11f8
+
+ test_carry_set ; H=0 N=0 Z=0 V=0 C=1
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ;; -> 0000 0000 0000 0000 1010 0101 1010 0101
+ cmp.l #0x0000a5a5, @long_dest
+ beq .Llabs3216
+ fail
+.Llabs3216:
+ mov #0xa5a5a5a5, @long_dest
+.endif
+.endif
+ pass
+
+ exit 0
+
--- /dev/null
+# Hitachi H8 testcase 'stc'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+ .data
+byte_dest1:
+ .byte 0
+byte_dest2:
+ .byte 0
+byte_dest3:
+ .byte 0
+byte_dest4:
+ .byte 0
+byte_dest5:
+ .byte 0
+byte_dest6:
+ .byte 0
+byte_dest7:
+ .byte 0
+byte_dest8:
+ .byte 0
+byte_dest9:
+ .byte 0
+byte_dest10:
+ .byte 0
+byte_dest11:
+ .byte 0
+byte_dest12:
+ .byte 0
+
+ start
+
+stc_ccr_reg8:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0xff, ccr ; test value
+ stc ccr, r0h ; copy test value to r0h
+
+ test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
+.if (sim_cpu) ; h/s/sx
+ test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
+stc_exr_reg8:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0x87, exr ; set exr to 0x87
+ stc exr, r0l ; retrieve and check exr value
+ cmp.b #0x87, r0l
+ beq .L21
+ fail
+.L21:
+ test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_ccr_abs16:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0xff, ccr
+ stc ccr, @byte_dest1:16 ; abs16 dest
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_exr_abs16:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0x87, exr
+ stc exr, @byte_dest2:16 ; abs16 dest
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_ccr_abs32:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0xff, ccr
+ stc ccr, @byte_dest3:32 ; abs32 dest
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_exr_abs32:
+ set_grs_a5a5
+ set_ccr_zero
+
+ ldc #0x87, exr
+ stc exr, @byte_dest4:32 ; abs32 dest
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_ccr_disp16:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest4, er1
+ ldc #0xff, ccr
+ stc ccr, @(1:16,er1) ; disp16 dest (5)
+
+ test_h_gr32 byte_dest4, er1 ; er1 still contains address
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_exr_disp16:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest7, er1
+ ldc #0x87, exr
+ stc exr, @(-1:16,er1) ; disp16 dest (6)
+
+ test_h_gr32 byte_dest7, er1 ; er1 still contains address
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_ccr_disp32:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest6, er1
+ ldc #0xff, ccr
+ stc ccr, @(1:32,er1) ; disp32 dest (7)
+
+ test_h_gr32 byte_dest6, er1 ; er1 still contains address
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_exr_disp32:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest9, er1
+ ldc #0x87, exr
+ stc exr, @(-1:32,er1) ; disp16 dest (8)
+
+ test_h_gr32 byte_dest9, er1 ; er1 still contains address
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_ccr_predecr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest10, er1
+ ldc #0xff, ccr
+ stc ccr, @-er1 ; predecr dest (9)
+
+ test_h_gr32 byte_dest9, er1 ; er1 still contains address
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_exr_predecr:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest11, er1
+ ldc #0x87, exr
+ stc exr, @-er1 ; predecr dest (10)
+
+ test_h_gr32 byte_dest10, er1 ; er1 still contains address
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_ccr_ind:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest11, er1
+ ldc #0xff, ccr
+ stc ccr, @er1 ; postinc dest (11)
+
+ test_h_gr32 byte_dest11, er1 ; er1 still contains address
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_exr_ind:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #byte_dest12, er1
+ ldc #0x87, exr
+ stc exr, @er1, exr ; postinc dest (12)
+
+ test_h_gr32 byte_dest12, er1 ; er1 still contains address
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
+stc_sbr_reg:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #0xaaaaaaaa, er0
+ ldc er0, sbr ; set sbr to 0xaaaaaaaa
+ stc sbr, er1 ; retreive and check sbr value
+
+ test_h_gr32 0xaaaaaaaa er1
+ test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+stc_vbr_reg:
+ set_grs_a5a5
+ set_ccr_zero
+
+ mov #0xaaaaaaaa, er0
+ ldc er0, vbr ; set sbr to 0xaaaaaaaa
+ stc vbr, er1 ; retreive and check sbr value
+
+ test_h_gr32 0xaaaaaaaa er1
+ test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+check_results:
+ ;; Now check results
+ mov @byte_dest1, r0h
+ cmp.b #0xff, r0h
+ beq .L1
+ fail
+
+.L1: mov @byte_dest2, r0h
+ cmp.b #0x87, r0h
+ beq .L2
+ fail
+
+.L2: mov @byte_dest3, r0h
+ cmp.b #0xff, r0h
+ beq .L3
+ fail
+
+.L3: mov @byte_dest4, r0h
+ cmp.b #0x87, r0h
+ beq .L4
+ fail
+
+.L4: mov @byte_dest5, r0h
+ cmp.b #0xff, r0h
+ beq .L5
+ fail
+
+.L5: mov @byte_dest6, r0h
+ cmp.b #0x87, r0h
+ beq .L6
+ fail
+
+.L6: mov @byte_dest7, r0h
+ cmp.b #0xff, r0h
+ beq .L7
+ fail
+
+.L7: mov @byte_dest8, r0h
+ cmp.b #0x87, r0h
+ beq .L8
+ fail
+
+.L8: mov @byte_dest9, r0h
+ cmp.b #0xff, r0h
+ beq .L9
+ fail
+
+.L9: mov @byte_dest10, r0h
+ cmp.b #0x87, r0h
+ beq .L10
+ fail
+
+.L10: mov @byte_dest11, r0h
+ cmp.b #0xff, r0h
+ beq .L11
+ fail
+
+.L11: mov @byte_dest12, r0h
+ cmp.b #0x87, r0h
+ beq .L12
+ fail
+
+.L12:
+.endif
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'sub.b'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # sub.b #xx:8, rd ; <illegal>
+ # sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
+ # sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
+ # sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
+ # sub.b rs, rd ; 1 8 rs rd
+ # sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ????
+ # sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs
+ # sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs
+ #
+
+ # Coming soon:
+ # sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
+ # sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
+ # sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs
+ # sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs
+ # ...
+
+.data
+pre_byte: .byte 0
+byte_dest: .byte 0xa5
+post_byte: .byte 0
+
+ start
+
+.if (0) ; Guess what? Sub.b immediate reg8 is illegal!
+sub_b_imm8_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.b #xx:8,Rd
+ sub.b #5, r0l ; Immediate 8-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu == h8sx)
+sub_b_imm8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; sub.b #xx:8,@eRd
+ mov #byte_dest, er0
+ sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x7d00
+;;; .word 0xa105
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest, er0 ; er0 still contains address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the sub to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa0, r0l
+ beq .L1
+ fail
+.L1:
+
+sub_b_imm8_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; sub.b #xx:8,@eRd+
+ mov #byte_dest, er0
+ sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0xa105
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 post_byte, er0 ; er0 still contains address plus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the sub to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x9b, r0l
+ beq .L2
+ fail
+.L2:
+
+sub_b_imm8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; sub.b #xx:8,@eRd-
+ mov #byte_dest, er0
+ sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0xa105
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 pre_byte, er0 ; er0 still contains address minus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the sub to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x96, r0l
+ beq .L3
+ fail
+.L3:
+
+.endif
+
+sub_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.b Rs,Rd
+ mov.b #5, r0h
+ sub.b r0h, r0l ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0x05a0 r0 ; sub result: a5 - 5
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+sub_b_reg8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; sub.b rs8,@eRd ; Subx to register indirect
+ mov #byte_dest, er0
+ mov #5, r1l
+ sub.b r1l, @er0 ; reg8 src, reg indirect dest
+;;; .word 0x7d00
+;;; .word 0x1890
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the sub to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x91, r0l
+ beq .L4
+ fail
+.L4:
+
+sub_b_reg8_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; sub.b rs8,@eRd+ ; Subx to register indirect
+ mov #byte_dest, er0
+ mov #5, r1l
+ sub.b r1l, @er0+ ; reg8 src, reg indirect dest
+;;; .word 0x0179
+;;; .word 0x8039
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 post_byte er0 ; er0 still contains address plus one
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the sub to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x8c, r0l
+ beq .L5
+ fail
+.L5:
+
+sub_b_reg8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; sub.b rs8,@eRd- ; Subx to register indirect
+ mov #byte_dest, er0
+ mov #5, r1l
+ sub.b r1l, @er0- ; reg8 src, reg indirect dest
+;;; .word 0x0179
+;;; .word 0xa039
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 pre_byte er0 ; er0 still contains address minus one
+ test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the sub to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x87, r0l
+ beq .L6
+ fail
+.L6:
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'sub.l'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu == h8sx) ;
+sub_l_imm3: ; 3-bit immediate mode only for h8sx
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.l #xx:3,eRd ; Immediate 3-bit operand
+ sub.l #7:3, er0
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+sub_l_imm16: ; sub immediate 16-bit value
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.l #xx:16,eRd ; Immediate 16-bit operand
+ sub.l #0x1111:16, er0
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111
+ test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+sub_l_imm32:
+ ;; sub.l immediate not available in h8300 mode.
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.l #xx:32,Rd
+ sub.l #0x11111111, er0 ; Immediate 32-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+sub.l.reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; add.l Rs,Rd
+ mov.l #0x11111111, er1
+ sub.l er1, er0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
+ test_h_gr32 0x11111111 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'sub.w'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
+sub_w_imm3: ; sub.w immediate not available in h8300 mode.
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.w #xx:3,Rd ; Immediate 3-bit operand
+ sub.w #7:3, r0
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7
+ test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+sub_w_imm16: ; sub.w immediate not available in h8300 mode.
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.w #xx:16,Rd
+ sub.w #0x111, r0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
+ test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+sub.w.reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; sub.w Rs,Rd
+ mov.w #0x111, r1
+ sub.w r1, r0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
+ test_h_gr16 0x0111 r1
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
+ test_h_gr32 0xa5a50111 er1
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Support macros for the Hitachi H8 assembly test cases.
+
+; Set up a minimal machine state
+ .macro start
+ .equ h8300, 0
+ .equ h8300h, 1
+ .equ h8300s, 2
+ .equ h8sx, 3
+ .if (sim_cpu == h8300s)
+ .h8300s
+ .else
+ .if (sim_cpu == h8300h)
+ .h8300h
+ .else
+ .if (sim_cpu == h8sx)
+ .h8300sx
+ .endif
+ .endif
+ .endif
+
+ .text
+ .align 2
+ .global _start
+_start:
+ jmp _main
+
+ .data
+ .align 2
+ .global pass_str
+ .global fail_str
+ .global ok_str
+ .global pass_loc
+ .global fail_loc
+ .global ok_loc
+pass_str:
+ .ascii "pass\n"
+fail_str:
+ .ascii "fail\n"
+ok_str:
+ .ascii "ok\n"
+pass_loc16:
+ .word pass_str
+pass_loc32:
+ .long pass_str
+fail_loc16:
+ .word fail_str
+fail_loc32:
+ .long fail_str
+ok_loc16:
+ .word ok_str
+ok_loc32:
+ .long ok_str
+ .text
+
+ .global _write_and_exit
+_write_and_exit:
+;ssize_t write(int fd, const void *buf, size_t count);
+;Integer arguments have to be zero extended.
+.if (sim_cpu)
+#if __INT_MAX__ == 32767
+ extu.l er0
+#endif
+.endif
+ jsr @@0xc7
+ mov #0, r0
+ jmp _exit
+
+ .global _exit
+_exit:
+ mov.b r0l, r0h
+ mov.w #0xdead, r1
+ mov.w #0xbeef, r2
+ sleep
+
+ .global _main
+_main:
+ .endm
+
+
+; Exit with an exit code
+ .macro exit code
+ mov.w #\code, r0
+ jmp _exit
+ .endm
+
+; Output "pass\n"
+ .macro pass
+ mov.w #0, r0 ; fd == stdout
+.if (sim_cpu == h8300)
+ mov.w #pass_str, r1 ; buf == "pass\n"
+ mov.w #5, r2 ; len == 5
+.else
+ mov.l #pass_str, er1 ; buf == "pass\n"
+ mov.l #5, er2 ; len == 5
+.endif
+ jmp _write_and_exit
+ .endm
+
+; Output "fail\n"
+ .macro fail
+ mov.w #0, r0 ; fd == stdout
+.if (sim_cpu == h8300)
+ mov.w #fail_str, r1 ; buf == "fail\n"
+ mov.w #5, r2 ; len == 5
+.else
+ mov.l #fail_str, er1 ; buf == "fail\n"
+ mov.l #5, er2 ; len == 5
+.endif
+ jmp _write_and_exit
+ .endm
+
+
+; Load an 8-bit immediate value into a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro mvi_h_gr8 val reg
+ mov.b #\val, \reg
+ .endm
+
+; Load a 16-bit immediate value into a general register
+; (reg must be r0 - r7)
+ .macro mvi_h_gr16 val reg
+ mov.w #\val, \reg
+ .endm
+
+; Load a 32-bit immediate value into a general register
+; (reg must be er0 - er7)
+ .macro mvi_h_gr32 val reg
+ mov.l #\val, \reg
+ .endm
+
+; Test the value of an 8-bit immediate against a general register
+; (reg must be r0l - r7l or r0h - r7h)
+ .macro test_h_gr8 val reg
+ cmp.b #\val, \reg
+ beq .Ltest_gr8\@
+ fail
+.Ltest_gr8\@:
+ .endm
+
+; Test the value of a 16-bit immediate against a general register
+; (reg must be r0 - r7)
+ .macro test_h_gr16 val reg h=h l=l
+ .if (sim_cpu == h8300)
+ test_h_gr8 (\val >> 8) \reg\h
+ test_h_gr8 (\val & 0xff) \reg\l
+ .else
+ cmp.w #\val, \reg
+ beq .Ltest_gr16\@
+ fail
+.Ltest_gr16\@:
+ .endif
+ .endm
+
+; Test the value of a 32-bit immediate against a general register
+; (reg must be er0 - er7)
+ .macro test_h_gr32 val reg
+ cmp.l #\val, \reg
+ beq .Ltest_gr32\@
+ fail
+.Ltest_gr32\@:
+ .endm
+
+; Set a general register to the fixed pattern 'a5a5a5a5'
+ .macro set_gr_a5a5 reg
+ .if (sim_cpu == 0)
+ ; h8300
+ mov.w #0xa5a5, r\reg
+ .else
+ mov.l #0xa5a5a5a5, er\reg
+ .endif
+ .endm
+
+; Set all general registers to the fixed pattern 'a5a5a5a5'
+ .macro set_grs_a5a5
+ .if (sim_cpu == 0)
+ ; h8300
+ mov.w #0xa5a5, r0
+ mov.w #0xa5a5, r1
+ mov.w #0xa5a5, r2
+ mov.w #0xa5a5, r3
+ mov.w #0xa5a5, r4
+ mov.w #0xa5a5, r5
+ mov.w #0xa5a5, r6
+ mov.w #0xa5a5, r7
+ .else
+ mov.l #0xa5a5a5a5, er0
+ mov.l #0xa5a5a5a5, er1
+ mov.l #0xa5a5a5a5, er2
+ mov.l #0xa5a5a5a5, er3
+ mov.l #0xa5a5a5a5, er4
+ mov.l #0xa5a5a5a5, er5
+ mov.l #0xa5a5a5a5, er6
+ mov.l #0xa5a5a5a5, er7
+ .endif
+ .endm
+
+; Test that a general register contains the fixed pattern 'a5a5a5a5'
+ .macro test_gr_a5a5 reg
+ .if (sim_cpu == 0)
+ ; h8300
+ test_h_gr16 0xa5a5 r\reg
+ .else
+ test_h_gr32 0xa5a5a5a5 er\reg
+ .endif
+ .endm
+
+; Test that all general regs contain the fixed pattern 'a5a5a5a5'
+ .macro test_grs_a5a5
+ test_gr_a5a5 0
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+ .endm
+
+; Set condition code register to an explicit value
+ .macro set_ccr val
+ ldc #\val, ccr
+ .endm
+
+; Set all condition code flags to zero
+ .macro set_ccr_zero
+ ldc #0, ccr
+ .endm
+
+; Set carry flag to value
+ .macro set_carry_flag val
+ .data
+scf\@: .byte 0
+ .text
+ mov.b r0l, @scf\@
+ mov.b #\val:8, r0l
+ or.b r0l, r0l
+ beq .Lccf\@ ; clear
+ stc ccr, r0l ; set
+ or.b #0x1, r0l
+ jmp .Lecf\@
+.Lccf\@: ; clear
+ stc ccr, r0l
+ and.b #0xfe, r0l
+.Lecf\@:
+ ldc r0l, ccr
+ mov @scf\@, r0l
+ .endm
+
+; Test that carry flag is clear
+ .macro test_carry_clear
+ bcc .Lcc\@
+ fail ; carry flag not clear
+.Lcc\@:
+ .endm
+
+; Test that carry flag is set
+ .macro test_carry_set
+ bcs .Lcs\@
+ fail ; carry flag not clear
+.Lcs\@:
+ .endm
+
+; Test that overflow flag is clear
+ .macro test_ovf_clear
+ bvc .Lvc\@
+ fail ; overflow flag not clear
+.Lvc\@:
+ .endm
+
+; Test that overflow flag is set
+ .macro test_ovf_set
+ bvs .Lvs\@
+ fail ; overflow flag not clear
+.Lvs\@:
+ .endm
+
+; Test that zero flag is clear
+ .macro test_zero_clear
+ bne .Lne\@
+ fail ; zero flag not clear
+.Lne\@:
+ .endm
+
+; Test that zero flag is set
+ .macro test_zero_set
+ beq .Leq\@
+ fail ; zero flag not clear
+.Leq\@:
+ .endm
+
+; Test that neg flag is clear
+ .macro test_neg_clear
+ bpl .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test that neg flag is set
+ .macro test_neg_set
+ bmi .Lneg\@
+ fail ; negative flag not clear
+.Lneg\@:
+ .endm
+
+; Test ccr against an explicit value
+ .macro test_ccr val
+ .data
+tccr\@: .byte 0
+ .text
+ mov.b r0l, @tccr\@
+ stc ccr, r0l
+ cmp.b #\val, r0l
+ bne .Ltcc\@
+ fail
+.Ltcc\@:
+ mov.b @tccr\@, r0l
+ .endm
+
+; Test that all (accessable) condition codes are clear
+ .macro test_cc_clear
+ test_carry_clear
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+ ; leaves H, I, U, and UI untested
+ .endm
+
+; Compare memory, fail if not equal (h8sx only, len > 0).
+ .macro memcmp src dst len
+ mov.l #\src, er5
+ mov.l #\dst, er6
+ mov.l #\len, er4
+.Lmemcmp_\@:
+ cmp.b @er5+, @er6+
+ beq .Lmemcmp2_\@
+ fail
+.Lmemcmp2_\@:
+ dec.l #1, er4
+ bne .Lmemcmp_\@
+ .endm
+
--- /dev/null
+# Hitachi H8 testcase 'xor.b'
+# mach(): all
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ # Instructions tested:
+ # xor.b #xx:8, rd ; d rd xxxxxxxx
+ # xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx
+ # xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx
+ # xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx
+ # xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx
+ # xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx
+ # xor.b rs, rd ; 1 5 rs rd
+ # xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ????
+ # xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs
+ # xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs
+ # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs
+ # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs
+ #
+
+ # Coming soon:
+ # ...
+
+.data
+pre_byte: .byte 0
+byte_dest: .byte 0xa5
+post_byte: .byte 0
+
+ start
+
+xor_b_imm8_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; xor.b #xx:8,Rd
+ xor.b #0xff, r0l ; Immediate 8-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+xor_b_imm8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; xor.b #xx:8,@eRd
+ mov #byte_dest, er0
+ xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x7d00
+;;; .word 0xd0ff
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 byte_dest, er0 ; er0 still contains address
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the xor to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x5a, r0l
+ beq .L1
+ fail
+.L1:
+
+xor_b_imm8_postinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; xor.b #xx:8,@eRd+
+ mov #byte_dest, er0
+ xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x0174
+;;; .word 0x6c08
+;;; .word 0xd0ff
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 post_byte, er0 ; er0 contains address plus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the xor to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L2
+ fail
+.L2:
+
+xor_b_imm8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; xor.b #xx:8,@eRd-
+ mov #byte_dest, er0
+ xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst
+;;; .word 0x0176
+;;; .word 0x6c08
+;;; .word 0xd0ff
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 pre_byte, er0 ; er0 contains address minus one
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the xor to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x5a, r0l
+ beq .L3
+ fail
+.L3:
+
+
+.endif
+
+xor_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; xor.b Rs,Rd
+ mov.b #0xff, r0h
+ xor.b r0h, r0l ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.if (sim_cpu == h8sx)
+xor_b_reg8_rdind:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; xor.b rs8,@eRd ; xor reg8 to register indirect
+ mov #byte_dest, er0
+ mov #0xff, r1l
+ xor.b r1l, @er0 ; reg8 src, reg indirect dest
+;;; .word 0x7d00
+;;; .word 0x1590
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 byte_dest er0 ; er0 still contains address
+ test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L4
+ fail
+.L4:
+
+xor_b_reg8_rdpostinc:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment
+ mov #byte_dest, er0
+ mov #0xff, r1l
+ xor.b r1l, @er0+ ; reg8 src, reg post-increment dest
+;;; .word 0x0179
+;;; .word 0x8059
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_clear
+
+ test_h_gr32 post_byte er0 ; er0 contains address plus one
+ test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0x5a, r0l
+ beq .L5
+ fail
+.L5:
+
+xor_b_reg8_rdpostdec:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement
+ mov #byte_dest, er0
+ mov #0xff, r1l
+ xor.b r1l, @er0- ; reg8 src, reg indirect dest
+;;; .word 0x0179
+;;; .word 0xa059
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_ovf_clear
+ test_zero_clear
+ test_neg_set
+
+ test_h_gr32 pre_byte er0 ; er0 contains address minus one
+ test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ ;; Now check the result of the or to memory.
+ sub.b r0l, r0l
+ mov.b @byte_dest, r0l
+ cmp.b #0xa5, r0l
+ beq .L6
+ fail
+.L6:
+
+xorc_imm8_ccr:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ ;; xorc #xx:8,ccr
+
+ test_neg_clear
+ xorc #0x8, ccr ; Immediate 8-bit operand (neg flag)
+ test_neg_set
+ xorc #0x8, ccr
+ test_neg_clear
+
+ test_zero_clear
+ xorc #0x4, ccr ; Immediate 8-bit operand (zero flag)
+ test_zero_set
+ xorc #0x4, ccr
+ test_zero_clear
+
+ test_ovf_clear
+ xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
+ test_ovf_set
+ xorc #0x2, ccr
+ test_ovf_clear
+
+ test_carry_clear
+ xorc #0x1, ccr ; Immediate 8-bit operand (carry flag)
+ test_carry_set
+ xorc #0x1, ccr
+ test_carry_clear
+
+ test_gr_a5a5 0 ; Make sure other general regs not disturbed
+ test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+.endif
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'xor.l'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
+xor_l_imm16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; xor.l #xx:16,Rd
+ xor.l #0xffff:16, er0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+xor_l_imm32:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; xor.l #xx:32,Rd
+ xor.l #0xffffffff, er0 ; Immediate 32-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+xor_l_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; xor.l Rs,Rd
+ mov.l #0xffffffff, er1
+ xor.l er1, er0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+
+ test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
+ test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
--- /dev/null
+# Hitachi H8 testcase 'xor.w'
+# mach(): h8300h h8300s h8sx
+# as(h8300): --defsym sim_cpu=0
+# as(h8300h): --defsym sim_cpu=1
+# as(h8300s): --defsym sim_cpu=2
+# as(h8sx): --defsym sim_cpu=3
+# ld(h8300h): -m h8300helf
+# ld(h8300s): -m h8300self
+# ld(h8sx): -m h8300sxelf
+
+ .include "testutils.inc"
+
+ start
+
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+xor_w_imm16:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; xor.w #xx:16,Rd
+ xor.w #0xffff, r0 ; Immediate 16-bit operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
+.endif
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+.endif
+
+xor_w_reg:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ ;; fixme set ccr
+
+ ;; xor.w Rs,Rd
+ mov.w #0xffff, r1
+ xor.w r1, r0 ; Register operand
+
+ ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
+ test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
+ test_h_gr16 0xffff r1 ; Make sure r1 is unchanged
+.if (sim_cpu) ; non-zero means h8300h, s, or sx
+ test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
+ test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged
+.endif
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ pass
+
+ exit 0
2003-04-06 Nick Clifton <nickc@redhat.com>
- * simops.c (OP_40): Delete. Move code to:
- * v850-igen.c (): Here. Sign extend the first operand.
+ * simops.c (OP_40): Delete. Move code to...
+ * v850-igen.c (): ...Here. Sign extend the first operand.
* simops.h (OP_40): Remove prototype.
2003-02-27 Andrew Cagney <cagney@redhat.com>
projects / external / binutils.git / commitdiff