#include <asm/mach-types.h>
#include <asm/mach/arch.h>
- #include <plat/omap7xx.h>
- #include <plat/board.h>
+ #include <mach/omap7xx.h>
#include <plat/keypad.h>
#include <plat/mmc.h>
break;
}
if (!tries)
- printk(KERN_WARNING "Timeout waiting for end of frame "
- "-- LCD may not be available\n");
+ pr_err("Timeout waiting for end of frame -- LCD may not be available\n");
/* turn off DMA */
reg = omap_readw(OMAP_DMA_LCD_CCR);
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/clkdev_omap.h>
- #include <plat/board.h>
#include <plat/sram.h> /* for omap_sram_reprogram_clock() */
#include <mach/hardware.h>
static void __init omap1_show_rates(void)
{
- pr_notice("Clocking rate (xtal/DPLL1/MPU): "
- "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
- ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
- ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
- arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+ pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+ ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+ ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+ arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
}
u32 cpu_mask;
int __init omap1_clk_init(void)
{
struct omap_clk *c;
- const struct omap_clock_config *info;
int crystal_type = 0; /* Default 12 MHz */
u32 reg;
ck_dpll1_p = clk_get(NULL, "ck_dpll1");
ck_ref_p = clk_get(NULL, "ck_ref");
- info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
- if (info != NULL) {
- if (!cpu_is_omap15xx())
- crystal_type = info->system_clock_type;
- }
-
if (cpu_is_omap7xx())
ck_ref.rate = 13000000;
if (cpu_is_omap16xx() && crystal_type == 2)
ck_ref.rate = 19200000;
- pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
- "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+ pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
+ omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
omap_readw(ARM_CKCTL));
/* We want to be in syncronous scalable mode */
#include <plat/dma.h>
#include <plat/tc.h>
- #include <plat/irqs.h>
+
+ #include <mach/irqs.h>
#define OMAP1_DMA_BASE (0xfffed800)
#define OMAP1_LOGICAL_DMA_CH_COUNT 17
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
(d->lch_count), GFP_KERNEL);
if (!d->chan) {
- dev_err(&pdev->dev, "%s: Memory allocation failed"
- "for d->chan!!!\n", __func__);
+ dev_err(&pdev->dev,
+ "%s: Memory allocation failed for d->chan!\n",
+ __func__);
goto exit_release_d;
}
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/io.h>
+ #include <linux/platform_data/gpio-omap.h>
#include <mach/hardware.h>
#include <asm/leds.h>
gpio_set_value(GPIO_IDLE, 0);
}
- __raw_writew(~0, &fpga->leds);
led_state &= ~LED_STATE_ENABLED;
- if (evt == led_halted) {
- iounmap(fpga);
- fpga = NULL;
+ if (fpga) {
+ __raw_writew(~0, &fpga->leds);
+ if (evt == led_halted) {
+ iounmap(fpga);
+ fpga = NULL;
+ }
}
goto done;
/*
* Actually burn the LEDs
*/
- if (led_state & LED_STATE_ENABLED)
+ if (led_state & LED_STATE_ENABLED && fpga)
__raw_writew(~hw_led_state, &fpga->leds);
done:
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
- #include <plat/board.h>
#include "common.h"
#include <plat/menelaus.h>
- #include <mach/irqs.h>
#include <plat/mcspi.h>
#include <plat/onenand.h>
#include <plat/mmc.h>
- #include <plat/serial.h>
#include "mux.h"
ret = menelaus_set_regulator_sleep(1, val);
if (ret < 0) {
- printk(KERN_ERR "Could not set regulators to sleep on "
- "menelaus: %u\n", ret);
+ pr_err("Could not set regulators to sleep on menelaus: %u\n",
+ ret);
return ret;
}
return 0;
ret = menelaus_set_vcore_hw(1400, 1050);
if (ret < 0) {
- printk(KERN_ERR "Could not set VCORE voltage on "
- "menelaus: %u\n", ret);
+ pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
return ret;
}
return 0;
static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
{
I2C_BOARD_INFO("menelaus", 0x72),
- .irq = INT_24XX_SYS_NIRQ,
+ .irq = 7 + OMAP_INTC_START,
.platform_data = &n8x0_menelaus_platform_data,
},
};
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
- #include <plat/board.h>
#include "common.h"
#include <video/omapdss.h>
#include <video/omap-panel-generic-dpi.h>
#include <video/omap-panel-tfp410.h>
#include <plat/gpmc.h>
- #include <mach/hardware.h>
#include <plat/nand.h>
#include <plat/mcspi.h>
- #include <plat/mux.h>
#include <plat/usb.h>
#include "mux.h"
}
static struct twl4030_gpio_platform_data overo_gpio_data = {
- .gpio_base = OMAP_MAX_GPIO_LINES,
- .irq_base = TWL4030_GPIO_IRQ_BASE,
- .irq_end = TWL4030_GPIO_IRQ_END,
.use_leds = true,
.setup = overo_twl_gpio_setup,
};
udelay(10);
gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
} else {
- printk(KERN_ERR "could not obtain gpio for "
- "OVERO_GPIO_W2W_NRESET\n");
+ pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
}
ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
if (ret == 0)
gpio_export(OVERO_GPIO_USBH_CPEN, 0);
else
- printk(KERN_ERR "could not obtain gpio for "
- "OVERO_GPIO_USBH_CPEN\n");
+ pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
}
MACHINE_START(OVERO, "Gumstix Overo")
#include <mach/board-zoom.h>
+ #include "soc.h"
+ #include "common.h"
+
#define ZOOM_SMSC911X_CS 7
#define ZOOM_SMSC911X_GPIO 158
#define ZOOM_QUADUART_CS 3
quart_cs = ZOOM_QUADUART_CS;
if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
- printk(KERN_ERR "Failed to request GPMC mem"
- "for Quad UART(TL16CP754C)\n");
+ pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
return;
}
if (gpio_request_one(debug_board_detect, GPIOF_IN,
"Zoom debug board detect") < 0) {
- printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
- "board detect\n", debug_board_detect);
+ pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
+ debug_board_detect);
return 0;
}
#include <asm/div64.h>
#include <plat/clock.h>
- #include <plat/cpu.h>
+ #include "soc.h"
#include "clock.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
}
if (fint < fint_min) {
- pr_debug("rejecting n=%d due to Fint failure, "
- "lowering max_divider\n", n);
+ pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
+ n);
dd->max_divider = n;
ret = DPLL_FINT_UNDERFLOW;
} else if (fint > fint_max) {
- pr_debug("rejecting n=%d due to Fint failure, "
- "boosting min_divider\n", n);
+ pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
+ n);
dd->min_divider = n;
ret = DPLL_FINT_INVALID;
} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
- #include <trace/events/power.h>
#include <asm/cpu.h>
+
#include <plat/clock.h>
- #include "clockdomain.h"
- #include <plat/cpu.h>
#include <plat/prcm.h>
+ #include <trace/events/power.h>
+
+ #include "soc.h"
+ #include "clockdomain.h"
#include "clock.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
clk->name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
- pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm_name);
+ pr_debug("clock: could not associate clk %s to clkdm %s\n",
+ clk->name, clk->clkdm_name);
}
}
* 'Independent' here refers to a clock which is not
* controlled by its parent.
*/
- printk(KERN_ERR "clock: clk_disable called on independent "
- "clock %s which has no enable_reg\n", clk->name);
+ pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
return;
}
void omap2_clk_disable(struct clk *clk)
{
if (clk->usecount == 0) {
- WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
- "already 0?", clk->name);
+ WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
return;
}
if (clkdm_control && clk->clkdm) {
ret = clkdm_clk_enable(clk->clkdm, clk);
if (ret) {
- WARN(1, "clock: %s: could not enable clockdomain %s: "
- "%d\n", clk->name, clk->clkdm->name, ret);
+ WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
+ clk->name, clk->clkdm->name, ret);
goto oce_err2;
}
}
hfclkin_rate = clk_get_rate(hfclkin_ck);
- pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (hfclkin_rate / 1000000),
- ((hfclkin_rate / 100000) % 10),
+ pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
(clk_get_rate(core_ck) / 1000000),
(clk_get_rate(mpu_ck) / 1000000));
}
#include <linux/list.h>
#include <linux/clk.h>
#include <plat/clkdev_omap.h>
- #include <plat/am33xx.h>
+ #include "am33xx.h"
#include "iomap.h"
#include "control.h"
#include "clock.h"
CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
- CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX),
- CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX),
- CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX),
- CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX),
- CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX),
- CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX),
- CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX),
+ CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
+ CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
+ CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
+ CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
+ CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
+ CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
+ CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
#include <linux/clk.h>
#include <linux/io.h>
- #include <plat/hardware.h>
#include <plat/clock.h>
+ #include "soc.h"
#include "clock.h"
#include "clock3xxx.h"
#include "prm2xxx_3xxx.h"
* on DPLL4.
*/
if (omap_rev() == OMAP3430_REV_ES1_0) {
- pr_err("clock: DPLL4 cannot change rate due to "
- "silicon 'Limitation 2.5' on 3430ES1.\n");
+ pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
return -EINVAL;
}
#include <plat/mcspi.h>
#include <plat/nand.h>
+ #include "common.h"
#include "common-board-devices.h"
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
}
if (nandcs > GPMC_CS_NUM) {
- printk(KERN_INFO "NAND: Unable to find configuration "
- "in GPMC\n ");
+ pr_info("NAND: Unable to find configuration in GPMC\n");
return;
}
#include <linux/bitops.h>
#include <linux/clkdev.h>
- #include <plat/cpu.h>
#include <plat/clock.h>
+ #include "soc.h"
#include "clock.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
while (pclk && !pclk->dpll_data)
pclk = pclk->parent;
- /* clk does not have a DPLL as a parent? */
- WARN_ON(!pclk);
+ /* clk does not have a DPLL as a parent? error in the clock data */
+ if (!pclk) {
+ WARN_ON(1);
+ return 0;
+ }
dd = pclk->dpll_data;
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/of.h>
+ #include <linux/platform_data/gpio-omap.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
if (!pdata->regs) {
pr_err("gpio%d: Memory allocation failed\n", id);
+ kfree(pdata);
return -ENOMEM;
}
#include <asm/mach-types.h>
#include <plat/gpmc.h>
+ #include <plat/cpu.h>
+ #include <plat/gpmc.h>
#include <plat/sdrc.h>
+ #include "soc.h"
+ #include "common.h"
+
/* GPMC register offsets */
#define GPMC_REVISION 0x00
#define GPMC_SYSCONFIG 0x10
#define ENABLE_PREFETCH (0x1 << 7)
#define DMA_MPU_MODE 2
+ /* XXX: Only NAND irq has been considered,currently these are the only ones used
+ */
+ #define GPMC_NR_IRQ 2
+
+ struct gpmc_client_irq {
+ unsigned irq;
+ u32 bitmask;
+ };
+
/* Structure to save gpmc cs context */
struct gpmc_cs_config {
u32 config1;
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};
+ static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
+ static struct irq_chip gpmc_irq_chip;
+ static unsigned gpmc_irq_start;
+
static struct resource gpmc_mem_root;
static struct resource gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
div = gpmc_cs_calc_divider(cs, t->sync_clk);
if (div < 0)
- return -1;
+ return div;
GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
}
EXPORT_SYMBOL(gpmc_prefetch_reset);
+ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
+ {
+ reg->gpmc_status = gpmc_base + GPMC_STATUS;
+ reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
+ GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
+ reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
+ GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
+ reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
+ GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
+ reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
+ reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
+ reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
+ reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
+ reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
+ reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
+ reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
+ reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
+ reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
+ }
+
+ int gpmc_get_client_irq(unsigned irq_config)
+ {
+ int i;
+
+ if (hweight32(irq_config) > 1)
+ return 0;
+
+ for (i = 0; i < GPMC_NR_IRQ; i++)
+ if (gpmc_client_irq[i].bitmask & irq_config)
+ return gpmc_client_irq[i].irq;
+
+ return 0;
+ }
+
+ static int gpmc_irq_endis(unsigned irq, bool endis)
+ {
+ int i;
+ u32 regval;
+
+ for (i = 0; i < GPMC_NR_IRQ; i++)
+ if (irq == gpmc_client_irq[i].irq) {
+ regval = gpmc_read_reg(GPMC_IRQENABLE);
+ if (endis)
+ regval |= gpmc_client_irq[i].bitmask;
+ else
+ regval &= ~gpmc_client_irq[i].bitmask;
+ gpmc_write_reg(GPMC_IRQENABLE, regval);
+ break;
+ }
+
+ return 0;
+ }
+
+ static void gpmc_irq_disable(struct irq_data *p)
+ {
+ gpmc_irq_endis(p->irq, false);
+ }
+
+ static void gpmc_irq_enable(struct irq_data *p)
+ {
+ gpmc_irq_endis(p->irq, true);
+ }
+
+ static void gpmc_irq_noop(struct irq_data *data) { }
+
+ static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
+
+ static int gpmc_setup_irq(int gpmc_irq)
+ {
+ int i;
+ u32 regval;
+
+ if (!gpmc_irq)
+ return -EINVAL;
+
+ gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
+ if (IS_ERR_VALUE(gpmc_irq_start)) {
+ pr_err("irq_alloc_descs failed\n");
+ return gpmc_irq_start;
+ }
+
+ gpmc_irq_chip.name = "gpmc";
+ gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
+ gpmc_irq_chip.irq_enable = gpmc_irq_enable;
+ gpmc_irq_chip.irq_disable = gpmc_irq_disable;
+ gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
+ gpmc_irq_chip.irq_ack = gpmc_irq_noop;
+ gpmc_irq_chip.irq_mask = gpmc_irq_noop;
+ gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
+
+ gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
+ gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
+
+ for (i = 0; i < GPMC_NR_IRQ; i++) {
+ gpmc_client_irq[i].irq = gpmc_irq_start + i;
+ irq_set_chip_and_handler(gpmc_client_irq[i].irq,
+ &gpmc_irq_chip, handle_simple_irq);
+ set_irq_flags(gpmc_client_irq[i].irq,
+ IRQF_VALID | IRQF_NOAUTOEN);
+ }
+
+ /* Disable interrupts */
+ gpmc_write_reg(GPMC_IRQENABLE, 0);
+
+ /* clear interrupts */
+ regval = gpmc_read_reg(GPMC_IRQSTATUS);
+ gpmc_write_reg(GPMC_IRQSTATUS, regval);
+
+ return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
+ }
+
static void __init gpmc_mem_init(void)
{
int cs;
static int __init gpmc_init(void)
{
- u32 l, irq;
- int cs, ret = -EINVAL;
+ u32 l;
+ int ret = -EINVAL;
int gpmc_irq;
char *ck = NULL;
l = OMAP2420_GPMC_BASE;
else
l = OMAP34XX_GPMC_BASE;
- gpmc_irq = INT_34XX_GPMC_IRQ;
+ gpmc_irq = 20 + OMAP_INTC_START;
} else if (cpu_is_omap34xx()) {
ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE;
- gpmc_irq = INT_34XX_GPMC_IRQ;
+ gpmc_irq = 20 + OMAP_INTC_START;
} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
/* Base address and irq number are same for OMAP4/5 */
ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE;
- gpmc_irq = OMAP44XX_IRQ_GPMC;
+ gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START;
}
if (WARN_ON(!ck))
gpmc_write_reg(GPMC_SYSCONFIG, l);
gpmc_mem_init();
- /* initalize the irq_chained */
- irq = OMAP_GPMC_IRQ_BASE;
- for (cs = 0; cs < GPMC_CS_NUM; cs++) {
- irq_set_chip_and_handler(irq, &dummy_irq_chip,
- handle_simple_irq);
- set_irq_flags(irq, IRQF_VALID);
- irq++;
- }
-
- ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
+ ret = gpmc_setup_irq(gpmc_irq);
if (ret)
pr_err("gpmc: irq-%d could not claim: err %d\n",
gpmc_irq, ret);
static irqreturn_t gpmc_handle_irq(int irq, void *dev)
{
- u8 cs;
+ int i;
+ u32 regval;
+
+ regval = gpmc_read_reg(GPMC_IRQSTATUS);
+
+ if (!regval)
+ return IRQ_NONE;
+
+ for (i = 0; i < GPMC_NR_IRQ; i++)
+ if (regval & gpmc_client_irq[i].bitmask)
+ generic_handle_irq(gpmc_client_irq[i].irq);
- /* check cs to invoke the irq */
- cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
- if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
- generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+ gpmc_write_reg(GPMC_IRQSTATUS, regval);
return IRQ_HANDLED;
}
#include <asm/cputype.h>
#include "common.h"
- #include <plat/cpu.h>
#include <mach/id.h>
+ #include "soc.h"
#include "control.h"
static unsigned int omap_revision;
}
if (j == ARRAY_SIZE(omap_ids)) {
- printk(KERN_ERR "Unknown OMAP device type. "
- "Handling it as OMAP%04x\n",
- omap_ids[i].type >> 16);
+ pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
+ omap_ids[i].type >> 16);
j = i;
}
#include <linux/of_address.h>
#include <linux/of_irq.h>
- #include <mach/hardware.h>
-
+ #include "soc.h"
#include "iomap.h"
#include "common.h"
#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
+ #define INTCPS_NR_MIR_REGS 3
+ #define INTCPS_NR_IRQS 96
/*
* OMAP2 has a number of different interrupt controllers, each interrupt
unsigned long tmp;
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
- printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
- "(revision %ld.%ld) with %d interrupts\n",
- bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+ pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
+ bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
tmp |= 1 << 1; /* soft reset */
#include <mach/omap-wakeupgen.h>
#include <mach/omap-secure.h>
+ #include "soc.h"
#include "omap4-sar-layout.h"
#include "common.h"
static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_SPINLOCK(wakeupgen_lock);
-static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_target_cpu[MAX_IRQS];
static unsigned int irq_banks = MAX_NR_REG_BANKS;
static unsigned int max_irqs = MAX_IRQS;
static unsigned int omap_secure_apis;
#include <linux/slab.h>
#include <linux/bootmem.h>
- #include "common.h"
- #include <plat/cpu.h>
- #include "clockdomain.h"
- #include "powerdomain.h"
#include <plat/clock.h>
#include <plat/omap_hwmod.h>
#include <plat/prcm.h>
+ #include "soc.h"
+ #include "common.h"
+ #include "clockdomain.h"
+ #include "powerdomain.h"
#include "cm2xxx_3xxx.h"
#include "cminst44xx.h"
#include "prm2xxx_3xxx.h"
* Return the bit position of the reset line that match the
* input name. Return -ENOENT if not found.
*/
-static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
- struct omap_hwmod_rst_info *ohri)
+static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+ struct omap_hwmod_rst_info *ohri)
{
int i;
static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
- u8 ret = -EINVAL;
+ int ret = -EINVAL;
if (!oh)
return -EINVAL;
return -ENOSYS;
ret = _lookup_hardreset(oh, name, &ohri);
- if (IS_ERR_VALUE(ret))
+ if (ret < 0)
return ret;
ret = soc_ops.assert_hardreset(oh, &ohri);
static int _read_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
- u8 ret = -EINVAL;
+ int ret = -EINVAL;
if (!oh)
return -EINVAL;
return -ENOSYS;
ret = _lookup_hardreset(oh, name, &ohri);
- if (IS_ERR_VALUE(ret))
+ if (ret < 0)
return ret;
return soc_ops.is_hardreset_asserted(oh, &ohri);
/* clocks must be on for this operation */
if (oh->_state != _HWMOD_STATE_ENABLED) {
- pr_warning("omap_hwmod: %s: reset can only be entered from "
- "enabled state\n", oh->name);
+ pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
+ oh->name);
return -EINVAL;
}
_enable_sysc(oh);
}
} else {
+ _omap4_disable_module(oh);
_disable_clocks(oh);
pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
oh->name, r);
* XXX these should be marked initdata for multi-OMAP kernels
*/
#include <linux/power/smartreflex.h>
+ #include <linux/platform_data/gpio-omap.h>
#include <plat/omap_hwmod.h>
- #include <mach/irqs.h>
- #include <plat/cpu.h>
#include <plat/dma.h>
#include <plat/serial.h>
#include <plat/l3_3xxx.h>
#include <plat/l4_3xxx.h>
#include <plat/i2c.h>
- #include <plat/gpio.h>
#include <plat/mmc.h>
#include <plat/mcbsp.h>
#include <plat/mcspi.h>
#include <plat/dmtimer.h>
+ #include <mach/am35xx.h>
+
+ #include "soc.h"
#include "omap_hwmod_common_data.h"
#include "prm-regbits-34xx.h"
#include "cm-regbits-34xx.h"
#include "wd_timer.h"
- #include <mach/am35xx.h>
/*
* OMAP3xxx hardware module integration data
/* L3 */
static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
- { .irq = INT_34XX_L3_DBG_IRQ },
- { .irq = INT_34XX_L3_APP_IRQ },
- { .irq = -1 }
+ { .irq = 9 + OMAP_INTC_START, },
+ { .irq = 10 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_l3_main_hwmod = {
/* IVA2 (IVA2) */
static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
- { .name = "logic", .rst_shift = 0 },
- { .name = "seq0", .rst_shift = 1 },
- { .name = "seq1", .rst_shift = 2 },
+ { .name = "logic", .rst_shift = 0, .st_shift = 8 },
+ { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
+ { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
};
static struct omap_hwmod omap3xxx_iva_hwmod = {
.rst_lines = omap3xxx_iva_resets,
.rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
.main_clk = "iva2_ck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = OMAP3430_IVA2_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
+ }
+ },
};
/* timer class */
/* timer12 */
static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
- { .irq = 95, },
- { .irq = -1 }
+ { .irq = 95 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_timer12_hwmod = {
/* UART4 */
static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
- { .irq = INT_36XX_UART4_IRQ, },
- { .irq = -1 }
+ { .irq = 80 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
};
static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
- { .irq = INT_35XX_UART4_IRQ, },
- { .irq = -1 }
+ { .irq = 84 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
};
static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
- { .irq = 25 },
- { .irq = -1 }
+ { .irq = 25 + OMAP_INTC_START, },
+ { .irq = -1 },
};
/* dss_dsi1 */
};
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
- { .irq = INT_34XX_I2C3_IRQ, },
- { .irq = -1 }
+ { .irq = 61 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
/* gpio5 */
static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
- { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
- { .irq = -1 }
+ { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
+ { .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
/* gpio6 */
static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
- { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
- { .irq = -1 }
+ { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
+ { .irq = -1 },
};
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
/* mcbsp1 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
- { .name = "common", .irq = 16 },
- { .name = "tx", .irq = 59 },
- { .name = "rx", .irq = 60 },
- { .irq = -1 }
+ { .name = "common", .irq = 16 + OMAP_INTC_START, },
+ { .name = "tx", .irq = 59 + OMAP_INTC_START, },
+ { .name = "rx", .irq = 60 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
/* mcbsp2 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
- { .name = "common", .irq = 17 },
- { .name = "tx", .irq = 62 },
- { .name = "rx", .irq = 63 },
- { .irq = -1 }
+ { .name = "common", .irq = 17 + OMAP_INTC_START, },
+ { .name = "tx", .irq = 62 + OMAP_INTC_START, },
+ { .name = "rx", .irq = 63 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
/* mcbsp3 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
- { .name = "common", .irq = 22 },
- { .name = "tx", .irq = 89 },
- { .name = "rx", .irq = 90 },
- { .irq = -1 }
+ { .name = "common", .irq = 22 + OMAP_INTC_START, },
+ { .name = "tx", .irq = 89 + OMAP_INTC_START, },
+ { .name = "rx", .irq = 90 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
/* mcbsp4 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
- { .name = "common", .irq = 23 },
- { .name = "tx", .irq = 54 },
- { .name = "rx", .irq = 55 },
- { .irq = -1 }
+ { .name = "common", .irq = 23 + OMAP_INTC_START, },
+ { .name = "tx", .irq = 54 + OMAP_INTC_START, },
+ { .name = "rx", .irq = 55 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
/* mcbsp5 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
- { .name = "common", .irq = 27 },
- { .name = "tx", .irq = 81 },
- { .name = "rx", .irq = 82 },
- { .irq = -1 }
+ { .name = "common", .irq = 27 + OMAP_INTC_START, },
+ { .name = "tx", .irq = 81 + OMAP_INTC_START, },
+ { .name = "rx", .irq = 82 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
/* mcbsp2_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
- { .name = "irq", .irq = 4 },
- { .irq = -1 }
+ { .name = "irq", .irq = 4 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
/* mcbsp3_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
- { .name = "irq", .irq = 5 },
- { .irq = -1 }
+ { .name = "irq", .irq = 5 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
};
static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
- { .irq = 18 },
- { .irq = -1 }
+ { .irq = 18 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap34xx_sr1_hwmod = {
};
static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
- { .irq = 19 },
- { .irq = -1 }
+ { .irq = 19 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap34xx_sr2_hwmod = {
};
static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
- { .irq = 26 },
- { .irq = -1 }
+ { .irq = 26 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_mailbox_hwmod = {
/* mcspi3 */
static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
- { .name = "irq", .irq = 91 }, /* 91 */
- { .irq = -1 }
+ { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
/* mcspi4 */
static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
- { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
- { .irq = -1 }
+ { .name = "irq", .irq = 48 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
/* usb_otg_hs */
static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
- { .name = "mc", .irq = 92 },
- { .name = "dma", .irq = 93 },
- { .irq = -1 }
+ { .name = "mc", .irq = 92 + OMAP_INTC_START, },
+ { .name = "dma", .irq = 93 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
/* usb_otg_hs */
static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
- { .name = "mc", .irq = 71 },
- { .irq = -1 }
+ { .name = "mc", .irq = 71 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_class am35xx_usbotg_class = {
/* MMC/SD/SDIO1 */
static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
- { .irq = 83, },
- { .irq = -1 }
+ { .irq = 83 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
/* MMC/SD/SDIO2 */
static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
- { .irq = INT_24XX_MMC2_IRQ, },
- { .irq = -1 }
+ { .irq = 86 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
/* MMC/SD/SDIO3 */
static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
- { .irq = 94, },
- { .irq = -1 }
+ { .irq = 94 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
};
static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
- { .name = "ohci-irq", .irq = 76 },
- { .name = "ehci-irq", .irq = 77 },
- { .irq = -1 }
+ { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
+ { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
};
static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
- { .name = "tll-irq", .irq = 78 },
- { .irq = -1 }
+ { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
+ { .irq = -1 },
};
static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
};
static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
- { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
- { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
- { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
- { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
- { .irq = -1 }
+ { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
+ { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
+ { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
+ { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
+ { .irq = -1 },
};
static struct omap_hwmod_class am35xx_emac_class = {
*/
#include <linux/io.h>
+ #include <linux/platform_data/gpio-omap.h>
#include <linux/power/smartreflex.h>
#include <plat/omap_hwmod.h>
- #include <plat/cpu.h>
#include <plat/i2c.h>
- #include <plat/gpio.h>
#include <plat/dma.h>
#include <plat/mcspi.h>
#include <plat/mcbsp.h>
};
/* dsp -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
.master = &omap44xx_dsp_hwmod,
.slave = &omap44xx_sl2if_hwmod,
.clk = "dpll_iva_m5x2_ck",
};
/* iva -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
.master = &omap44xx_iva_hwmod,
.slave = &omap44xx_sl2if_hwmod,
.clk = "dpll_iva_m5x2_ck",
};
/* l3_main_2 -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_sl2if_hwmod,
.clk = "l3_div_ck",
&omap44xx_l4_abe__dmic,
&omap44xx_l4_abe__dmic_dma,
&omap44xx_dsp__iva,
- &omap44xx_dsp__sl2if,
+ /* &omap44xx_dsp__sl2if, */
&omap44xx_l4_cfg__dsp,
&omap44xx_l3_main_2__dss,
&omap44xx_l4_per__dss,
&omap44xx_l4_per__i2c4,
&omap44xx_l3_main_2__ipu,
&omap44xx_l3_main_2__iss,
- &omap44xx_iva__sl2if,
+ /* &omap44xx_iva__sl2if, */
&omap44xx_l3_main_2__iva,
&omap44xx_l4_wkup__kbd,
&omap44xx_l4_cfg__mailbox,
&omap44xx_l4_cfg__cm_core,
&omap44xx_l4_wkup__prm,
&omap44xx_l4_wkup__scrm,
- &omap44xx_l3_main_2__sl2if,
+ /* &omap44xx_l3_main_2__sl2if, */
&omap44xx_l4_abe__slimbus1,
&omap44xx_l4_abe__slimbus1_dma,
&omap44xx_l4_per__slimbus2,
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
+ #include <linux/platform_data/gpio-omap.h>
+
#include <trace/events/power.h>
#include <asm/suspend.h>
list_for_each_entry(pwrst, &pwrst_list, node) {
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
if (state > pwrst->next_state) {
- pr_info("Powerdomain (%s) didn't enter "
- "target state %d\n",
- pwrst->pwrdm->name, pwrst->next_state);
+ pr_info("Powerdomain (%s) didn't enter target state %d\n",
+ pwrst->pwrdm->name, pwrst->next_state);
ret = -1;
}
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
omap3_secure_ram_storage =
kmalloc(0x803F, GFP_KERNEL);
if (!omap3_secure_ram_storage)
- pr_err("Memory allocation failed when "
- "allocating for secure sram context\n");
+ pr_err("Memory allocation failed when allocating for secure sram context\n");
local_irq_disable();
local_fiq_disable();
#include "prm44xx.h"
#include <asm/cpu.h>
- #include <plat/cpu.h>
+
+ #include <plat/prcm.h>
+
#include "powerdomain.h"
#include "clockdomain.h"
- #include <plat/prcm.h>
+ #include "soc.h"
#include "pm.h"
#define PWRDM_TRACE_STATES_FLAG (1<<31)
if (!pwrdm || !clkdm)
return -EINVAL;
- pr_debug("powerdomain: associating clockdomain %s with powerdomain "
- "%s\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: associating clockdomain %s\n",
+ pwrdm->name, clkdm->name);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
if (!pwrdm->pwrdm_clkdms[i])
}
if (i == PWRDM_MAX_CLKDMS) {
- pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
- "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+ pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n",
+ pwrdm->name, clkdm->name);
WARN_ON(1);
ret = -ENOMEM;
goto pac_exit;
if (!pwrdm || !clkdm)
return -EINVAL;
- pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
- "%s\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
+ pwrdm->name, clkdm->name);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
if (pwrdm->pwrdm_clkdms[i] == clkdm)
break;
if (i == PWRDM_MAX_CLKDMS) {
- pr_debug("powerdomain: clkdm %s not associated with pwrdm "
- "%s ?!\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
+ pwrdm->name, clkdm->name);
ret = -ENOENT;
goto pdc_exit;
}
if (!(pwrdm->pwrsts & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+ pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
pwrdm->name, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+ pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
pwrdm->name, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next memory powerstate for domain %s "
- "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+ pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n",
+ pwrdm->name, bank, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next memory powerstate for domain %s "
- "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+ pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n",
+ pwrdm->name, bank, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
* warn & fail if it is not ON.
*/
- pr_debug("powerdomain: clearing previous power state reg for %s\n",
+ pr_debug("powerdomain: %s: clearing previous power state reg\n",
pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return ret;
- pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
- pwrdm->name);
+ pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return ret;
- pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
- pwrdm->name);
+ pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
#include "common.h"
#include <plat/prcm.h>
- #include <plat/irqs.h>
#include "clock.h"
#include "clock2xxx.h"
MAX_MODULE_ENABLE_WAIT, i);
if (i < MAX_MODULE_ENABLE_WAIT)
- pr_debug("cm: Module associated with clock %s ready after %d "
- "loops\n", name, i);
+ pr_debug("cm: Module associated with clock %s ready after %d loops\n",
+ name, i);
else
- pr_err("cm: Module associated with clock %s didn't enable in "
- "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+ pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
+ name, MAX_MODULE_ENABLE_WAIT);
return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
};
#include <plat/omap-serial.h>
#include "common.h"
- #include <plat/board.h>
#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>
+ #include <plat/serial.h>
#include "prm2xxx_3xxx.h"
#include "pm.h"
};
#ifdef CONFIG_PM
- static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+ static void omap_uart_enable_wakeup(struct device *dev, bool enable)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct omap_device *od = to_omap_device(pdev);
if (!od)
* in Smartidle Mode When Configured for DMA Operations.
* WA: configure uart in force idle mode.
*/
- static void omap_uart_set_noidle(struct platform_device *pdev)
+ static void omap_uart_set_noidle(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct omap_device *od = to_omap_device(pdev);
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
}
- static void omap_uart_set_smartidle(struct platform_device *pdev)
+ static void omap_uart_set_smartidle(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct omap_device *od = to_omap_device(pdev);
u8 idlemode;
}
#else
- static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+ static void omap_uart_enable_wakeup(struct device *dev, bool enable)
{}
- static void omap_uart_set_noidle(struct platform_device *pdev) {}
- static void omap_uart_set_smartidle(struct platform_device *pdev) {}
+ static void omap_uart_set_noidle(struct device *dev) {}
+ static void omap_uart_set_smartidle(struct device *dev) {}
#endif /* CONFIG_PM */
#ifdef CONFIG_OMAP_MUX
if (console_loglevel >= 10) {
uart_debug = true;
- pr_info("%s used as console in debug mode"
- " uart%d clocks will not be"
- " gated", uart_name, uart->num);
+ pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
+ uart_name, uart->num);
}
if (cmdline_find_option("no_console_suspend"))
omap_up.dma_rx_timeout = info->dma_rx_timeout;
omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
omap_up.autosuspend_timeout = info->autosuspend_timeout;
+ omap_up.DTR_gpio = info->DTR_gpio;
+ omap_up.DTR_inverted = info->DTR_inverted;
+ omap_up.DTR_present = info->DTR_present;
pdata = &omap_up;
pdata_size = sizeof(struct omap_uart_port_info);
pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
NULL, 0, false);
- WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
- name, oh->name);
+ if (IS_ERR(pdev)) {
+ WARN(1, "Could not build omap_device for %s: %s.\n", name,
+ oh->name);
+ return;
+ }
if ((console_uart_id == bdata->id) && no_console_suspend)
omap_device_disable_idle_on_suspend(pdev);
#include <linux/slab.h>
#include <asm/mach/time.h>
- #include <plat/dmtimer.h>
#include <asm/smp_twd.h>
#include <asm/sched_clock.h>
- #include "common.h"
+
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
+ #include <plat/dmtimer.h>
#include <plat/omap-pm.h>
+ #include "soc.h"
+ #include "common.h"
#include "powerdomain.h"
/* Parent clocks, eventually these will come from the clock framework */
res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
BUG_ON(res);
- omap2_gp_timer_irq.dev_id = (void *)&clkev;
+ omap2_gp_timer_irq.dev_id = &clkev;
setup_irq(clkev.irq, &omap2_gp_timer_irq);
__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
return 0;
}
+#ifdef CONFIG_OMAP_32K_TIMER
/* Setup free-running counter for clocksource */
static int __init omap2_sync32k_clocksource_init(void)
{
return ret;
}
+#else
+static inline int omap2_sync32k_clocksource_init(void)
+{
+ return -ENODEV;
+}
+#endif
static void __init omap2_gptimer_clocksource_init(int gptimer_id,
const char *fck_source)
#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_LOCAL_TIMERS
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
- OMAP44XX_LOCAL_TWD_BASE,
- OMAP44XX_IRQ_LOCALTIMER);
+ OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START);
#endif
static void __init omap4_timer_init(void)
#include <linux/init.h>
#include <linux/bug.h>
- #include <plat/cpu.h>
-
+ #include "soc.h"
#include "voltage.h"
#include "vc.h"
#include "prm-regbits-34xx.h"
}
if (!voltdm->pmic->uv_to_vsel) {
- pr_err("%s: PMIC function to convert voltage in uV to"
- "vsel not registered. Hence unable to scale voltage"
- "for vdd_%s\n", __func__, voltdm->name);
+ pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
+ __func__, voltdm->name);
return -ENODATA;
}
#include <linux/slab.h>
#include <linux/delay.h>
- #include <mach/hardware.h>
+ #include <plat/cpu.h>
#include <plat/dma.h>
-
#include <plat/tc.h>
/*
l = p->dma_read(CCR, lch);
}
if (i >= 100)
- printk(KERN_ERR "DMA drain did not complete on "
- "lch %d\n", lch);
+ pr_err("DMA drain did not complete on lch %d\n", lch);
/* Restore OCP_SYSCONFIG */
p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
} else {
if ((dma_chan[lch_head].dev_id == -1) ||
(dma_chan[lch_queue].dev_id == -1)) {
- printk(KERN_ERR "omap_dma: trying to link "
- "non requested channels\n");
+ pr_err("omap_dma: trying to link non requested channels\n");
dump_stack();
}
if (dma_chan[lch_head].next_lch != lch_queue ||
dma_chan[lch_head].next_lch == -1) {
- printk(KERN_ERR "omap_dma: trying to unlink "
- "non linked channels\n");
+ pr_err("omap_dma: trying to unlink non linked channels\n");
dump_stack();
}
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
(dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
- printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
- "before unlinking\n");
+ pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
dump_stack();
}
if ((csr & 0x3f) == 0)
return 0;
if (unlikely(dma_chan[ch].dev_id == -1)) {
- printk(KERN_WARNING "Spurious interrupt from DMA channel "
- "%d (CSR %04x)\n", ch, csr);
+ pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
+ ch, csr);
return 0;
}
if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
- printk(KERN_WARNING "DMA timeout with device %d\n",
- dma_chan[ch].dev_id);
+ pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ))
- printk(KERN_WARNING "DMA synchronization event drop occurred "
- "with device %d\n", dma_chan[ch].dev_id);
+ pr_warn("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (likely(csr & OMAP_DMA_BLOCK_IRQ))
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
if (likely(dma_chan[ch].callback != NULL))
if (!status) {
if (printk_ratelimit())
- printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
- ch);
+ pr_warn("Spurious DMA IRQ for lch %d\n", ch);
p->dma_write(1 << ch, IRQSTATUS_L0, ch);
return 0;
}
if (unlikely(dma_chan[ch].dev_id == -1)) {
if (printk_ratelimit())
- printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
- "channel %d\n", status, ch);
+ pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
+ status, ch);
return 0;
}
if (unlikely(status & OMAP_DMA_DROP_IRQ))
- printk(KERN_INFO
- "DMA synchronization event drop occurred with device "
- "%d\n", dma_chan[ch].dev_id);
+ pr_info("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
printk(KERN_INFO "DMA transaction error with device %d\n",
dma_chan[ch].dev_id);
p = pdev->dev.platform_data;
if (!p) {
- dev_err(&pdev->dev, "%s: System DMA initialized without"
- "platform data\n", __func__);
+ dev_err(&pdev->dev,
+ "%s: System DMA initialized without platform data\n",
+ __func__);
return -EINVAL;
}
}
ret = setup_irq(dma_irq, &omap24xx_dma_irq);
if (ret) {
- dev_err(&pdev->dev, "set_up failed for IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
goto exit_dma_lch_fail;
}
}
/* reserve dma channels 0 and 1 in high security devices */
if (cpu_is_omap34xx() &&
(omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
- "HS ROM code\n");
+ pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
dma_chan[0].dev_id = 0;
dma_chan[1].dev_id = 1;
}
return 0;
exit_dma_irq_fail:
- dev_err(&pdev->dev, "unable to request IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
for (irq_rel = 0; irq_rel < ch; irq_rel++) {
dma_irq = platform_get_irq(pdev, irq_rel);
free_irq(dma_irq, (void *)(irq_rel + 1));
#include <asm/mach/map.h>
#include <plat/sram.h>
- #include <plat/board.h>
#include <plat/cpu.h>
#include "sram.h"
static unsigned long omap_sram_start;
static void __iomem *omap_sram_base;
+static unsigned long omap_sram_skip;
static unsigned long omap_sram_size;
static void __iomem *omap_sram_ceil;
*/
static void __init omap_detect_sram(void)
{
+ omap_sram_skip = SRAM_BOOTLOADER_SZ;
if (cpu_class_is_omap2()) {
if (is_sram_locked()) {
if (cpu_is_omap34xx()) {
if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
omap_sram_size = 0x7000; /* 28K */
+ omap_sram_skip += SZ_16K;
} else {
omap_sram_size = 0x8000; /* 32K */
}
return;
#ifdef CONFIG_OMAP4_ERRATA_I688
+ if (cpu_is_omap44xx()) {
omap_sram_start += PAGE_SIZE;
omap_sram_size -= SZ_16K;
+ }
#endif
if (cpu_is_omap34xx()) {
/*
* Looks like we need to preserve some bootloader code at the
* beginning of SRAM for jumping to flash for reboot to work...
*/
- memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
- omap_sram_size - SRAM_BOOTLOADER_SZ);
+ memset_io(omap_sram_base + omap_sram_skip, 0,
+ omap_sram_size - omap_sram_skip);
}
/*
{
unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
- available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
+ available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
if (size > available) {
pr_err("Not enough space in SRAM\n");
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
unsigned short trcv_delay; /* transceiver delay */
struct clk *clk_ipg;
struct clk *clk_per;
- struct imx_uart_data *devdata;
+ const struct imx_uart_data *devdata;
};
struct imx_port_ucrs {
static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
{
unsigned int val;
- unsigned int ufcr_rfdiv;
-
- /* set receiver / transmitter trigger level.
- * RFDIV is set such way to satisfy requested uartclk value
- */
- val = TXTL << 10 | RXTL;
- ufcr_rfdiv = (clk_get_rate(sport->clk_per) + sport->port.uartclk / 2)
- / sport->port.uartclk;
-
- if(!ufcr_rfdiv)
- ufcr_rfdiv = 1;
-
- val |= UFCR_RFDIV_REG(ufcr_rfdiv);
+ /* set receiver / transmitter trigger level */
+ val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
+ val |= TXTL << UFCR_TXTL_SHF | RXTL;
writel(val, sport->port.membase + UFCR);
-
return 0;
}
}
}
+ spin_lock_irqsave(&sport->port.lock, flags);
/*
* Finally, clear and enable interrupts
*/
/*
* Enable modem status interrupts
*/
- spin_lock_irqsave(&sport->port.lock,flags);
imx_enable_ms(&sport->port);
spin_unlock_irqrestore(&sport->port.lock,flags);
{
struct imx_port *sport = (struct imx_port *)port;
unsigned long temp;
+ unsigned long flags;
+ spin_lock_irqsave(&sport->port.lock, flags);
temp = readl(sport->port.membase + UCR2);
temp &= ~(UCR2_TXEN);
writel(temp, sport->port.membase + UCR2);
+ spin_unlock_irqrestore(&sport->port.lock, flags);
if (USE_IRDA(sport)) {
struct imxuart_platform_data *pdata;
* Disable all interrupts, port and break condition.
*/
+ spin_lock_irqsave(&sport->port.lock, flags);
temp = readl(sport->port.membase + UCR1);
temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
if (USE_IRDA(sport))
temp &= ~(UCR1_IREN);
writel(temp, sport->port.membase + UCR1);
+ spin_unlock_irqrestore(&sport->port.lock, flags);
}
static void
struct imx_port *sport = imx_ports[co->index];
struct imx_port_ucrs old_ucr;
unsigned int ucr1;
+ unsigned long flags;
+
+ spin_lock_irqsave(&sport->port.lock, flags);
/*
* First, save UCR1/2/3 and then disable interrupts
while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
imx_port_ucrs_restore(&sport->port, &old_ucr);
+
+ spin_unlock_irqrestore(&sport->port.lock, flags);
}
/*
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
if (IS_ERR(pinctrl)) {
ret = PTR_ERR(pinctrl);
+ dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
goto unmap;
}
sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(sport->clk_ipg)) {
ret = PTR_ERR(sport->clk_ipg);
+ dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
goto unmap;
}
sport->clk_per = devm_clk_get(&pdev->dev, "per");
if (IS_ERR(sport->clk_per)) {
ret = PTR_ERR(sport->clk_per);
+ dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
goto unmap;
}
#ifdef VERBOSE_DEBUG
+#ifndef pr_vdebug
#define pr_vdebug(fmt, arg...) \
pr_debug(fmt, ##arg)
+#endif /* pr_vdebug */
#else
+#ifndef pr_vdebig
#define pr_vdebug(fmt, arg...) \
({ if (0) pr_debug(fmt, ##arg); })
+#endif /* pr_vdebug */
#endif
/*-------------------------------------------------------------------------*/
for (i = 0; i < count; i++) {
struct device *tty_dev;
- tty_dev = tty_register_device(gs_tty_driver, i, &g->dev);
+ tty_dev = tty_port_register_device(&ports[i].port->port,
+ gs_tty_driver, i, &g->dev);
if (IS_ERR(tty_dev))
pr_warning("%s: no classdev for port %d, err %ld\n",
__func__, i, PTR_ERR(tty_dev));
{ USB_DEVICE(FTDI_VID, FTDI_PCDJ_DAC2_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_RRCIRKITS_LOCOBUFFER_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_ASK_RDR400_PID) },
+ { USB_DEVICE(FTDI_VID, FTDI_NZR_SEM_USB_PID) },
{ USB_DEVICE(ICOM_VID, ICOM_ID_1_PID) },
{ USB_DEVICE(ICOM_VID, ICOM_OPC_U_UC_PID) },
{ USB_DEVICE(ICOM_VID, ICOM_ID_RP2C1_PID) },
.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
{ USB_DEVICE(ADI_VID, ADI_GNICEPLUS_PID),
.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
- { USB_DEVICE(MICROCHIP_VID, MICROCHIP_USB_BOARD_PID) },
+ { USB_DEVICE_AND_INTERFACE_INFO(MICROCHIP_VID, MICROCHIP_USB_BOARD_PID,
+ USB_CLASS_VENDOR_SPEC,
+ USB_SUBCLASS_VENDOR_SPEC, 0x00) },
{ USB_DEVICE(JETI_VID, JETI_SPC1201_PID) },
{ USB_DEVICE(MARVELL_VID, MARVELL_SHEEVAPLUG_PID),
.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
{ USB_DEVICE(LARSENBRUSGAARD_VID, LB_ALTITRACK_PID) },
{ USB_DEVICE(GN_OTOMETRICS_VID, AURICAL_USB_PID) },
+ { USB_DEVICE(FTDI_VID, PI_C865_PID) },
+ { USB_DEVICE(FTDI_VID, PI_C857_PID) },
+ { USB_DEVICE(PI_VID, PI_C866_PID) },
+ { USB_DEVICE(PI_VID, PI_C663_PID) },
+ { USB_DEVICE(PI_VID, PI_C725_PID) },
+ { USB_DEVICE(PI_VID, PI_E517_PID) },
+ { USB_DEVICE(PI_VID, PI_C863_PID) },
{ USB_DEVICE(PI_VID, PI_E861_PID) },
+ { USB_DEVICE(PI_VID, PI_C867_PID) },
+ { USB_DEVICE(PI_VID, PI_E609_PID) },
+ { USB_DEVICE(PI_VID, PI_E709_PID) },
+ { USB_DEVICE(PI_VID, PI_100F_PID) },
+ { USB_DEVICE(PI_VID, PI_1011_PID) },
+ { USB_DEVICE(PI_VID, PI_1012_PID) },
+ { USB_DEVICE(PI_VID, PI_1013_PID) },
+ { USB_DEVICE(PI_VID, PI_1014_PID) },
+ { USB_DEVICE(PI_VID, PI_1015_PID) },
+ { USB_DEVICE(PI_VID, PI_1016_PID) },
{ USB_DEVICE(KONDO_VID, KONDO_USB_SERIAL_PID) },
{ USB_DEVICE(BAYER_VID, BAYER_CONTOUR_CABLE_PID) },
{ USB_DEVICE(FTDI_VID, MARVELL_OPENRD_PID),
{
struct usb_device *dev = port->serial->dev;
struct ftdi_private *priv = usb_get_serial_port_data(port);
- struct ktermios *termios = tty->termios;
+ struct ktermios *termios = &tty->termios;
unsigned int cflag = termios->c_cflag;
__u16 urb_value; /* will hold the new flags */
projects / platform / adaptation / renesas_rcar / renesas_kernel.git / commitdiff