rockchip: rk322x: move board_debug_uart_init() to rk322x.c

Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up header-list to not break FASTBOOT:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
index c50130c..888310e 100644 (file)
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -10,54 +10,13 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch-rockchip/cru_rk322x.h>
-#include <asm/arch-rockchip/grf_rk322x.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/timer.h>
-#include <asm/arch-rockchip/uart.h>
 
 u32 spl_boot_device(void)
 {
        return BOOT_DEVICE_MMC1;
 }
-#define GRF_BASE       0x11000000
-#define SGRF_BASE      0x10140000
-
-#define DEBUG_UART_BASE        0x11030000
-
-void board_debug_uart_init(void)
-{
-       static struct rk322x_grf * const grf = (void *)GRF_BASE;
-       enum {
-               GPIO1B2_SHIFT           = 4,
-               GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
-               GPIO1B2_GPIO            = 0,
-               GPIO1B2_UART1_SIN,
-               GPIO1B2_UART21_SIN,
-
-               GPIO1B1_SHIFT           = 2,
-               GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
-               GPIO1B1_GPIO            = 0,
-               GPIO1B1_UART1_SOUT,
-               GPIO1B1_UART21_SOUT,
-       };
-       enum {
-               CON_IOMUX_UART2SEL_SHIFT= 8,
-               CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
-               CON_IOMUX_UART2SEL_2    = 0,
-               CON_IOMUX_UART2SEL_21,
-       };
-
-       /* Enable early UART2 channel 1 on the RK322x */
-       rk_clrsetreg(&grf->gpio1b_iomux,
-                    GPIO1B1_MASK | GPIO1B2_MASK,
-                    GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
-                    GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
-       /* Set channel C as UART2 input */
-       rk_clrsetreg(&grf->con_iomux,
-                    CON_IOMUX_UART2SEL_MASK,
-                    CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
-}
 
 #define SGRF_DDR_CON0 0x10150000
 void board_init_f(ulong dummy)
@@ -65,6 +24,7 @@ void board_init_f(ulong dummy)
        struct udevice *dev;
        int ret;
 
+#ifdef CONFIG_DEBUG_UART
        /*
         * Debug UART can be used from here if required:
         *
@@ -75,7 +35,7 @@ void board_init_f(ulong dummy)
         */
        debug_uart_init();
        printascii("SPL Init");
-
+#endif
        ret = spl_early_init();
        if (ret) {
                debug("spl_early_init() failed: %d\n", ret);

diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
index f040c1b..6170c76 100644 (file)
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -10,8 +10,8 @@
 #include <asm/io.h>
 #include <asm/arch-rockchip/boot_mode.h>
 #include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/periph.h>
 #include <asm/arch-rockchip/grf_rk322x.h>
+#include <asm/arch-rockchip/periph.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -32,34 +32,7 @@ int board_init(void)
 #include <asm/arch-rockchip/grf_rk322x.h>
        /* Enable early UART2 channel 1 on the RK322x */
 #define GRF_BASE       0x11000000
-       struct rk322x_grf * const grf = (void *)GRF_BASE;
-       enum {
-               GPIO1B2_SHIFT           = 4,
-               GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
-               GPIO1B2_GPIO            = 0,
-               GPIO1B2_UART21_SIN,
-
-               GPIO1B1_SHIFT           = 2,
-               GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
-               GPIO1B1_GPIO            = 0,
-               GPIO1B1_UART1_SOUT,
-               GPIO1B1_UART21_SOUT,
-       };
-       enum {
-               CON_IOMUX_UART2SEL_SHIFT= 8,
-               CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
-               CON_IOMUX_UART2SEL_2    = 0,
-               CON_IOMUX_UART2SEL_21,
-       };
-
-       rk_clrsetreg(&grf->gpio1b_iomux,
-                    GPIO1B1_MASK | GPIO1B2_MASK,
-                    GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
-                    GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
-       /* Set channel C as UART2 input */
-       rk_clrsetreg(&grf->con_iomux,
-                    CON_IOMUX_UART2SEL_MASK,
-                    CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+       static struct rk322x_grf * const grf = (void *)GRF_BASE;
 
        /*
        * The integrated macphy is enabled by default, disable it

diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile
index ecb3e8d..89b0fed 100644 (file)
--- a/arch/arm/mach-rockchip/rk322x/Makefile
+++ b/arch/arm/mach-rockchip/rk322x/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-
 obj-y += clk_rk322x.o
+obj-y += rk322x.o
 obj-y += syscon_rk322x.o

diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
new file mode 100644 (file)
index 0000000..e5250bc
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#define GRF_BASE       0x11000000
+       static struct rk322x_grf * const grf = (void *)GRF_BASE;
+       enum {
+               GPIO1B2_SHIFT           = 4,
+               GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
+               GPIO1B2_GPIO            = 0,
+               GPIO1B2_UART1_SIN,
+               GPIO1B2_UART21_SIN,
+
+               GPIO1B1_SHIFT           = 2,
+               GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
+               GPIO1B1_GPIO            = 0,
+               GPIO1B1_UART1_SOUT,
+               GPIO1B1_UART21_SOUT,
+       };
+       enum {
+               CON_IOMUX_UART2SEL_SHIFT = 8,
+               CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+               CON_IOMUX_UART2SEL_2    = 0,
+               CON_IOMUX_UART2SEL_21,
+       };
+
+       /* Enable early UART2 channel 1 on the RK322x */
+       rk_clrsetreg(&grf->gpio1b_iomux,
+                    GPIO1B1_MASK | GPIO1B2_MASK,
+                    GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
+                    GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
+       /* Set channel C as UART2 input */
+       rk_clrsetreg(&grf->con_iomux,
+                    CON_IOMUX_UART2SEL_MASK,
+                    CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+}
+#endif