ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodes

J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT
entries for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index d590079..8ea25de 100644 (file)
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -93,6 +93,33 @@
                clock-names = "fclk";
        };
 
+       fss: system-controller@47000000 {
+               compatible = "syscon", "simple-mfd";
+               reg = <0x0 0x47000000 0x0 0x100>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               hbmc_mux: hbmc-mux {
+                       compatible = "mmio-mux";
+                       #mux-control-cells = <1>;
+                       mux-reg-masks = <0x4 0x2>; /* HBMC select */
+               };
+
+               hbmc: hyperbus@47034000 {
+                       compatible = "ti,am654-hbmc";
+                       reg = <0x0 0x47034000 0x0 0x100>,
+                               <0x5 0x00000000 0x1 0x0000000>;
+                       power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+                       mux-controls = <&hbmc_mux 0>;
+                       clocks = <&k3_clks 102 5>;
+                       assigned-clocks = <&k3_clks 102 5>;
+                       assigned-clock-rates = <333333333>;
+               };
+       };
+
        mcu_i2c0: i2c@40b00000 {
                compatible = "ti,j721e-i2c", "ti,omap4-i2c";
                reg = <0x0 0x40b00000 0x0 0x100>;

diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi
index 22fc50b..ea5280d 100644 (file)
--- a/arch/arm/dts/k3-j7200-som-p0.dtsi
+++ b/arch/arm/dts/k3-j7200-som-p0.dtsi
@@ -27,3 +27,36 @@
                };
        };
 };
+
+&wkup_pmx0 {
+       mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+                       J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+                       J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+                       J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+                       J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+                       J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+                       J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+                       J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+                       J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+                       J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+                       J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+                       J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+                       J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+               >;
+       };
+};
+
+&hbmc {
+       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+       ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
+                <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
+
+       flash@0,0 {
+               compatible = "cypress,hyperflash", "cfi-flash";
+               reg = <0x0 0x0 0x4000000>;
+       };
+};

diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi
index 7b2313d..126c31b 100644 (file)
--- a/arch/arm/dts/k3-j7200.dtsi
+++ b/arch/arm/dts/k3-j7200.dtsi
@@ -149,7 +149,8 @@
                         <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
                         <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
                         <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
-                        <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>;
+                        <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
+                        <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>;
 
                cbass_mcu_wakeup: bus@28380000 {
                        compatible = "simple-bus";
@@ -165,7 +166,8 @@
                                 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
                                 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
                                 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
-                                <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>; /* FSS OSPI0/1 data region 0 */
+                                <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
+                                <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>; /* FSS OSPI0 data region 3 */
                };
        };
 };