Fix more unrecognised GCN instructions

2019-12-09  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>): Change
	%s to %o in asm output.
	(gather<mode>_insn_2offsets<exec>): Likewise.

From-SVN: r279131

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index aec9bba..82a1bfb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-12-09  Andrew Stubbs  <ams@codesourcery.com>
+
+       * config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>): Change
+       %s to %o in asm output.
+       (gather<mode>_insn_2offsets<exec>): Likewise.
+
 2019-12-09  Richard Earnshaw  <rearnsha@arm.com>
 
        * config/arm/t-multilib: Use arm->thumb multilib reuse rules

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 95e0731..16b37e8 100644 (file)
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -722,7 +722,7 @@
          sprintf (buf, "flat_load%%o0\t%%0, %%1%s\;s_waitcnt\t0", glc);
       }
     else if (AS_GLOBAL_P (as))
-      sprintf (buf, "global_load%%s0\t%%0, %%1, off offset:%%2%s\;"
+      sprintf (buf, "global_load%%o0\t%%0, %%1, off offset:%%2%s\;"
               "s_waitcnt\tvmcnt(0)", glc);
     else
       gcc_unreachable ();
@@ -780,7 +780,7 @@
        /* Work around assembler bug in which a 64-bit register is expected,
        but a 32-bit value would be correct.  */
        int reg = REGNO (operands[2]) - FIRST_VGPR_REG;
-       sprintf (buf, "global_load%%s0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
+       sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
                      "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc);
       }
     else