amdgcn: Fix wrong-code bug in 64-bit masked add

2020-04-24  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
	of high-part.
	(add<mode>_sext_dup2_exec): Likewise.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4b6456e..30e9675 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-24  Andrew Stubbs  <ams@codesourcery.com>
+
+       * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
+       of high-part.
+       (add<mode>_sext_dup2_exec): Likewise.
+
 2020-04-24  Segher Boessenkool  <segher@kernel.crashing.org>
 
        PR target/94710

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 0422e15..d3badb4 100644 (file)
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1497,7 +1497,8 @@
     rtx dsthi = gcn_operand_part (<MODE>mode, operands[0], 1);
     emit_insn (gen_vec_duplicate<vnsi>_exec
                (dsthi, gcn_operand_part (DImode, operands[2], 1),
-                gcn_gen_undef (<VnSI>mode), operands[4]));
+                gcn_operand_part (<MODE>mode, operands[3], 1),
+                operands[4]));
     emit_insn (gen_addc<vnsi>3_exec
                (dsthi, dsthi, const0_rtx, vcc, vcc,
                 gcn_operand_part (<MODE>mode, operands[3], 1),
@@ -1564,7 +1565,8 @@
     rtx dsthi = gcn_operand_part (<MODE>mode, operands[0], 1);
     emit_insn (gen_vec_duplicate<vnsi>_exec
                (dsthi, gcn_operand_part (DImode, operands[2], 1),
-                gcn_gen_undef (<VnSI>mode), operands[4]));
+               gcn_operand_part (<MODE>mode, operands[3], 1),
+               operands[4]));
     emit_insn (gen_addc<vnsi>3_exec
                (dsthi, dsthi, operands[5], vcc, vcc,
                 gcn_operand_part (<MODE>mode, operands[3], 1),