}
so->rt[i].colormask = rt.colormask;
+
+ if (rt.colormask)
+ so->store |= (PIPE_CLEAR_COLOR0 << i);
}
return so;
so->back_stencil = so->front_stencil;
}
+ if (state->depth_enabled) {
+ if (state->depth_func != PIPE_FUNC_NEVER &&
+ state->depth_func != PIPE_FUNC_ALWAYS) {
+
+ so->load |= PIPE_CLEAR_DEPTH;
+ }
+
+ if (state->depth_writemask)
+ so->store |= PIPE_CLEAR_DEPTH;
+ }
+
+ if (state->stencil[0].enabled) {
+ so->load |= PIPE_CLEAR_STENCIL; /* TODO: Optimize */
+ so->store |= PIPE_CLEAR_STENCIL;
+ }
+
return so;
}
if (reduced_prim != batch->reduced_prim) ctx->dirty |= AGX_DIRTY_PRIM;
batch->reduced_prim = reduced_prim;
- /* TODO: masks */
- batch->draw |= ~0;
- batch->load |= ~0;
+ /* Update batch masks based on current state */
+ if (ctx->dirty & AGX_DIRTY_BLEND) {
+ /* TODO: Any point to tracking load? */
+ batch->draw |= ctx->blend->store;
+ batch->resolve |= ctx->blend->store;
+ }
+
+ if (ctx->dirty & AGX_DIRTY_ZS) {
+ batch->load |= ctx->zs->load;
+ batch->draw |= ctx->zs->store;
+ batch->resolve |= ctx->zs->store;
+ }
/* TODO: These are expensive calls, consider finer dirty tracking */
if (agx_update_vs(ctx))
struct agx_tilebuffer_layout tilebuffer_layout;
/* PIPE_CLEAR_* bitmask */
- uint32_t clear, draw, load;
+ uint32_t clear, draw, load, resolve;
/* Base of uploaded texture descriptors */
uint64_t textures;
struct pipe_depth_stencil_alpha_state base;
struct agx_fragment_face_packed depth;
struct agx_fragment_stencil_packed front_stencil, back_stencil;
+
+ /* PIPE_CLEAR_* bitmask corresponding to this depth/stencil state */
+ uint32_t load, store;
};
struct agx_blend {
bool logicop_enable, blend_enable;
nir_lower_blend_rt rt[8];
unsigned logicop_func;
+
+ /* PIPE_CLEAR_* bitmask corresponding to this blend state */
+ uint32_t store;
};
struct asahi_shader_key {