"version" : "1.6"
},
{
+ "opname" : "OpTypeCooperativeMatrixKHR",
+ "class" : "Type-Declaration",
+ "opcode" : 4456,
+ "operands" : [
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Component Type'" },
+ { "kind" : "IdScope", "name" : "'Scope'" },
+ { "kind" : "IdRef", "name" : "'Rows'" },
+ { "kind" : "IdRef", "name" : "'Columns'" },
+ { "kind" : "IdRef", "name" : "'Use'" }
+ ],
+ "capabilities" : [ "CooperativeMatrixKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpCooperativeMatrixLoadKHR",
+ "class" : "Memory",
+ "opcode" : 4457,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Pointer'" },
+ { "kind" : "IdRef", "name" : "'MemoryLayout'" },
+ { "kind" : "IdRef", "name" : "'Stride'", "quantifier": "?" },
+ { "kind" : "MemoryAccess", "name" : "'Memory Operand'", "quantifier" : "?" }
+ ],
+ "capabilities" : [ "CooperativeMatrixKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpCooperativeMatrixStoreKHR",
+ "class" : "Memory",
+ "opcode" : 4458,
+ "operands" : [
+ { "kind" : "IdRef", "name" : "'Pointer'" },
+ { "kind" : "IdRef", "name" : "'Object'" },
+ { "kind" : "IdRef", "name" : "'MemoryLayout'" },
+ { "kind" : "IdRef", "name" : "'Stride'", "quantifier": "?" },
+ { "kind" : "MemoryAccess", "name" : "'Memory Operand'", "quantifier" : "?" }
+ ],
+ "capabilities" : [ "CooperativeMatrixKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpCooperativeMatrixMulAddKHR",
+ "class" : "Arithmetic",
+ "opcode" : 4459,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'A'" },
+ { "kind" : "IdRef", "name" : "'B'" },
+ { "kind" : "IdRef", "name" : "'C'" },
+ { "kind" : "CooperativeMatrixOperands", "name" : "'Cooperative Matrix Operands'", "quantifier" : "?" }
+ ],
+ "capabilities" : [ "CooperativeMatrixKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpCooperativeMatrixLengthKHR",
+ "class" : "Miscellaneous",
+ "opcode" : 4460,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Type'" }
+ ],
+ "capabilities" : [ "CooperativeMatrixKHR" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpTypeRayQueryKHR",
"class" : "Reserved",
"opcode" : 4472,
"version" : "None"
},
{
+ "opname" : "OpFinalizeNodePayloadsAMDX",
+ "class" : "Reserved",
+ "opcode" : 5075,
+ "operands" : [
+ { "kind" : "IdRef", "name": "'Payload Array'" }
+ ],
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpFinishWritingNodePayloadAMDX",
+ "class" : "Reserved",
+ "opcode" : 5078,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name": "'Payload'" }
+ ],
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpInitializeNodePayloadsAMDX",
+ "class" : "Reserved",
+ "opcode" : 5090,
+ "operands" : [
+ { "kind" : "IdRef", "name": "'Payload Array'" },
+ { "kind" : "IdScope", "name": "'Visibility'" },
+ { "kind" : "IdRef", "name": "'Payload Count'" },
+ { "kind" : "IdRef", "name": "'Node Index'" }
+ ],
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpHitObjectRecordHitMotionNV",
"class" : "Reserved",
"opcode" : 5249,
{
"enumerant" : "SYCL",
"value" : 7
+ },
+ {
+ "enumerant" : "HERO_C",
+ "value" : 8
+ },
+ {
+ "enumerant" : "NZSL",
+ "value" : 9
+ },
+ {
+ "enumerant" : "WGSL",
+ "value" : 10
}
]
},
"version" : "None"
},
{
+ "enumerant" : "CoalescingAMDX",
+ "value" : 5069,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MaxNodeRecursionAMDX",
+ "value" : 5071,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'Number of recursions'" }
+ ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "StaticNumWorkgroupsAMDX",
+ "value" : 5072,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'x size'" },
+ { "kind" : "IdRef", "name" : "'y size'" },
+ { "kind" : "IdRef", "name" : "'z size'" }
+ ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "ShaderIndexAMDX",
+ "value" : 5073,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'Shader Index'" }
+ ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MaxNumWorkgroupsAMDX",
+ "value" : 5077,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'x size'" },
+ { "kind" : "IdRef", "name" : "'y size'" },
+ { "kind" : "IdRef", "name" : "'z size'" }
+ ],
+ "version" : "None"
+ },
+ {
"enumerant": "StencilRefUnchangedFrontAMD",
"value": 5079,
"capabilities": [ "StencilExportEXT" ],
"version" : "None"
},
{
+ "enumerant" : "NodePayloadAMDX",
+ "value" : 5068,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "NodeOutputPayloadAMDX",
+ "value" : 5076,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "CallableDataNV",
"value" : 5328,
"extensions" : [ "SPV_NV_ray_tracing" , "SPV_KHR_ray_tracing" ],
"enumerant" : "UnormInt101010_2",
"value" : 16,
"capabilities" : [ "Kernel" ]
+ },
+ {
+ "enumerant" : "UnsignedIntRaw10EXT",
+ "value" : 19,
+ "capabilities" : [ "Kernel" ]
+ },
+ {
+ "enumerant" : "UnsignedIntRaw12EXT",
+ "value" : 20,
+ "capabilities" : [ "Kernel" ]
}
]
},
},
{
"category" : "ValueEnum",
+ "kind" : "HostAccessQualifier",
+ "enumerants" : [
+ {
+ "enumerant" : "NoneINTEL",
+ "value" : 0,
+ "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+ },
+ {
+ "enumerant" : "ReadINTEL",
+ "value" : 1,
+ "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+ },
+ {
+ "enumerant" : "WriteINTEL",
+ "value" : 2,
+ "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+ },
+ {
+ "enumerant" : "ReadWriteINTEL",
+ "value" : 3,
+ "capabilities" : [ "GlobalVariableHostAccessINTEL" ]
+ }
+ ]
+ },
+ {
+ "category" : "ValueEnum",
"kind" : "FunctionParameterAttribute",
"enumerants" : [
{
"version" : "None"
},
{
+ "enumerant" : "NodeSharesPayloadLimitsWithAMDX",
+ "value" : 5019,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'Payload Array'" }
+ ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "NodeMaxPayloadsAMDX",
+ "value" : 5020,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "parameters" : [
+ { "kind" : "IdRef", "name" : "'Max number of payloads'" }
+ ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "TrackFinishWritingAMDX",
+ "value" : 5078,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "PayloadNodeNameAMDX",
+ "value" : 5091,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "parameters" : [
+ { "kind" : "LiteralString", "name" : "'Node Name'" }
+ ],
+ "version" : "None"
+ },
+ {
"enumerant" : "OverrideCoverageNV",
"value" : 5248,
"capabilities" : [ "SampleMaskOverrideCoverageNV" ],
"version" : "None"
},
{
+ "enumerant" : "InitModeINTEL",
+ "value" : 6147,
+ "parameters": [
+ { "kind" : "InitializationModeQualifier", "name" : "'Trigger'" }
+ ],
+ "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "ImplementInRegisterMapINTEL",
+ "value" : 6148,
+ "parameters": [
+ { "kind" : "LiteralInteger", "name" : "Value" }
+ ],
+ "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "HostAccessINTEL",
+ "value" : 6168,
+ "parameters": [
+ { "kind" : "HostAccessQualifier", "name" : "'Access'" },
+ { "kind" : "LiteralString", "name" : "'Name'" }
+ ],
+ "capabilities" : [ "GlobalVariableHostAccessINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "FPMaxErrorDecorationINTEL",
+ "value" : 6170,
+ "parameters" : [
+ { "kind" : "LiteralFloat", "name" : "'Max Error'" }
+ ],
+ "capabilities" : [ "FPMaxErrorINTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "LatencyControlLabelINTEL",
"value" : 6172,
"parameters" : [
"version" : "None"
},
{
+ "enumerant" : "CoalescedInputCountAMDX",
+ "value" : 5021,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "ShaderIndexAMDX",
+ "value" : 5073,
+ "capabilities" : [ "ShaderEnqueueAMDX" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "ViewportMaskNV",
"value" : 5253,
"capabilities" : [ "ShaderViewportMaskNV", "MeshShadingNV" ],
"version" : "None"
},
{
+ "enumerant" : "ShaderEnqueueAMDX",
+ "value" : 5067,
+ "capabilities" : [ "Shader" ],
+ "extensions" : [ "SPV_AMDX_shader_enqueue" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "SampleMaskOverrideCoverageNV",
"value" : 5249,
"capabilities" : [ "SampleRateShading" ],
"version" : "None"
},
{
+ "enumerant" : "CooperativeMatrixKHR",
+ "value" : 6022,
+ "extensions" : [ "SPV_KHR_cooperative_matrix" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "BitInstructions",
"value" : 6025,
"extensions" : [ "SPV_KHR_bit_instructions" ],
"version" : "None"
},
{
+ "enumerant" : "GlobalVariableFPGADecorationsINTEL",
+ "value" : 6146,
+ "extensions": [ "SPV_INTEL_global_variable_fpga_decorations" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPGAKernelAttributesv2INTEL",
"value" : 6161,
"capabilities" : [ "FPGAKernelAttributesINTEL" ],
"version" : "None"
},
{
+ "enumerant" : "GlobalVariableHostAccessINTEL",
+ "value" : 6167,
+ "extensions": [ "SPV_INTEL_global_variable_host_access" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "FPMaxErrorINTEL",
+ "value" : 6169,
+ "extensions" : [ "SPV_INTEL_fp_max_error" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPGALatencyControlINTEL",
"value" : 6171,
"extensions" : [ "SPV_INTEL_fpga_latency_control" ],
]
},
{
+ "category" : "BitEnum",
+ "kind" : "CooperativeMatrixOperands",
+ "enumerants" : [
+ {
+ "enumerant" : "NoneKHR",
+ "value" : "0x0000",
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MatrixASignedComponentsKHR",
+ "value" : "0x0001",
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MatrixBSignedComponentsKHR",
+ "value" : "0x0002",
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MatrixCSignedComponentsKHR",
+ "value" : "0x0004",
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MatrixResultSignedComponentsKHR",
+ "value" : "0x0008",
+ "version" : "None"
+ },
+ {
+ "enumerant" : "SaturatingAccumulationKHR",
+ "value" : "0x0010",
+ "version" : "None"
+ }
+ ]
+ },
+ {
+ "category" : "ValueEnum",
+ "kind" : "CooperativeMatrixLayout",
+ "enumerants" : [
+ {
+ "enumerant" : "RowMajorKHR",
+ "value" : 0,
+ "version" : "None"
+ },
+ {
+ "enumerant" : "ColumnMajorKHR",
+ "value" : 1,
+ "version" : "None"
+ }
+ ]
+ },
+ {
+ "category" : "ValueEnum",
+ "kind" : "CooperativeMatrixUse",
+ "enumerants" : [
+ {
+ "enumerant" : "MatrixAKHR",
+ "value" : 0,
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MatrixBKHR",
+ "value" : 1,
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MatrixAccumulatorKHR",
+ "value" : 2,
+ "version" : "None"
+ }
+ ]
+ },
+ {
+ "category" : "ValueEnum",
+ "kind" : "InitializationModeQualifier",
+ "enumerants" : [
+ {
+ "enumerant" : "InitOnDeviceReprogramINTEL",
+ "value" : 0,
+ "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "InitOnDeviceResetINTEL",
+ "value" : 1,
+ "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
+ "version" : "None"
+ }
+ ]
+ },
+ {
"category" : "Id",
"kind" : "IdResultType",
"doc" : "Reference to an <id> representing the result's type of the enclosing instruction"
SpvSourceLanguageHLSL = 5,
SpvSourceLanguageCPP_for_OpenCL = 6,
SpvSourceLanguageSYCL = 7,
+ SpvSourceLanguageHERO_C = 8,
+ SpvSourceLanguageNZSL = 9,
+ SpvSourceLanguageWGSL = 10,
SpvSourceLanguageMax = 0x7fffffff,
} SpvSourceLanguage;
SpvExecutionModeRoundingModeRTZ = 4463,
SpvExecutionModeEarlyAndLateFragmentTestsAMD = 5017,
SpvExecutionModeStencilRefReplacingEXT = 5027,
+ SpvExecutionModeCoalescingAMDX = 5069,
+ SpvExecutionModeMaxNodeRecursionAMDX = 5071,
+ SpvExecutionModeStaticNumWorkgroupsAMDX = 5072,
+ SpvExecutionModeShaderIndexAMDX = 5073,
+ SpvExecutionModeMaxNumWorkgroupsAMDX = 5077,
SpvExecutionModeStencilRefUnchangedFrontAMD = 5079,
SpvExecutionModeStencilRefGreaterFrontAMD = 5080,
SpvExecutionModeStencilRefLessFrontAMD = 5081,
SpvStorageClassImage = 11,
SpvStorageClassStorageBuffer = 12,
SpvStorageClassTileImageEXT = 4172,
+ SpvStorageClassNodePayloadAMDX = 5068,
+ SpvStorageClassNodeOutputPayloadAMDX = 5076,
SpvStorageClassCallableDataKHR = 5328,
SpvStorageClassCallableDataNV = 5328,
SpvStorageClassIncomingCallableDataKHR = 5329,
SpvImageChannelDataTypeFloat = 14,
SpvImageChannelDataTypeUnormInt24 = 15,
SpvImageChannelDataTypeUnormInt101010_2 = 16,
+ SpvImageChannelDataTypeUnsignedIntRaw10EXT = 19,
+ SpvImageChannelDataTypeUnsignedIntRaw12EXT = 20,
SpvImageChannelDataTypeMax = 0x7fffffff,
} SpvImageChannelDataType;
SpvDecorationWeightTextureQCOM = 4487,
SpvDecorationBlockMatchTextureQCOM = 4488,
SpvDecorationExplicitInterpAMD = 4999,
+ SpvDecorationNodeSharesPayloadLimitsWithAMDX = 5019,
+ SpvDecorationNodeMaxPayloadsAMDX = 5020,
+ SpvDecorationTrackFinishWritingAMDX = 5078,
+ SpvDecorationPayloadNodeNameAMDX = 5091,
SpvDecorationOverrideCoverageNV = 5248,
SpvDecorationPassthroughNV = 5250,
SpvDecorationViewportRelativeNV = 5252,
SpvDecorationSingleElementVectorINTEL = 6085,
SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
SpvDecorationMediaBlockIOINTEL = 6140,
+ SpvDecorationInitModeINTEL = 6147,
+ SpvDecorationImplementInRegisterMapINTEL = 6148,
+ SpvDecorationHostAccessINTEL = 6168,
+ SpvDecorationFPMaxErrorDecorationINTEL = 6170,
SpvDecorationLatencyControlLabelINTEL = 6172,
SpvDecorationLatencyControlConstraintINTEL = 6173,
SpvDecorationConduitKernelArgumentINTEL = 6175,
SpvBuiltInBaryCoordSmoothSampleAMD = 4997,
SpvBuiltInBaryCoordPullModelAMD = 4998,
SpvBuiltInFragStencilRefEXT = 5014,
+ SpvBuiltInCoalescedInputCountAMDX = 5021,
+ SpvBuiltInShaderIndexAMDX = 5073,
SpvBuiltInViewportMaskNV = 5253,
SpvBuiltInSecondaryPositionNV = 5257,
SpvBuiltInSecondaryViewportMaskNV = 5258,
SpvCapabilityImageReadWriteLodAMD = 5015,
SpvCapabilityInt64ImageEXT = 5016,
SpvCapabilityShaderClockKHR = 5055,
+ SpvCapabilityShaderEnqueueAMDX = 5067,
SpvCapabilitySampleMaskOverrideCoverageNV = 5249,
SpvCapabilityGeometryShaderPassthroughNV = 5251,
SpvCapabilityShaderViewportIndexLayerEXT = 5254,
SpvCapabilityDotProduct = 6019,
SpvCapabilityDotProductKHR = 6019,
SpvCapabilityRayCullMaskKHR = 6020,
+ SpvCapabilityCooperativeMatrixKHR = 6022,
SpvCapabilityBitInstructions = 6025,
SpvCapabilityGroupNonUniformRotateKHR = 6026,
SpvCapabilityAtomicFloat32AddEXT = 6033,
SpvCapabilityDebugInfoModuleINTEL = 6114,
SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141,
+ SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6146,
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
+ SpvCapabilityGlobalVariableHostAccessINTEL = 6167,
+ SpvCapabilityFPMaxErrorINTEL = 6169,
SpvCapabilityFPGALatencyControlINTEL = 6171,
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvPackedVectorFormatMax = 0x7fffffff,
} SpvPackedVectorFormat;
+typedef enum SpvCooperativeMatrixOperandsShift_ {
+ SpvCooperativeMatrixOperandsMatrixASignedComponentsKHRShift = 0,
+ SpvCooperativeMatrixOperandsMatrixBSignedComponentsKHRShift = 1,
+ SpvCooperativeMatrixOperandsMatrixCSignedComponentsKHRShift = 2,
+ SpvCooperativeMatrixOperandsMatrixResultSignedComponentsKHRShift = 3,
+ SpvCooperativeMatrixOperandsSaturatingAccumulationKHRShift = 4,
+ SpvCooperativeMatrixOperandsMax = 0x7fffffff,
+} SpvCooperativeMatrixOperandsShift;
+
+typedef enum SpvCooperativeMatrixOperandsMask_ {
+ SpvCooperativeMatrixOperandsMaskNone = 0,
+ SpvCooperativeMatrixOperandsMatrixASignedComponentsKHRMask = 0x00000001,
+ SpvCooperativeMatrixOperandsMatrixBSignedComponentsKHRMask = 0x00000002,
+ SpvCooperativeMatrixOperandsMatrixCSignedComponentsKHRMask = 0x00000004,
+ SpvCooperativeMatrixOperandsMatrixResultSignedComponentsKHRMask = 0x00000008,
+ SpvCooperativeMatrixOperandsSaturatingAccumulationKHRMask = 0x00000010,
+} SpvCooperativeMatrixOperandsMask;
+
+typedef enum SpvCooperativeMatrixLayout_ {
+ SpvCooperativeMatrixLayoutRowMajorKHR = 0,
+ SpvCooperativeMatrixLayoutColumnMajorKHR = 1,
+ SpvCooperativeMatrixLayoutMax = 0x7fffffff,
+} SpvCooperativeMatrixLayout;
+
+typedef enum SpvCooperativeMatrixUse_ {
+ SpvCooperativeMatrixUseMatrixAKHR = 0,
+ SpvCooperativeMatrixUseMatrixBKHR = 1,
+ SpvCooperativeMatrixUseMatrixAccumulatorKHR = 2,
+ SpvCooperativeMatrixUseMax = 0x7fffffff,
+} SpvCooperativeMatrixUse;
+
+typedef enum SpvInitializationModeQualifier_ {
+ SpvInitializationModeQualifierInitOnDeviceReprogramINTEL = 0,
+ SpvInitializationModeQualifierInitOnDeviceResetINTEL = 1,
+ SpvInitializationModeQualifierMax = 0x7fffffff,
+} SpvInitializationModeQualifier;
+
+typedef enum SpvHostAccessQualifier_ {
+ SpvHostAccessQualifierNoneINTEL = 0,
+ SpvHostAccessQualifierReadINTEL = 1,
+ SpvHostAccessQualifierWriteINTEL = 2,
+ SpvHostAccessQualifierReadWriteINTEL = 3,
+ SpvHostAccessQualifierMax = 0x7fffffff,
+} SpvHostAccessQualifier;
+
typedef enum SpvOp_ {
SpvOpNop = 0,
SpvOpUndef = 1,
SpvOpUDotAccSatKHR = 4454,
SpvOpSUDotAccSat = 4455,
SpvOpSUDotAccSatKHR = 4455,
+ SpvOpTypeCooperativeMatrixKHR = 4456,
+ SpvOpCooperativeMatrixLoadKHR = 4457,
+ SpvOpCooperativeMatrixStoreKHR = 4458,
+ SpvOpCooperativeMatrixMulAddKHR = 4459,
+ SpvOpCooperativeMatrixLengthKHR = 4460,
SpvOpTypeRayQueryKHR = 4472,
SpvOpRayQueryInitializeKHR = 4473,
SpvOpRayQueryTerminateKHR = 4474,
SpvOpFragmentMaskFetchAMD = 5011,
SpvOpFragmentFetchAMD = 5012,
SpvOpReadClockKHR = 5056,
+ SpvOpFinalizeNodePayloadsAMDX = 5075,
+ SpvOpFinishWritingNodePayloadAMDX = 5078,
+ SpvOpInitializeNodePayloadsAMDX = 5090,
SpvOpHitObjectRecordHitMotionNV = 5249,
SpvOpHitObjectRecordHitWithIndexMotionNV = 5250,
SpvOpHitObjectRecordMissMotionNV = 5251,
case SpvOpSDotAccSat: *hasResult = true; *hasResultType = true; break;
case SpvOpUDotAccSat: *hasResult = true; *hasResultType = true; break;
case SpvOpSUDotAccSat: *hasResult = true; *hasResultType = true; break;
+ case SpvOpTypeCooperativeMatrixKHR: *hasResult = true; *hasResultType = false; break;
+ case SpvOpCooperativeMatrixLoadKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpCooperativeMatrixStoreKHR: *hasResult = false; *hasResultType = false; break;
+ case SpvOpCooperativeMatrixMulAddKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpCooperativeMatrixLengthKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpTypeRayQueryKHR: *hasResult = true; *hasResultType = false; break;
case SpvOpRayQueryInitializeKHR: *hasResult = false; *hasResultType = false; break;
case SpvOpRayQueryTerminateKHR: *hasResult = false; *hasResultType = false; break;
case SpvOpFragmentMaskFetchAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpFragmentFetchAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpReadClockKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpFinalizeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
+ case SpvOpFinishWritingNodePayloadAMDX: *hasResult = true; *hasResultType = true; break;
+ case SpvOpInitializeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
case SpvOpHitObjectRecordHitMotionNV: *hasResult = false; *hasResultType = false; break;
case SpvOpHitObjectRecordHitWithIndexMotionNV: *hasResult = false; *hasResultType = false; break;
case SpvOpHitObjectRecordMissMotionNV: *hasResult = false; *hasResultType = false; break;