ARM: mach-sc: remove build warnings 23/158523/1
authorSeung-Woo Kim <sw0312.kim@samsung.com>
Wed, 1 Nov 2017 11:41:44 +0000 (20:41 +0900)
committerSeung-Woo Kim <sw0312.kim@samsung.com>
Wed, 1 Nov 2017 11:41:48 +0000 (20:41 +0900)
Remove build warnings with explict type conversion, modified
function pointers, and modified print formats.

Change-Id: I5f173bb04d014e1c93ea56e62374466a05e5101e
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
arch/arm/mach-sc/mach-scx35-dt.c
arch/arm/mach-sc/syssleep.c

index 41ee3ab..29f6c74 100644 (file)
@@ -46,6 +46,9 @@ extern int __init sci_regulator_init(void);
 extern int __init sprd_ramconsole_init(void);
 #endif
 
+#define sprd_readl(addr)       __raw_readl((void __iomem __force *)(addr))
+#define sprd_writel(val, addr) __raw_writel(val, (void __iomem __force *)(addr))
+
 struct class *sec_class;
 EXPORT_SYMBOL(sec_class);
 int current_cable_type = POWER_SUPPLY_TYPE_BATTERY;
@@ -115,7 +118,7 @@ int __init __clock_init_early(void)
 
 static inline int      __sci_get_chip_id(void)
 {
-       return __raw_readl(CHIP_ID_LOW_REG);
+       return sprd_readl(CHIP_ID_LOW_REG);
 }
 const struct of_device_id of_sprd_default_bus_match_table[] = {
        { .compatible = "simple-bus", },
@@ -149,8 +152,8 @@ do {                                                        \
                io_addr_sprd.id.length =                \
                        resource_size(&res);            \
                io_addr_sprd.id.vaddr =                 \
-               ioremap_nocache(res.start, io_addr_sprd.id.length);\
-               pr_debug("sprd io map: phys=%08x virt=%08x size=%08x\n", \
+               (unsigned long)ioremap_nocache(res.start, io_addr_sprd.id.length);\
+               pr_debug("sprd io map: phys=%08lx virt=%08lx size=%08lx\n", \
        io_addr_sprd.id.paddr, io_addr_sprd.id.vaddr, io_addr_sprd.id.length);\
        }                                               \
 } while (0)
@@ -163,7 +166,7 @@ do {                                                        \
                io_addr_sprd.id.length =                \
                        resource_size(&res);            \
                io_addr_sprd.id.vaddr =                 \
-               ioremap_nocache(res.start, io_addr_sprd.id.length);\
+               (unsigned long)ioremap_nocache(res.start, io_addr_sprd.id.length);\
                pr_debug("sprd io map: phys=%16lx virt=%16lx size=%16lx\n", \
        io_addr_sprd.id.paddr, io_addr_sprd.id.vaddr, io_addr_sprd.id.length);\
        }                                               \
@@ -221,7 +224,7 @@ static void __init sc8830_init_machine(void)
         if (IS_ERR(sec_class)) {
                pr_err("Failed to create class(sec)!\n");
                printk("Failed create class \n");
-               return PTR_ERR(sec_class);
+               return;
        }
        platform_device_register(&bcm47522_gps);
 }
@@ -267,31 +270,31 @@ void __init sprd_init_before_irq(void)
 }
 static void __init sc8830_pmu_init(void)
 {
-       __raw_writel(__raw_readl(REG_PMU_APB_PD_MM_TOP_CFG)
+       sprd_writel(sprd_readl(REG_PMU_APB_PD_MM_TOP_CFG)
                        & ~(BIT_PD_MM_TOP_FORCE_SHUTDOWN),
                        REG_PMU_APB_PD_MM_TOP_CFG);
 
-       __raw_writel(__raw_readl(REG_PMU_APB_PD_GPU_TOP_CFG)
+       sprd_writel(sprd_readl(REG_PMU_APB_PD_GPU_TOP_CFG)
                        & ~(BIT_PD_GPU_TOP_FORCE_SHUTDOWN),
                        REG_PMU_APB_PD_GPU_TOP_CFG);
 
-       __raw_writel(__raw_readl(REG_AON_APB_APB_EB0) | BIT_MM_EB | BIT_GPU_EB, 
+       sprd_writel(sprd_readl(REG_AON_APB_APB_EB0) | BIT_MM_EB | BIT_GPU_EB, 
                REG_AON_APB_APB_EB0);
 
        /* only need open this power init in Tshark2 */
 #if defined(CONFIG_ARCH_SCX30G2)
-       __raw_writel(__raw_readl(REG_AON_APB_APB_EB1) | BIT_CODEC_EB, 
+       sprd_writel(sprd_readl(REG_AON_APB_APB_EB1) | BIT_CODEC_EB, 
                 REG_AON_APB_APB_EB1);
 #endif
 
-       __raw_writel(__raw_readl(REG_MM_AHB_AHB_EB) | BIT_MM_CKG_EB,
+       sprd_writel(sprd_readl(REG_MM_AHB_AHB_EB) | BIT_MM_CKG_EB,
                        REG_MM_AHB_AHB_EB);
 
-       __raw_writel(__raw_readl(REG_MM_AHB_GEN_CKG_CFG)
+       sprd_writel(sprd_readl(REG_MM_AHB_GEN_CKG_CFG)
                        | BIT_MM_MTX_AXI_CKG_EN | BIT_MM_AXI_CKG_EN,
                        REG_MM_AHB_GEN_CKG_CFG);
 
-       __raw_writel(__raw_readl(REG_MM_CLK_MM_AHB_CFG) | 0x3,
+       sprd_writel(sprd_readl(REG_MM_CLK_MM_AHB_CFG) | 0x3,
                        REG_MM_CLK_MM_AHB_CFG);
 }
 
index 52833f3..dd4b2e4 100755 (executable)
 #include <soc/sprd/sci_glb_regs.h>
 #include <soc/sprd/hardware.h>
 
-static int syssleep_read_proc(char *page, char **start, off_t off,
-                         int count, int *eof, void *data)
+static ssize_t syssleep_read_proc(struct file *file, char __user *buffer,
+                                 size_t count, loff_t *data)
 {
        return 0;
 }
 
-static int syssleep_write_proc(struct file *file, const char __user *buffer,
-                          unsigned long count, void *data)
+static ssize_t syssleep_write_proc(struct file *file, const char __user *buffer,
+                                  size_t count, loff_t *data)
 {
 #if 0
     sci_glb_write(REG_PMU_APB_PD_CP0_ARM9_0_CFG, BIT(24) | BIT(25), -1UL);