net: hns3: add ethtool parameter check for CQE/EQE mode

For DEVICE_VERSION_V2, the hardware does not support the CQE mode.
So add capability bit for coalesce CQE mode and add parameter check
for it in ethtool.

Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
index 79c64f4..8a3a446 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
@@ -96,6 +96,7 @@ enum HNAE3_DEV_CAP_BITS {
        HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
        HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
        HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
+       HNAE3_DEV_SUPPORT_CQ_B,
 };
 
 #define hnae3_dev_fd_supported(hdev) \
@@ -155,6 +156,9 @@ enum HNAE3_DEV_CAP_BITS {
 #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
        test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
 
+#define hnae3_ae_dev_cq_supported(ae_dev) \
+       test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
+
 enum HNAE3_PF_CAP_BITS {
        HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
 };

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
index c15ca71..c8b151d 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
@@ -149,6 +149,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
        {HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B,
         HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
        {HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
+       {HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},
 };
 
 static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
@@ -160,6 +161,7 @@ static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
        {HCLGE_COMM_CAP_QB_B, HNAE3_DEV_SUPPORT_QB_B},
        {HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},
        {HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
+       {HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},
 };
 
 static void

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
index 876650e..7a7d4cf 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
@@ -338,6 +338,7 @@ enum HCLGE_COMM_CAP_BITS {
        HCLGE_COMM_CAP_PAUSE_B = 14,
        HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,
        HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,
+       HCLGE_COMM_CAP_CQ_B = 18,
 };
 
 enum HCLGE_COMM_API_CAP_BITS {

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index 14dc12c..7e9f9da 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -5159,10 +5159,7 @@ static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
                        priv->tqp_vector[i].rx_group.dim.mode = mode;
        }
 
-       /* only device version above V3(include V3), GL can switch CQ/EQ
-        * period mode.
-        */
-       if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
+       if (hnae3_ae_dev_cq_supported(ae_dev)) {
                u32 new_mode;
                u64 reg;
 

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
index 9f4111f..8663ba5 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
@@ -1415,11 +1415,33 @@ static int hns3_check_ql_coalesce_param(struct net_device *netdev,
        return 0;
 }
 
-static int hns3_check_coalesce_para(struct net_device *netdev,
-                                   struct ethtool_coalesce *cmd)
+static int
+hns3_check_cqe_coalesce_param(struct net_device *netdev,
+                             struct kernel_ethtool_coalesce *kernel_coal)
+{
+       struct hnae3_handle *handle = hns3_get_handle(netdev);
+       struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+
+       if ((kernel_coal->use_cqe_mode_tx || kernel_coal->use_cqe_mode_rx) &&
+           !hnae3_ae_dev_cq_supported(ae_dev)) {
+               netdev_err(netdev, "coalesced cqe mode is not supported\n");
+               return -EOPNOTSUPP;
+       }
+
+       return 0;
+}
+
+static int
+hns3_check_coalesce_para(struct net_device *netdev,
+                        struct ethtool_coalesce *cmd,
+                        struct kernel_ethtool_coalesce *kernel_coal)
 {
        int ret;
 
+       ret = hns3_check_cqe_coalesce_param(netdev, kernel_coal);
+       if (ret)
+               return ret;
+
        ret = hns3_check_gl_coalesce_para(netdev, cmd);
        if (ret) {
                netdev_err(netdev,
@@ -1494,7 +1516,7 @@ static int hns3_set_coalesce(struct net_device *netdev,
        if (hns3_nic_resetting(netdev))
                return -EBUSY;
 
-       ret = hns3_check_coalesce_para(netdev, cmd);
+       ret = hns3_check_coalesce_para(netdev, cmd, kernel_coal);
        if (ret)
                return ret;