mxs: Explain why some mx23 DDR registers are not configured
authorFabio Estevam <fabio.estevam@freescale.com>
Sun, 5 May 2013 16:11:59 +0000 (16:11 +0000)
committerStefano Babic <sbabic@denx.de>
Mon, 6 May 2013 07:55:52 +0000 (09:55 +0200)
Put an explanation in the source code as to why some DDR registers do not
need to be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c

index 4ed197b..3902406 100644 (file)
@@ -127,6 +127,15 @@ static void initialize_dram_values(void)
 
        mxs_adjust_memory_params(dram_vals);
 
+       /*
+        * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+        * per FSL bootlets code.
+        *
+        * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+        * "reserved".
+        * HW_DRAM_CTL8 is setup as the last element.
+        * So skip the initialization of these HW_DRAM_CTL registers.
+        */
        for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
                if (i == 8 || i == 27 || i == 28 || i == 35)
                        continue;