S/390: Rename cpu facility vec to vx.

gcc/ChangeLog:

2017-03-24  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.md: Rename the cpu facilty vec to vx throughout
	the file.

From-SVN: r246444

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e3fcfbe..b11b508 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2017-03-24  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
+       * config/s390/s390.md: Rename the cpu facilty vec to vx throughout
+       the file.
+
+2017-03-24  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
        PR target/79893
        * config/s390/s390-c.c (s390_adjust_builtin_arglist): Issue an
        error if the boundary argument is not constant.

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 19daf31..660b5f9 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -482,7 +482,7 @@
   (const (symbol_ref "s390_tune_attr")))
 
 (define_attr "cpu_facility"
-  "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec,z13"
+  "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13"
   (const_string "standard"))
 
 (define_attr "enabled" ""
@@ -525,7 +525,7 @@
               (match_test "TARGET_ZEC12"))
         (const_int 1)
 
-         (and (eq_attr "cpu_facility" "vec")
+         (and (eq_attr "cpu_facility" "vx")
               (match_test "TARGET_VX"))
         (const_int 1)
 
@@ -1484,7 +1484,7 @@
    #"
   [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
    (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
-   (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
+   (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")])
 
 (define_split
   [(set (match_operand:TI 0 "nonimmediate_operand" "")
@@ -1720,7 +1720,7 @@
                      *,*,*,*,*,*,*")
    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
                              z10,*,*,*,*,*,longdisp,*,longdisp,
-                             z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
+                             z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx")
    (set_attr "z10prop" "z10_fwd_A1,
                         z10_fwd_E1,
                         z10_fwd_E1,
@@ -2001,7 +2001,7 @@
                      *,
                      *,*,*,*,*,*,*")
    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
-                             vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
+                             vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx")
    (set_attr "z10prop" "z10_fwd_A1,
                         z10_fwd_E1,
                         z10_fwd_E1,
@@ -2049,7 +2049,7 @@
    (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
    (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
                         z10_super,*,*")
-   (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
+   (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*")
 ])
 
 (define_peephole2
@@ -2183,7 +2183,7 @@
    vsteh\t%v1,%0,0"
   [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
    (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
-   (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vec,vec,vec,vec,vec,vec")
+   (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx")
    (set_attr "z10prop" "z10_fr_E1,
                        z10_fwd_A1,
                        z10_super_E1,
@@ -2248,7 +2248,7 @@
    vsteb\t%v1,%0,0"
   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
    (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
-   (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vec,vec,vec,vec,vec,vec")
+   (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx")
    (set_attr "z10prop" "z10_fr_E1,
                         z10_fwd_A1,
                         z10_super_E1,
@@ -2476,7 +2476,7 @@
    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
-   (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
+   (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx")])
 
 (define_insn "*mov<mode>_64"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T,v,v,R")
@@ -2502,7 +2502,7 @@
    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
-   (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vec,vec,vec")])
+   (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx")])
 
 (define_insn "*mov<mode>_31"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
@@ -2606,7 +2606,7 @@
    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
-   (set_attr "cpu_facility" "z196,vec,*,vec,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vec,vec,vec,vec,vec,vec")])
+   (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")])
 
 ;
 ; movcc instruction pattern
@@ -4983,7 +4983,7 @@
    wcdgb\t%v0,%v1,0,0"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "type"         "itof<mode>" )
-   (set_attr "cpu_facility" "*,vec")
+   (set_attr "cpu_facility" "*,vx")
    (set_attr "enabled"      "*,<DFDI>")])
 
 ; cxfbr, cdfbr, cefbr
@@ -5048,7 +5048,7 @@
                        ; According to BFP rounding mode
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "type"         "ftruncdf")
-   (set_attr "cpu_facility" "*,vec")])
+   (set_attr "cpu_facility" "*,vx")])
 
 ;
 ; trunctf(df|sf)2 instruction pattern(s).
@@ -5767,7 +5767,7 @@
    wfadb\t%v0,%v1,%v2"
   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fsimp<mode>")
-   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "cpu_facility" "*,*,*,vx")
    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
@@ -6198,7 +6198,7 @@
    wfsdb\t%v0,%v1,%v2"
   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fsimp<mode>")
-   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "cpu_facility" "*,*,*,vx")
    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
@@ -6628,7 +6628,7 @@
    wfmdb\t%v0,%v1,%v2"
   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fmul<mode>")
-   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "cpu_facility" "*,*,*,vx")
    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 ; madbr, maebr, maxb, madb, maeb
@@ -6644,7 +6644,7 @@
    wfmadb\t%v0,%v1,%v2,%v3"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fmadd<mode>")
-   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "cpu_facility" "*,*,vx")
    (set_attr "enabled"      "*,*,<DFDI>")])
 
 ; msxbr, msdbr, msebr, msxb, msdb, mseb
@@ -6660,7 +6660,7 @@
    wfmsdb\t%v0,%v1,%v2,%v3"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fmadd<mode>")
-   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "cpu_facility" "*,*,vx")
    (set_attr "enabled"      "*,*,<DFDI>")])
 
 ;;
@@ -7104,7 +7104,7 @@
    wfddb\t%v0,%v1,%v2"
   [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fdiv<mode>")
-   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "cpu_facility" "*,*,*,vx")
    (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 
@@ -8353,7 +8353,7 @@
    lc<xde>br\t%0,%1
    wflcdb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
-   (set_attr "cpu_facility" "*,vec")
+   (set_attr "cpu_facility" "*,vx")
    (set_attr "type"         "fsimp<mode>,*")
    (set_attr "enabled"      "*,<DFDI>")])
 
@@ -8476,7 +8476,7 @@
     lp<xde>br\t%0,%1
     wflpdb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
-   (set_attr "cpu_facility" "*,vec")
+   (set_attr "cpu_facility" "*,vx")
    (set_attr "type"         "fsimp<mode>,*")
    (set_attr "enabled"      "*,<DFDI>")])
 
@@ -8592,7 +8592,7 @@
    ln<xde>br\t%0,%1
    wflndb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
-   (set_attr "cpu_facility" "*,vec")
+   (set_attr "cpu_facility" "*,vx")
    (set_attr "type"         "fsimp<mode>,*")
    (set_attr "enabled"      "*,<DFDI>")])
 
@@ -8615,7 +8615,7 @@
    wfsqdb\t%v0,%v1"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fsqrt<mode>")
-   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "cpu_facility" "*,*,vx")
    (set_attr "enabled"      "*,<DSF>,<DFDI>")])