drm/amd/display/dc: fix azalia workaround sw implementation bug
authorhersen wu <hersenxs.wu@amd.com>
Sat, 1 Jun 2019 22:23:38 +0000 (18:23 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Sat, 22 Jun 2019 14:34:07 +0000 (09:34 -0500)
caller of pp_nv_set_pme_wa_enable pass incorrect pp_smu:
dc->res_pool->pp_smu. it should be dc->res_pool->pp_smu->nv_funcs.pp_smu.
with incorrect input, pp->dm = NULL. This causes system crash.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

index e7cc58e..edda426 100644 (file)
@@ -969,10 +969,10 @@ static void set_pme_wa_enable_by_version(struct dc *dc)
 
        if (pp_smu) {
                if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable)
-                       pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx));
+                       pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->rv_funcs.pp_smu));
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
                else if (pp_smu->ctx.ver == PP_SMU_VER_NV && pp_smu->nv_funcs.set_pme_wa_enable)
-                       pp_smu->nv_funcs.set_pme_wa_enable(&(pp_smu->ctx));
+                       pp_smu->nv_funcs.set_pme_wa_enable(&(pp_smu->nv_funcs.pp_smu));
 #endif
        }
 }