--- /dev/null
+/*
+ * Copyright (c) 2022 Samsung Electronics Co., Ltd.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <gtest/gtest.h>
+#include <gmock/gmock.h>
+
+#include <hal/hal-common.h>
+#include <hal/hal-common-interface.h>
+
+#include "hal-power.h"
+#include "hal-power-interface.h"
+
+#define ARRAY_SIZE(name) (int)(sizeof(name)/sizeof(name[0]))
+
+#define MAX_BUFF 255
+#define DEFAULT_FREQ 1000000
+#define DEFAULT_FAULT_AROUND_BYTES 4096
+
+class HalApiPowerTest : public testing::Test {
+ public:
+ HalApiPowerTest() {}
+ virtual ~HalApiPowerTest() {}
+ virtual void SetUp() {}
+ virtual void TearDown() {}
+};
+
+static int resources[] = {
+ PASS_RESOURCE_CPU_ID,
+ PASS_RESOURCE_BUS_ID,
+ PASS_RESOURCE_GPU_ID,
+ PASS_RESOURCE_MEMORY_ID,
+};
+
+static int test_begin(void)
+{
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(resources); i++) {
+ ret = hal_power_get_backend(resources[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int test_end(void)
+{
+ int ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(resources); i++) {
+ ret = hal_power_put_backend();
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+TEST(HalApiPowerTest, hal_power_get_backend_with_cpu_id) {
+ int ret = hal_power_get_backend(PASS_RESOURCE_CPU_ID);
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_put_backend();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_get_backend_with_bus_id) {
+ int ret = hal_power_get_backend(PASS_RESOURCE_BUS_ID);
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_put_backend();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_get_backend_with_gpu_id) {
+ int ret = hal_power_get_backend(PASS_RESOURCE_GPU_ID);
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_put_backend();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_get_backend_with_memory_id) {
+ int ret = hal_power_get_backend(PASS_RESOURCE_MEMORY_ID);
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_put_backend();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_get_backend_with_nonstandard_id) {
+ int ret = hal_power_get_backend(PASS_RESOURCE_NONSTANDARD_ID);
+ EXPECT_TRUE(ret != 0);
+
+ ret = hal_power_put_backend();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_curr_governor_valid) {
+ int ret;
+ char governor[MAX_BUFF];
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_CPU_ID, res_name, governor);
+ EXPECT_TRUE(ret == 0);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_BUS_ID, res_name, governor);
+ EXPECT_TRUE(ret == 0);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_GPU_ID, res_name, governor);
+ EXPECT_TRUE(ret == 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_curr_governor_invalid) {
+ int ret;
+ char governor[MAX_BUFF];
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_CPU_ID, NULL, governor);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_CPU_ID, res_name, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_BUS_ID, NULL, governor);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_BUS_ID, res_name, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_GPU_ID, NULL, governor);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_GPU_ID, res_name, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_MEMORY_ID, res_name, governor);
+ EXPECT_TRUE(ret == -EPERM);
+ ret = hal_power_dvfs_get_curr_governor(PASS_RESOURCE_NONSTANDARD_ID, res_name, governor);
+ EXPECT_TRUE(ret == -EPERM);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_curr_freq_valid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_CPU_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_BUS_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_GPU_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_curr_freq_invalid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_UNKNOWN, res_name);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_UNKNOWN, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_CPU_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_BUS_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_GPU_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_MEMORY_ID, res_name);
+ EXPECT_TRUE(ret == -EPERM);
+ ret = hal_power_dvfs_get_curr_freq(PASS_RESOURCE_NONSTANDARD_ID, res_name);
+ EXPECT_TRUE(ret == -EPERM);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_min_freq_valid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_CPU_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_BUS_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_GPU_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_min_freq_invalid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_UNKNOWN, res_name);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_UNKNOWN, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_CPU_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_BUS_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_GPU_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_MEMORY_ID, res_name);
+ EXPECT_TRUE(ret == -EPERM);
+ ret = hal_power_dvfs_get_min_freq(PASS_RESOURCE_NONSTANDARD_ID, res_name);
+ EXPECT_TRUE(ret == -EPERM);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_max_freq_valid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_CPU_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_BUS_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_GPU_ID, res_name);
+ EXPECT_TRUE(ret > 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_get_max_freq_invalid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_UNKNOWN, res_name);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_UNKNOWN, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_CPU_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_BUS_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_GPU_ID, NULL);
+ EXPECT_TRUE(ret == -EINVAL);
+
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_MEMORY_ID, res_name);
+ EXPECT_TRUE(ret == -EPERM);
+ ret = hal_power_dvfs_get_max_freq(PASS_RESOURCE_NONSTANDARD_ID, res_name);
+ EXPECT_TRUE(ret == -EPERM);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_set_min_freq_valid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_CPU_ID, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret == 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_BUS_ID, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret == 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_GPU_ID, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret == 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_set_min_freq_invalid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_UNKNOWN, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_UNKNOWN, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_UNKNOWN, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_CPU_ID, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_CPU_ID, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_BUS_ID, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_BUS_ID, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_GPU_ID, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_GPU_ID, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_MEMORY_ID, res_name, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_min_freq(PASS_RESOURCE_NONSTANDARD_ID, res_name, 0);
+ EXPECT_TRUE(ret != 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_set_max_freq_valid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_CPU_ID, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret == 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_BUS_ID, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret == 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_GPU_ID, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret == 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_dvfs_set_max_freq_invalid) {
+ int ret;
+ char res_name[] = "resource_name";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_UNKNOWN, res_name, DEFAULT_FREQ);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_UNKNOWN, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_UNKNOWN, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_CPU_ID, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_CPU_ID, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_BUS_ID, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_BUS_ID, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_GPU_ID, res_name, -1);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_GPU_ID, NULL, 0);
+ EXPECT_TRUE(ret != 0);
+
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_MEMORY_ID, res_name, 0);
+ EXPECT_TRUE(ret != 0);
+ ret = hal_power_dvfs_set_max_freq(PASS_RESOURCE_NONSTANDARD_ID, res_name, 0);
+ EXPECT_TRUE(ret != 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_memory_set_fault_around_bytes_valid) {
+ int ret;
+ char res_name[] = "memory";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_memory_set_fault_around_bytes(PASS_RESOURCE_MEMORY_ID, res_name, DEFAULT_FAULT_AROUND_BYTES);
+ EXPECT_TRUE(ret == 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}
+
+TEST(HalApiPowerTest, hal_power_memory_set_fault_around_bytes_invalid) {
+ int ret;
+ char res_name[] = "memory";
+
+ ret = test_begin();
+ EXPECT_TRUE(ret == 0);
+
+ ret = hal_power_memory_set_fault_around_bytes(PASS_RESOURCE_MEMORY_ID, res_name, 0);
+ EXPECT_TRUE(ret != 0);
+
+ ret = hal_power_memory_set_fault_around_bytes(PASS_RESOURCE_MEMORY_ID, res_name, 6000);
+ EXPECT_TRUE(ret != 0);
+
+ ret = test_end();
+ EXPECT_TRUE(ret == 0);
+}