amd: add VanGogh support

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6820>

diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h b/src/amd/addrlib/src/amdgpu_asic_addr.h
index 278c2a4..0c74673 100644 (file)
--- a/src/amd/addrlib/src/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/src/amdgpu_asic_addr.h
@@ -44,6 +44,7 @@
 #define FAMILY_AI      0x8D
 #define FAMILY_RV      0x8E
 #define FAMILY_NV      0x8F
+#define FAMILY_VGH     0x90
 
 // AMDGPU_FAMILY_IS(familyId, familyName)
 #define FAMILY_IS(f, fn)     (f == FAMILY_##fn)
@@ -101,6 +102,8 @@
 #define AMDGPU_NAVY_FLOUNDER_RANGE      0x32, 0x3C
 #define AMDGPU_DIMGREY_CAVEFISH_RANGE   0x3C, 0x46
 
+#define AMDGPU_VANGOGH_RANGE    0x01, 0xFF
+
 #define AMDGPU_EXPAND_FIX(x) x
 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
 #define AMDGPU_IN_RANGE(val, ...)   AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
@@ -151,4 +154,6 @@
 #define ASICREV_IS_NAVY_FLOUNDER(r)    ASICREV_IS(r, NAVY_FLOUNDER)
 #define ASICREV_IS_DIMGREY_CAVEFISH(r) ASICREV_IS(r, DIMGREY_CAVEFISH)
 
+#define ASICREV_IS_VANGOGH(r)          ASICREV_IS(r, VANGOGH)
+
 #endif // _AMDGPU_ASIC_ADDR_H

diff --git a/src/amd/addrlib/src/core/addrlib.cpp b/src/amd/addrlib/src/core/addrlib.cpp
index 5d99d4d..6696a97 100644 (file)
--- a/src/amd/addrlib/src/core/addrlib.cpp
+++ b/src/amd/addrlib/src/core/addrlib.cpp
@@ -226,6 +226,9 @@ ADDR_E_RETURNCODE Lib::Create(
                     case FAMILY_NV:
                         pLib = Gfx10HwlInit(&client);
                         break;
+                    case FAMILY_VGH:
+                        pLib = Gfx10HwlInit(&client);
+                        break;
                     default:
                         ADDR_ASSERT_ALWAYS();
                         break;

diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
index bc12a2c..5583ce5 100644 (file)
--- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
+++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
@@ -940,6 +940,17 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
                 m_settings.dccUnsup3DSwDis = 0;
             }
             break;
+
+        case FAMILY_VGH:
+            m_settings.isDcn2 = 1;
+
+            if (ASICREV_IS_VANGOGH(chipRevision))
+            {
+                m_settings.supportRbPlus   = 1;
+                m_settings.dccUnsup3DSwDis = 0;
+            }
+            break;
+
         default:
             ADDR_ASSERT(!"Unknown chip family");
             break;

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 468bc37..fee83ac 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -402,6 +402,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
       identify_chip(NAVY_FLOUNDER);
       identify_chip(DIMGREY_CAVEFISH);
       break;
+   case FAMILY_VGH:
+      identify_chip(VANGOGH);
+      break;
    }
 
    if (!info->name) {
@@ -713,6 +716,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
       case CHIP_NAVI14:
          pc_lines = 512;
          break;
+      case CHIP_VANGOGH:
+         pc_lines = 256;
+         break;
       case CHIP_ARCTURUS:
          break;
       default:

diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index a1395a3..cfb3f47 100644 (file)
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -106,6 +106,7 @@ enum radeon_family
    CHIP_SIENNA_CICHLID,
    CHIP_NAVY_FLOUNDER,
    CHIP_DIMGREY_CAVEFISH,
+   CHIP_VANGOGH,
    CHIP_LAST,
 };
 

diff --git a/src/amd/llvm/ac_llvm_util.c b/src/amd/llvm/ac_llvm_util.c
index 0685e98..1d47d35 100644 (file)
--- a/src/amd/llvm/ac_llvm_util.c
+++ b/src/amd/llvm/ac_llvm_util.c
@@ -177,6 +177,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
    case CHIP_SIENNA_CICHLID:
    case CHIP_NAVY_FLOUNDER:
    case CHIP_DIMGREY_CAVEFISH:
+   case CHIP_VANGOGH:
       return "gfx1030";
    default:
       return "";

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 9254367..265f3bf 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1615,6 +1615,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
    case CHIP_SIENNA_CICHLID:
    case CHIP_NAVY_FLOUNDER:
    case CHIP_DIMGREY_CAVEFISH:
+   case CHIP_VANGOGH:
       dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
       dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
       dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 4f72cb9..66c6ec4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1145,8 +1145,10 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
        !(sscreen->debug_flags & (DBG(ALWAYS_NGG_CULLING_ALL) | DBG(ALWAYS_NGG_CULLING_TESS))))
       sscreen->debug_flags |= DBG(NO_NGG_CULLING);
 
-   sscreen->use_ngg = sscreen->info.chip_class >= GFX10 && sscreen->info.family != CHIP_NAVI14 &&
-                      !(sscreen->debug_flags & DBG(NO_NGG));
+   sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) &&
+                      sscreen->info.chip_class >= GFX10 &&
+                      sscreen->info.family != CHIP_NAVI14 &&
+                      sscreen->info.has_dedicated_vram;
    sscreen->use_ngg_culling = sscreen->use_ngg && !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
    sscreen->always_use_ngg_culling_all =
       sscreen->use_ngg_culling && sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL);