return nullptr;
// Since we may modify cmp of this MBB, make sure NZCV does not live out.
- for (auto SuccBB : MBB->successors())
+ for (auto *SuccBB : MBB->successors())
if (SuccBB->isLiveIn(AArch64::NZCV))
return nullptr;
/// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
/// leads to duplicated ADRP instructions.
static bool isWorthFoldingADDlow(SDValue N) {
- for (auto Use : N->uses()) {
+ for (auto *Use : N->uses()) {
if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
Use->getOpcode() != ISD::ATOMIC_LOAD &&
Use->getOpcode() != ISD::ATOMIC_STORE)
EntryBlocks.push_back(&MF.front());
for (const LandingPadInfo &LPI : MF.getLandingPads())
EntryBlocks.push_back(LPI.LandingPadBlock);
- for (auto Entry : EntryBlocks)
+ for (auto *Entry : EntryBlocks)
insertSPToRegTaintPropagation(
*Entry, Entry->SkipPHIsLabelsAndDebug(Entry->begin()));
}
// Fixup debug intrinsics to point to the new alloca.
- for (auto DVI : Info.DbgVariableIntrinsics)
+ for (auto *DVI : Info.DbgVariableIntrinsics)
DVI->replaceVariableLocationOp(OldAI, Info.AI);
}
OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
: MCDR_DataRegionJT16);
- for (auto MBB : JTBBs) {
+ for (auto *MBB : JTBBs) {
const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
OutContext);
// Otherwise it's an offset from the dispatch instruction. Construct an
// Learn whether the last use/def of each cross-iteration register is a use or
// def. If it is a def, RegisterPressure will implicitly increase max pressure
// and we do not have to add the pressure.
- for (auto SU : ProposedSchedule)
+ for (auto *SU : ProposedSchedule)
for (ConstMIBundleOperands OperI(*SU->getInstr()); OperI.isValid();
++OperI) {
auto MO = *OperI;
bumpCrossIterationPressure(RPTracker, CrossIterationNeeds);
- for (auto SU : ProposedSchedule) {
+ for (auto *SU : ProposedSchedule) {
MachineBasicBlock::const_iterator CurInstI = SU->getInstr();
RPTracker.setPos(std::next(CurInstI));
RPTracker.recede();
return SDValue();
// Check that all the users could perform the shl themselves.
- for (auto U : N->uses()) {
+ for (auto *U : N->uses()) {
switch(U->getOpcode()) {
default:
return SDValue();
}
if (LookAtSuccessors) {
- for (auto Succ : BB->successors()) {
+ for (auto *Succ : BB->successors()) {
if (!Visited.contains(Succ) && !is_contained(Frontier, Succ))
Frontier.push_back(Succ);
}
BBUtils->adjustBBOffsetsAfter(&MF->front());
bool Changed = false;
- for (auto ML : *MLI) {
+ for (auto *ML : *MLI) {
if (ML->isOutermost())
Changed |= ProcessLoop(ML);
}
}
bool Changed = false;
// Remove the tagged DMB
- for (auto MI : ToRemove) {
+ for (auto *MI : ToRemove) {
MI->eraseFromParent();
++NumDMBsRemoved;
Changed = true;
// Record any writes that may alias a load.
const auto Size = LocationSize::beforeOrAfterPointer();
- for (auto Write : Writes) {
- for (auto Read : Loads) {
+ for (auto *Write : Writes) {
+ for (auto *Read : Loads) {
MemoryLocation ReadLoc =
MemoryLocation(Read->getPointerOperand(), Size);
if (RAWDeps.count(Dominated)) {
InstSet &WritesBefore = RAWDeps[Dominated];
- for (auto Before : WritesBefore) {
+ for (auto *Before : WritesBefore) {
// We can't move the second load backward, past a write, to merge
// with the first load.
if (Dominator->comesBefore(Before))
};
// Visit inner loops.
- for (auto Inner : *L)
+ for (auto *Inner : *L)
if (!ScanLoop(Inner))
return false;
// Remove dead instructions and now dead phis.
for (auto *II : ActiveLaneMasks)
RecursivelyDeleteTriviallyDeadInstructions(II);
- for (auto I : L->blocks())
+ for (auto *I : L->blocks())
DeleteDeadPHIs(I);
return true;
}
void BPFAbstractMemberAccess::replaceWithGEP(std::vector<CallInst *> &CallList,
uint32_t DimensionIndex,
uint32_t GEPIndex) {
- for (auto Call : CallList) {
+ for (auto *Call : CallList) {
uint32_t Dimension = 1;
if (DimensionIndex > 0)
Dimension = getConstant(Call->getArgOperand(DimensionIndex));
// addr = GEP(base, 0, gep_index)
replaceWithGEP(PreserveArrayIndexCalls, 1, 2);
replaceWithGEP(PreserveStructIndexCalls, 0, 1);
- for (auto Call : PreserveUnionIndexCalls) {
+ for (auto *Call : PreserveUnionIndexCalls) {
Call->replaceAllUsesWith(Call->getArgOperand(0));
Call->eraseFromParent();
}
std::string BaseName = "llvm.btf_type_id.";
static int Count = 0;
- for (auto Call : PreserveDITypeCalls) {
+ for (auto *Call : PreserveDITypeCalls) {
const ConstantInt *Flag = dyn_cast<ConstantInt>(Call->getArgOperand(1));
assert(Flag);
uint64_t FlagValue = Flag->getValue().getZExtValue();
for (MachineInstr &MI : llvm::reverse(*B))
Instrs.push_back(&MI);
- for (auto MI : Instrs) {
+ for (auto *MI : Instrs) {
unsigned Opc = MI->getOpcode();
// Do not touch lifetime markers. This is why the target-independent DCE
// cannot be used.
Instrs.push_back(&MI);
bool Changed = false;
- for (auto I : Instrs) {
+ for (auto *I : Instrs) {
unsigned Opc = I->getOpcode();
if (!CopyPropagation::isCopyReg(Opc, true))
continue;
for (unsigned i = 0; i < BO.size(); ++i) {
BasicBlock *B = cast<BasicBlock>(BO[i]);
- for (auto DTN : children<DomTreeNode*>(DT->getNode(B)))
+ for (auto *DTN : children<DomTreeNode *>(DT->getNode(B)))
BO.push_back(DTN->getBlock());
}
if (!DoInsertAtI1 && DbgMItoMove.size() != 0) {
// Insert debug instructions at the new location before I2.
MachineBasicBlock *BB = InsertPt->getParent();
- for (auto NewMI : DbgMItoMove) {
+ for (auto *NewMI : DbgMItoMove) {
// If iterator MI is pointing to DEBUG_VAL, make sure
// MI now points to next relevant instruction.
if (NewMI == MI)
if (MI.getOpcode() == Hexagon::PS_alloca)
AdjustRegs.push_back(&MI);
- for (auto MI : AdjustRegs) {
+ for (auto *MI : AdjustRegs) {
assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
expandAlloca(MI, HII, SP, MaxCF);
MI->eraseFromParent();
void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) {
SelectionDAG &DAG = *CurDAG;
- for (auto I : Nodes) {
+ for (auto *I : Nodes) {
if (I->getOpcode() != ISD::OR)
continue;
void HexagonDAGToDAGISel::ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes) {
SelectionDAG &DAG = *CurDAG;
- for (auto I : Nodes) {
+ for (auto *I : Nodes) {
if (I->getOpcode() != ISD::STORE)
continue;
return true;
// If any of the block's successors is a landing pad, this could be a
// throwing call.
- for (auto I : MBB->successors())
+ for (auto *I : MBB->successors())
if (I->isEHPad())
return true;
}
auto *BB = cast<Instruction>(Out)->getParent();
bool HadPhi = false;
- for (auto U : Out->users()) {
+ for (auto *U : Out->users()) {
auto *I = dyn_cast<Instruction>(&*U);
if (I == nullptr || I->getParent() != BB)
continue;
continue;
if (!Worklist.count(&In) && In.mayHaveSideEffects())
return false;
- for (auto K : In.users()) {
+ for (auto *K : In.users()) {
Instruction *UseI = dyn_cast<Instruction>(K);
if (!UseI)
continue;
for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG))
Changed |= processBlock(BA);
- for (auto MI : Deleted)
+ for (auto *MI : Deleted)
MI->eraseFromParent();
if (Changed) {
}
MISet Erase;
- for (auto MI : SplitIns) {
+ for (auto *MI : SplitIns) {
if (isFixedInstr(MI)) {
collapseRegPairs(MI, PairMap);
} else {
for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
U != W; ++U)
Uses.insert(U->getParent());
- for (auto M : Uses)
+ for (auto *M : Uses)
replaceSubregUses(M, PairMap);
}
- for (auto MI : Erase) {
+ for (auto *MI : Erase) {
MachineBasicBlock *B = MI->getParent();
B->erase(MI);
}
MemoryLocation L(MMO.getValue(), MMO.getSize(), MMO.getAAInfo());
- for (auto SI : Stores) {
+ for (auto *SI : Stores) {
const MachineMemOperand &SMO = getStoreTarget(SI);
if (!SMO.getValue())
return true;
// Create a set of all instructions in OG (for quick lookup).
SmallPtrSet<MachineInstr*, 4> InstrSet;
- for (auto I : OG)
+ for (auto *I : OG)
InstrSet.insert(I);
// Traverse the block, until we hit an instruction from OG.
else
AtBBStart = true;
- for (auto I : OG)
+ for (auto *I : OG)
I->eraseFromParent();
if (!AtBBStart)
else
InsertAt = MBB->begin();
- for (auto I : NG)
+ for (auto *I : NG)
MBB->insert(InsertAt, I);
return true;
void HexagonPacketizerList::cleanUpDotCur() {
MachineInstr *MI = nullptr;
- for (auto BI : CurrentPacketMIs) {
+ for (auto *BI : CurrentPacketMIs) {
LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
if (HII->isDotCurInst(*BI)) {
MI = BI;
// Check for existing uses of a vector register within the packet which
// would be affected by converting a vector load into .cur formt.
- for (auto BI : CurrentPacketMIs) {
+ for (auto *BI : CurrentPacketMIs) {
LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
return false;
// New-value stores are of class NV (slot 0), dual stores require class ST
// in slot 0 (PRM 5.5).
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
SUnit *PacketSU = MIToSUnit.find(I)->second;
if (PacketSU->getInstr()->mayStore())
return false;
unsigned StartCheck = 0;
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
SUnit *TempSU = MIToSUnit.find(I)->second;
MachineInstr &TempMI = *TempSU->getInstr();
unsigned DepReg) {
SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
// We only care for dependencies to predicated instructions
if (!HII->isPredicated(*I))
continue;
// Analyze relationships between all existing members of the packet.
// Look for Anti dependecy on the same predicate reg as used in the
// candidate.
- for (auto I : CurrentPacketMIs) {
+ for (auto *I : CurrentPacketMIs) {
// Scheduling Unit for current insn in the packet.
SUnit *PacketSU = MIToSUnit.find(I)->second;
bool FoundLoad = false;
bool FoundStore = false;
- for (auto MJ : CurrentPacketMIs) {
+ for (auto *MJ : CurrentPacketMIs) {
unsigned Opc = MJ->getOpcode();
if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
continue;
// }
// Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
- for (auto J : CurrentPacketMIs) {
+ for (auto *J : CurrentPacketMIs) {
SUnit *SUJ = MIToSUnit[J];
for (auto &Pred : SUI->Preds)
if (Pred.getSUnit() == SUJ)
// Check if the latency is greater than one between this instruction and any
// instruction in the previous packet.
- for (auto J : OldPacketMIs) {
+ for (auto *J : OldPacketMIs) {
SUnit *SUJ = MIToSUnit[J];
for (auto &Pred : SUI->Preds)
if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
void finishLayout(MCAssembler const &Asm,
MCAsmLayout &Layout) const override {
- for (auto I : Layout.getSectionOrder()) {
+ for (auto *I : Layout.getSectionOrder()) {
auto &Fragments = I->getFragmentList();
for (auto &J : Fragments) {
switch (J.getKind()) {
}
MachineDomTreeNode *N = MDT.getNode(B);
- for (auto I : *N)
+ for (auto *I : *N)
Changed |= scanBlock(I->getBlock());
return Changed;
// Find and record all uses of this vector that extract element 0 or 1.
SmallVector<SDNode *, 4> E0, E1;
- for (auto U : Vector.getNode()->uses()) {
+ for (auto *U : Vector.getNode()->uses()) {
if (U->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
continue;
if (U->getOperand(0) != Vector)
TII = static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
MRI = &MF.getRegInfo();
- for (auto ML : MLI) {
+ for (auto *ML : MLI) {
if (ML->isOutermost())
Changed |= processLoop(ML);
}
// Note that LoopPredecessor might occur in the predecessor list multiple
// times, and we need to add it the right number of times.
- for (auto PI : predecessors(Header)) {
+ for (auto *PI : predecessors(Header)) {
if (PI != LoopPredecessor)
continue;
I8Ty, NewPHI, IncNode, getInstrName(BaseMemI, GEPNodeIncNameSuffix),
InsPoint);
cast<GetElementPtrInst>(PtrInc)->setIsInBounds(IsPtrInBounds(BasePtr));
- for (auto PI : predecessors(Header)) {
+ for (auto *PI : predecessors(Header)) {
if (PI == LoopPredecessor)
continue;
} else {
// Note that LoopPredecessor might occur in the predecessor list multiple
// times, and we need to make sure no more incoming value for them in PHI.
- for (auto PI : predecessors(Header)) {
+ for (auto *PI : predecessors(Header)) {
if (PI == LoopPredecessor)
continue;
// Is this ADD instruction only used as the base pointer of scalar loads and
// stores?
static bool isWorthFoldingAdd(SDValue Add) {
- for (auto Use : Add->uses()) {
+ for (auto *Use : Add->uses()) {
if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
Use->getOpcode() != ISD::ATOMIC_LOAD &&
Use->getOpcode() != ISD::ATOMIC_STORE)
}
bool MadeChange = false;
- for (auto MI : SExtWRemovalCands) {
+ for (auto *MI : SExtWRemovalCands) {
SmallPtrSet<MachineInstr *, 4> FixableDef;
Register SrcReg = MI->getOperand(1).getReg();
MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
BuildMI(MBB, Fixable, DL, ST.getInstrInfo()->get(Code));
for (auto Op : Fixable->operands())
Replacement.add(Op);
- for (auto Op : Fixable->memoperands())
+ for (auto *Op : Fixable->memoperands())
Replacement.addMemOperand(Op);
LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
// destination registers, and the registers that went into the PHI.
DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
- for (auto MI : Selects) {
+ for (auto *MI : Selects) {
Register DestReg = MI->getOperand(0).getReg();
Register TrueReg = MI->getOperand(1).getReg();
Register FalseReg = MI->getOperand(2).getReg();
NextMIIt->usesCustomInsertionHook())
break;
bool User = false;
- for (auto SelMI : Selects)
+ for (auto *SelMI : Selects)
if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) {
User = true;
break;
// ...
MBB = JoinMBB;
createPHIsForSelects(Selects, StartMBB, FalseMBB, MBB);
- for (auto SelMI : Selects)
+ for (auto *SelMI : Selects)
SelMI->eraseFromParent();
MachineBasicBlock::iterator InsertPos = MBB->getFirstNonPHI();
- for (auto DbgMI : DbgValues)
+ for (auto *DbgMI : DbgValues)
MBB->splice(InsertPos, StartMBB, DbgMI);
return JoinMBB;
SmallVector<MachineBasicBlock *, 8> Successors(MBB->succ_rbegin(),
MBB->succ_rend());
// FIXME: Avoid quadratic complexity.
- for (auto MBBS : Successors) {
+ for (auto *MBBS : Successors) {
if (MBBS->isEHPad()) {
MBB->removeSuccessor(MBBS);
MBBLPads.push_back(MBBS);
// any blocks deferred because the header didn't dominate them.
for (Entry &E : Entries)
if (E.TheRegion->contains(MBB) && --E.NumBlocksLeft == 0)
- for (auto DeferredBlock : E.Deferred)
+ for (auto *DeferredBlock : E.Deferred)
Ready.push(DeferredBlock);
while (!Entries.empty() && Entries.back().NumBlocksLeft == 0)
Entries.pop_back();
if (Region->isLoop()) {
// Loop header. The loop predecessor should be sorted above, and the
// other predecessors should be backedges below.
- for (auto Pred : MBB.predecessors())
+ for (auto *Pred : MBB.predecessors())
assert(
(Pred->getNumber() < MBB.getNumber() || Region->contains(Pred)) &&
"Loop header predecessors must be loop predecessors or "
"backedges");
} else {
// Exception header. All predecessors should be sorted above.
- for (auto Pred : MBB.predecessors())
+ for (auto *Pred : MBB.predecessors())
assert(Pred->getNumber() < MBB.getNumber() &&
"Non-loop-header predecessors should be topologically sorted");
}
} else {
// Not a region header. All predecessors should be sorted above.
- for (auto Pred : MBB.predecessors())
+ for (auto *Pred : MBB.predecessors())
assert(Pred->getNumber() < MBB.getNumber() &&
"Non-loop-header predecessors should be topologically sorted");
assert(OnStack.count(SRI.getRegionFor(&MBB)) &&
const MachineDominanceFrontier &MDF) {
// Postorder traversal of the dominator tree.
SmallVector<std::unique_ptr<WebAssemblyException>, 8> Exceptions;
- for (auto DomNode : post_order(&MDT)) {
+ for (auto *DomNode : post_order(&MDT)) {
MachineBasicBlock *EHPad = DomNode->getBlock();
if (!EHPad->isEHPad())
continue;
}
// Add BBs to exceptions' block vector
- for (auto DomNode : post_order(&MDT)) {
+ for (auto *DomNode : post_order(&MDT)) {
MachineBasicBlock *MBB = DomNode->getBlock();
WebAssemblyException *WE = getExceptionFor(MBB);
for (; WE; WE = WE->getParentException())
BlockVector SortedEntries = getSortedEntries(Entries);
#ifndef NDEBUG
- for (auto Block : SortedEntries)
+ for (auto *Block : SortedEntries)
assert(Block->getNumber() != -1);
if (SortedEntries.size() > 1) {
for (auto I = SortedEntries.begin(), E = SortedEntries.end() - 1; I != E;
const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
// Add an operand for each case.
- for (auto MBB : MBBs)
+ for (auto *MBB : MBBs)
Ops.push_back(DAG.getBasicBlock(MBB));
// Add the first MBB as a dummy default target for now. This will be replaced
SmallVector<MachineBasicBlock *, 8> Successors(MBB->succ_rbegin(),
MBB->succ_rend());
// FIXME: Avoid quadratic complexity.
- for (auto MBBS : Successors) {
+ for (auto *MBBS : Successors) {
if (MBBS->isEHPad()) {
MBB->removeSuccessor(MBBS);
MBBLPads.push_back(MBBS);
BestLEA = nullptr;
// Loop over all LEA instructions.
- for (auto DefMI : List) {
+ for (auto *DefMI : List) {
// Get new address displacement.
int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1);