Build fix/update of AFEB9260

Make AFEB9260 build again.
Based on fix for AT91SAM9260EK.

Signed-off-by: Sergey Lapin <slapin@ossfans.org>

diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
index 3c37557..f0e2e80 100644 (file)
--- a/board/afeb9260/afeb9260.c
+++ b/board/afeb9260/afeb9260.c
@@ -31,7 +31,7 @@
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 #include <asm/arch/hardware.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <netdev.h>
@@ -48,28 +48,28 @@ DECLARE_GLOBAL_DATA_PTR;
 static void afeb9260_nand_hw_init(void)
 {
        unsigned long csa;
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+       struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 
-       /* Enable CS3 */
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA,
-                      csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       /* Assign CS3 to NAND/SmartMedia Interface */
+       csa = readl(&matrix->ebicsa);
+       csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+       writel(csa, &matrix->ebicsa);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
-       at91_sys_write(AT91_SMC_SETUP(3),
-                      AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-                      AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-                      AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-                      AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-       at91_sys_write(AT91_SMC_MODE(3),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
-                      AT91_SMC_DBW_8 |
-                      AT91_SMC_TDF_(2));
-
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+               &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+               &smc->cs[3].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+               AT91_SMC_MODE_EXNW_DISABLE |
+               AT91_SMC_MODE_DBW_8 |
+               AT91_SMC_MODE_TDF_CYCLE(2),
+               &smc->cs[3].mode);
 
        /* Configure RDY/BSY */
        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -81,10 +81,15 @@ static void afeb9260_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void afeb9260_macb_hw_init(void)
 {
-       unsigned long rstc;
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+       unsigned long erstl;
+
+
+       /* Enable EMAC clock */
+       writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
-       /* Enable clock */
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
 
        /*
         * Disable pull-up on:
@@ -103,24 +108,22 @@ static void afeb9260_macb_hw_init(void)
               pin_to_mask(AT91_PIN_PA25) |
               pin_to_mask(AT91_PIN_PA26) |
               pin_to_mask(AT91_PIN_PA28),
-              pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+              &pioa->pudr);
 
-       rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 
        /* Need to reset PHY -> 500ms reset */
-       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-                                    AT91_RSTC_ERSTL | (0x0D << 8) |
-                                    AT91_RSTC_URSTEN);
-
-       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
+               AT91_RSTC_MR_URSTEN, &rstc->mr);
+       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 
        /* Wait for end hardware reset */
-       while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
+       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+               ;
        /* Restore NRST value */
-       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-                                    (rstc) |
-                                    AT91_RSTC_URSTEN);
+       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
+               &rstc->mr);
+
 
        /* Re-enable pull-up */
        writel(pin_to_mask(AT91_PIN_PA14) |
@@ -129,23 +132,29 @@ static void afeb9260_macb_hw_init(void)
               pin_to_mask(AT91_PIN_PA25) |
               pin_to_mask(AT91_PIN_PA26) |
               pin_to_mask(AT91_PIN_PA28),
-              pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+              &pioa->puer);
 
        at91_macb_hw_init();
 }
 #endif
-
+int board_early_init_f(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       /* Enable clocks for all PIOs */
+       writel((1 << ATMEL_ID_PIOA) |
+               (1 << ATMEL_ID_PIOB) |
+               (1 << ATMEL_ID_PIOC),
+               &pmc->pcer);
+       return 0;
+}
 int board_init(void)
 {
-       /* Enable Ctrlc */
-       console_init_f();
-
        /* arch number of AT91SAM9260EK-Board */
        gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
        /* adress of boot parameters */
-       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-       at91_serial_hw_init();
+       at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
        afeb9260_nand_hw_init();
 #endif
@@ -159,8 +168,10 @@ int board_init(void)
 
 int dram_init(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM;
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size(
+       (void *)CONFIG_SYS_SDRAM_BASE,
+               CONFIG_SYS_SDRAM_SIZE);
+
        return 0;
 }
 
@@ -174,7 +185,7 @@ int board_eth_init(bd_t *bis)
 {
        int rc = 0;
 #ifdef CONFIG_MACB
-       rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01);
+       rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01);
 #endif
        return rc;
 }

diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 36a2a46..2c2c077 100644 (file)
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -25,17 +25,21 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
+#define CONFIG_AT91SAM9260             /* Atmel AT91SAM9260 SoC*/
+#include <asm/arch/hardware.h>
 
-#define CONFIG_AT91_LEGACY
+#define CONFIG_SYS_TEXT_BASE           0x21f00000
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK             18429952        /* from 18.432 MHz crystal */
-#define CONFIG_SYS_HZ          1000
+#define CONFIG_SYS_AT91_SLOW_CLOCK             32768
+#define CONFIG_SYS_HZ                          1000
 
-#define CONFIG_AT91SAM9260     1       /* It's an Atmel AT91SAM9260 SoC*/
-#define CONFIG_AFEB9260                1       /* on an AFEB9260 Board */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_AFEB9260                        /* AFEB9260 Board       */
 #define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
 
 #define CONFIG_CMDLINE_TAG     1       /* enable passing of ATAGs      */
 #define CONFIG_SETUP_MEMORY_TAGS 1
@@ -46,12 +50,14 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_AT91_GPIO       1
-#define CONFIG_ATMEL_USART     1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#define CONFIG_USART3          1       /* USART 3 is DBGU */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_PULLUP     1
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE      ATMEL_BASE_DBGU
+#define CONFIG_USART_ID                ATMEL_ID_SYS
+#define CONFIG_USART3          /* USART 3 is DBGU */
 
 #define CONFIG_BOOTDELAY       3
 
@@ -74,20 +80,20 @@
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_SOURCE
 
-#define CONFIG_CMD_PING                1
-#define CONFIG_CMD_DHCP                1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
 
-#define CONFIG_CMD_NAND                1
-#define CONFIG_CMD_USB         1
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS           1
-#define PHYS_SDRAM                     0x20000000
-#define PHYS_SDRAM_SIZE                        0x04000000      /* 64 megs */
+#define CONFIG_SYS_SDRAM_BASE          ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE          0x04000000      /* 64 megs */
 
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
-#define CONFIG_HAS_DATAFLASH           1
+#define CONFIG_HAS_DATAFLASH
 #define CONFIG_SYS_SPI_WRITE_TOUT              (5 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS         2
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* CS0 */
@@ -100,8 +106,8 @@
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
 #define CONFIG_SYS_MAX_NAND_DEVICE             1
-#define CONFIG_SYS_NAND_BASE                   0x40000000
-#define CONFIG_SYS_NAND_DBW_8                  1
+#define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
 /* our CLE is AD22 */
@@ -112,37 +118,36 @@
 #endif
 
 /* NOR flash - no real flash on this board */
-#define CONFIG_SYS_NO_FLASH            1
+#define CONFIG_SYS_NO_FLASH
 
 /* Ethernet */
-#define CONFIG_MACB                    1
-#undef CONFIG_RMII                     /* We have full MII there */
-#define CONFIG_RESET_PHY_R             1
+#define CONFIG_MACB
+#define CONFIG_RESET_PHY_R
 
-#define CONFIG_NET_MULTI               1
+#define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT         20
 
 /* USB */
 #define CONFIG_USB_ATMEL
-#define CONFIG_USB_OHCI_NEW            1
-#define CONFIG_DOS_PARTITION           1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT           1
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
 #define CONFIG_SYS_USB_OHCI_REGS_BASE          0x00500000      /* AT91SAM9260_UHP_BASE */
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9260"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     1
-#define CONFIG_USB_STORAGE             1
+#define CONFIG_USB_STORAGE
 
 #define CONFIG_SYS_LOAD_ADDR                   0x21000000      /* load address */
 
-#define CONFIG_SYS_MEMTEST_START               PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START               CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END                 0x21e00000
 
-#undef CONFIG_SYS_USE_DATAFLASH_CS0
-#define CONFIG_SYS_USE_DATAFLASH_CS1           1
-#undef CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SYS_USE_DATAFLASH_CS1
+#define CONFIG_SYS_INIT_SP_ADDR                (ATMEL_BASE_SRAM1 + 0x1000 -\
+                                       GENERATED_GBL_DATA_SIZE)
 
 /* bootstrap + u-boot + env + linux in dataflash on CS1 */
-#define CONFIG_ENV_IS_IN_DATAFLASH     1
+#define CONFIG_ENV_IS_IN_DATAFLASH
 #define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
 #define CONFIG_ENV_OFFSET              0x4200
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
@@ -159,8 +164,8 @@
 #define CONFIG_SYS_CBSIZE              256
 #define CONFIG_SYS_MAXARGS             16
 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP            1
-#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
 
 /*
  * Size of malloc() pool
@@ -172,5 +177,4 @@
 #ifdef CONFIG_USE_IRQ
 #error CONFIG_USE_IRQ not supported
 #endif
-
 #endif