This reverts commit
a547b4e26b311e417cd51100e379693f51a3f448,
relanding commit
31d219d2997fed1b7dc97e0adf170d5aaf65883e,
which was reverted because there was a conflicting inverse transform,
which was causing an endless combine loop, which has now been adjusted.
Original commit message:
https://alive2.llvm.org/ce/z/67w-wQ
We prefer `add`s over `sub`, and this particular xform
allows further folds to happen:
Fixes https://bugs.llvm.org/show_bug.cgi?id=49858
// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
-// CHECK-LE-NEXT: [[VADDUQM_I_NEG:%.*]] = sub <1 x i128> [[TMP2]], [[TMP0]]
-// CHECK-LE-NEXT: [[VSUBUQM_I:%.*]] = sub <1 x i128> [[VADDUQM_I_NEG]], [[TMP1]]
+// CHECK-LE-NEXT: [[VADDUQM_I_NEG:%.*]] = add <1 x i128> [[TMP0]], [[TMP1]]
+// CHECK-LE-NEXT: [[VSUBUQM_I:%.*]] = sub <1 x i128> [[TMP2]], [[VADDUQM_I_NEG]]
// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[VSUBUQM_I]] to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8> [[TMP3]]
//
// CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
// CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
// CHECK-AIX-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
-// CHECK-AIX-NEXT: [[VADDUQM_I_NEG:%.*]] = sub <1 x i128> [[TMP2]], [[TMP0]]
-// CHECK-AIX-NEXT: [[VSUBUQM_I:%.*]] = sub <1 x i128> [[VADDUQM_I_NEG]], [[TMP1]]
+// CHECK-AIX-NEXT: [[VADDUQM_I_NEG:%.*]] = add <1 x i128> [[TMP0]], [[TMP1]]
+// CHECK-AIX-NEXT: [[VSUBUQM_I:%.*]] = sub <1 x i128> [[TMP2]], [[VADDUQM_I_NEG]]
// CHECK-AIX-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[VSUBUQM_I]] to <16 x i8>
// CHECK-AIX-NEXT: ret <16 x i8> [[TMP3]]
//
return BinaryOperator::CreateSub(XZ, YW);
}
+ // ((X - Y) - Op1) --> X - (Y + Op1)
+ if (match(Op0, m_OneUse(m_Sub(m_Value(X), m_Value(Y))))) {
+ Value *Add = Builder.CreateAdd(Y, Op1);
+ return BinaryOperator::CreateSub(X, Add);
+ }
+
auto m_AddRdx = [](Value *&Vec) {
return m_OneUse(m_Intrinsic<Intrinsic::vector_reduce_add>(m_Value(Vec)));
};
define i32 @nabs_canonical_9(i32 %a, i32 %b) {
; CHECK-LABEL: @nabs_canonical_9(
; CHECK-NEXT: [[T1:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = sub i32 [[B]], [[A]]
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[T1]], i1 false)
-; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[T2]], [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], [[A]]
+; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[B]], [[TMP2]]
; CHECK-NEXT: ret i32 [[ADD]]
;
%t1 = sub i32 %a, %b
; Basic test
define i8 @t0(i8 %x, i8 %y, i8 %z) {
; CHECK-LABEL: @t0(
-; CHECK-NEXT: [[I0:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[R:%.*]] = sub i8 [[I0]], [[Z:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[Y:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sub i8 [[X:%.*]], [[TMP1]]
; CHECK-NEXT: ret i8 [[R]]
;
%i0 = sub i8 %x, %y
; No flags are propagated
define i8 @t1_flags(i8 %x, i8 %y, i8 %z) {
; CHECK-LABEL: @t1_flags(
-; CHECK-NEXT: [[O0:%.*]] = sub nuw nsw i8 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[R:%.*]] = sub nuw nsw i8 [[O0]], [[Z:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[Y:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sub i8 [[X:%.*]], [[TMP1]]
; CHECK-NEXT: ret i8 [[R]]
;
%o0 = sub nuw nsw i8 %x, %y
define i8 @t3_c0(i8 %y, i8 %z) {
; CHECK-LABEL: @t3_c0(
-; CHECK-NEXT: [[I0:%.*]] = sub i8 42, [[Y:%.*]]
-; CHECK-NEXT: [[R:%.*]] = sub i8 [[I0]], [[Z:%.*]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[Y:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[R:%.*]] = sub i8 42, [[TMP1]]
; CHECK-NEXT: ret i8 [[R]]
;
%i0 = sub i8 42, %y