* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_WDT
+
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <syscon.h>
#include <wdt.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
val & (SR_PVU | SR_RVU), CONFIG_SYS_HZ);
if (ret < 0) {
- pr_err("Updating IWDG registers timeout");
+ dev_err(dev, "Updating IWDG registers timeout");
return -ETIMEDOUT;
}
struct clk clk;
int ret;
- debug("IWDG init\n");
+ dev_dbg(dev, "IWDG init\n");
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
priv->wdt_clk_rate = clk_get_rate(&clk);
- debug("IWDG init done\n");
+ dev_dbg(dev, "IWDG init done\n");
return 0;
}